679 lines
23 KiB
C++
679 lines
23 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <boost/range/adaptor/reversed.hpp>
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#include <cmath>
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#include <cstring>
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#include "gfx.h"
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#include "globals.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "router1.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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static std::tuple<int, int, std::string> split_identifier_name(const std::string &name)
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{
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size_t first_slash = name.find('/');
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NPNR_ASSERT(first_slash != std::string::npos);
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size_t second_slash = name.find('/', first_slash + 1);
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NPNR_ASSERT(second_slash != std::string::npos);
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return std::make_tuple(std::stoi(name.substr(1, first_slash)),
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std::stoi(name.substr(first_slash + 2, second_slash - first_slash)),
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name.substr(second_slash + 1));
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};
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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#if defined(_MSC_VER)
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void load_chipdb();
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#endif
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//#define LFE5U_45F_ONLY
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Arch::Arch(ArchArgs args) : args(args)
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{
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#if defined(_MSC_VER)
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load_chipdb();
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#endif
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#ifdef LFE5U_45F_ONLY
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if (args.type == ArchArgs::LFE5U_45F) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_45k));
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} else {
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log_error("Unsupported ECP5 chip type.\n");
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}
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#else
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if (args.type == ArchArgs::LFE5U_25F || args.type == ArchArgs::LFE5UM_25F || args.type == ArchArgs::LFE5UM5G_25F) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_25k));
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} else if (args.type == ArchArgs::LFE5U_45F || args.type == ArchArgs::LFE5UM_45F ||
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args.type == ArchArgs::LFE5UM5G_45F) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_45k));
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} else if (args.type == ArchArgs::LFE5U_85F || args.type == ArchArgs::LFE5UM_85F ||
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args.type == ArchArgs::LFE5UM5G_85F) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_85k));
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} else {
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log_error("Unsupported ECP5 chip type.\n");
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}
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#endif
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package_info = nullptr;
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for (int i = 0; i < chip_info->num_packages; i++) {
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if (args.package == chip_info->package_info[i].name.get()) {
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package_info = &(chip_info->package_info[i]);
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break;
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}
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}
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if (!package_info)
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log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
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bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr);
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const
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{
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if (args.type == ArchArgs::LFE5U_25F) {
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return "LFE5U-25F";
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} else if (args.type == ArchArgs::LFE5U_45F) {
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return "LFE5U-45F";
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} else if (args.type == ArchArgs::LFE5U_85F) {
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return "LFE5U-85F";
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} else if (args.type == ArchArgs::LFE5UM_25F) {
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return "LFE5UM-25F";
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} else if (args.type == ArchArgs::LFE5UM_45F) {
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return "LFE5UM-45F";
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} else if (args.type == ArchArgs::LFE5UM_85F) {
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return "LFE5UM-85F";
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} else if (args.type == ArchArgs::LFE5UM5G_25F) {
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return "LFE5UM5G-25F";
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} else if (args.type == ArchArgs::LFE5UM5G_45F) {
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return "LFE5UM5G-45F";
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} else if (args.type == ArchArgs::LFE5UM5G_85F) {
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return "LFE5UM5G-85F";
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} else {
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log_error("Unknown chip\n");
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}
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}
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const
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{
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if (args.type == ArchArgs::LFE5U_25F)
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return id("lfe5u_25f");
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if (args.type == ArchArgs::LFE5U_45F)
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return id("lfe5u_45f");
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if (args.type == ArchArgs::LFE5U_85F)
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return id("lfe5u_85f");
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if (args.type == ArchArgs::LFE5UM_25F)
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return id("lfe5um_25f");
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if (args.type == ArchArgs::LFE5UM_45F)
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return id("lfe5um_45f");
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if (args.type == ArchArgs::LFE5UM_85F)
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return id("lfe5um_85f");
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if (args.type == ArchArgs::LFE5UM5G_25F)
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return id("lfe5um5g_25f");
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if (args.type == ArchArgs::LFE5UM5G_45F)
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return id("lfe5um5g_45f");
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if (args.type == ArchArgs::LFE5UM5G_85F)
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return id("lfe5um5g_85f");
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return IdString();
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}
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// -----------------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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BelId ret;
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auto it = bel_by_name.find(name);
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if (it != bel_by_name.end())
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return it->second;
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Location loc;
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std::string basename;
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std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
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ret.location = loc;
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const LocationTypePOD *loci = locInfo(ret);
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for (int i = 0; i < loci->num_bels; i++) {
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if (std::strcmp(loci->bel_data[i].name.get(), basename.c_str()) == 0) {
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ret.index = i;
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break;
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}
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}
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if (ret.index >= 0)
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bel_by_name[name] = ret;
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return ret;
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor_tile = y * chip_info->width + x;
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br.e.cursor_tile = y * chip_info->width + x;
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br.b.cursor_index = 0;
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br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].num_bels - 1;
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br.b.chip = chip_info;
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br.e.chip = chip_info;
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if (br.e.cursor_index == -1)
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++br.e.cursor_index;
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else
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++br.e;
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return br;
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}
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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WireId ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin.index) {
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ret.location = bel.location + bel_wires[i].rel_wire_loc;
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ret.index = bel_wires[i].wire_index;
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break;
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}
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return ret;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].type);
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return PORT_INOUT;
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}
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// -----------------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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WireId ret;
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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return it->second;
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Location loc;
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std::string basename;
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std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
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ret.location = loc;
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const LocationTypePOD *loci = locInfo(ret);
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for (int i = 0; i < loci->num_wires; i++) {
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if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) {
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ret.index = i;
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ret.location = loc;
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break;
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}
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}
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if (ret.index >= 0)
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wire_by_name[name] = ret;
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else
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ret.location = Location();
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return ret;
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}
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// -----------------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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auto it = pip_by_name.find(name);
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if (it != pip_by_name.end())
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return it->second;
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PipId ret;
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Location loc;
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std::string basename;
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std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
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ret.location = loc;
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const LocationTypePOD *loci = locInfo(ret);
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for (int i = 0; i < loci->num_pips; i++) {
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PipId curr;
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curr.location = loc;
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curr.index = i;
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pip_by_name[getPipName(curr)] = curr;
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}
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if (pip_by_name.find(name) == pip_by_name.end())
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NPNR_ASSERT_FALSE_STR("no pip named " + name.str(this));
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return pip_by_name[name];
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}
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IdString Arch::getPipName(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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int x = pip.location.x;
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int y = pip.location.y;
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std::string src_name = getWireName(getPipSrcWire(pip)).str(this);
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std::replace(src_name.begin(), src_name.end(), '/', '.');
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std::string dst_name = getWireName(getPipDstWire(pip)).str(this);
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std::replace(dst_name.begin(), dst_name.end(), '/', '.');
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return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
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}
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// -----------------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pin_data[i].name.get() == pin) {
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BelId bel;
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bel.location = package_info->pin_data[i].abs_loc;
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bel.index = package_info->pin_data[i].bel_index;
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return bel;
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}
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}
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return BelId();
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}
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std::string Arch::getBelPackagePin(BelId bel) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (Location(package_info->pin_data[i].abs_loc) == bel.location &&
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package_info->pin_data[i].bel_index == bel.index) {
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return package_info->pin_data[i].name.get();
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}
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}
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return "";
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}
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int Arch::getPioBelBank(BelId bel) const
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{
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for (int i = 0; i < chip_info->num_pios; i++) {
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if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) {
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return chip_info->pio_info[i].bank;
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}
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}
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NPNR_ASSERT_FALSE("failed to find PIO");
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}
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std::string Arch::getPioFunctionName(BelId bel) const
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{
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for (int i = 0; i < chip_info->num_pios; i++) {
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if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) {
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const char *func = chip_info->pio_info[i].function_name.get();
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if (func == nullptr)
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return "";
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else
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return func;
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}
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}
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NPNR_ASSERT_FALSE("failed to find PIO");
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}
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BelId Arch::getPioByFunctionName(const std::string &name) const
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{
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for (int i = 0; i < chip_info->num_pios; i++) {
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const char *func = chip_info->pio_info[i].function_name.get();
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if (func != nullptr && func == name) {
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BelId bel;
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bel.location = chip_info->pio_info[i].abs_loc;
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bel.index = chip_info->pio_info[i].bel_index;
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return bel;
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}
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}
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return BelId();
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++) {
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IdString id;
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id.index = bel_wires[i].port;
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ret.push_back(id);
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}
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return ret;
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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if (loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[loc.y * chip_info->width + loc.x]];
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for (int i = 0; i < locI.num_bels; i++) {
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if (locI.bel_data[i].z == loc.z) {
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BelId bi;
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bi.location.x = loc.x;
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bi.location.y = loc.y;
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bi.index = i;
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return bi;
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}
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}
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return BelId();
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}
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// -----------------------------------------------------------------------
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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return 100 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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const auto &driver = net_info->driver;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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}
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
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// -----------------------------------------------------------------------
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bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
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bool Arch::route()
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{
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route_ecp5_globals(getCtx());
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assign_budget(getCtx(), true);
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return router1(getCtx(), Router1Cfg(getCtx()));
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}
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// -----------------------------------------------------------------------
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std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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{
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std::vector<GraphicElement> ret;
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if (decal.type == DecalId::TYPE_BEL) {
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BelId bel;
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bel.index = decal.z;
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bel.location = decal.location;
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int z = locInfo(bel)->bel_data[bel.index].z;
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auto bel_type = getBelType(bel);
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if (bel_type == id_TRELLIS_SLICE) {
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GraphicElement el;
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el.type = GraphicElement::TYPE_BOX;
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el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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el.x1 = bel.location.x + logic_cell_x1;
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el.x2 = bel.location.x + logic_cell_x2;
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el.y1 = bel.location.y + logic_cell_y1 + (z)*logic_cell_pitch;
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el.y2 = bel.location.y + logic_cell_y2 + (z)*logic_cell_pitch;
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ret.push_back(el);
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}
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if (bel_type == id_TRELLIS_IO) {
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GraphicElement el;
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el.type = GraphicElement::TYPE_BOX;
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el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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el.x1 = bel.location.x + logic_cell_x1;
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el.x2 = bel.location.x + logic_cell_x2;
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el.y1 = bel.location.y + logic_cell_y1 + (2 * z) * logic_cell_pitch;
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el.y2 = bel.location.y + logic_cell_y2 + (2 * z + 1) * logic_cell_pitch;
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ret.push_back(el);
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}
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}
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return ret;
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}
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DecalXY Arch::getBelDecal(BelId bel) const
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{
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DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_BEL;
|
|
decalxy.decal.location = bel.location;
|
|
decalxy.decal.z = bel.index;
|
|
decalxy.decal.active = (bel_to_cell.at(getBelFlatIndex(bel)) != nullptr);
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
|
|
|
|
DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
|
|
|
|
DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
|
{
|
|
// Data for -8 grade
|
|
if (cell->type == id_TRELLIS_SLICE) {
|
|
bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2";
|
|
if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0) {
|
|
if (toPort == id_F0) {
|
|
delay.delay = 180;
|
|
return true;
|
|
} else if (has_carry && toPort == id_F1) {
|
|
delay.delay = 500;
|
|
return true;
|
|
} else if (has_carry && toPort == id_FCO) {
|
|
delay.delay = 355;
|
|
return true;
|
|
} else if (toPort == id_OFX0) {
|
|
delay.delay = 306;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1) {
|
|
if (toPort == id_F1) {
|
|
delay.delay = 180;
|
|
return true;
|
|
} else if (has_carry && toPort == id_FCO) {
|
|
delay.delay = 355;
|
|
return true;
|
|
} else if (toPort == id_OFX0) {
|
|
delay.delay = 306;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (has_carry && fromPort == id_FCI) {
|
|
if (toPort == id_F0) {
|
|
delay.delay = 328;
|
|
return true;
|
|
} else if (toPort == id_F1) {
|
|
delay.delay = 349;
|
|
return true;
|
|
} else if (toPort == id_FCO) {
|
|
delay.delay = 56;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (fromPort == id_CLK && (toPort == id_Q0 || toPort == id_Q1)) {
|
|
delay.delay = 395;
|
|
return true;
|
|
}
|
|
|
|
if (fromPort == id_M0 && toPort == id_OFX0) {
|
|
delay.delay = 193;
|
|
return true;
|
|
}
|
|
#if 0 // FIXME
|
|
if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) {
|
|
delay.delay = 717;
|
|
return true;
|
|
}
|
|
#endif
|
|
if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
|
|
(fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
|
|
(fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
|
|
(fromPort == id_D0 && toPort == id_WADO0) || (fromPort == id_D1 && toPort == id_WDO2)) {
|
|
delay.delay = 0;
|
|
return true;
|
|
}
|
|
return false;
|
|
} else if (cell->type == id_DCCA) {
|
|
if (fromPort == id_CLKI && toPort == id_CLKO) {
|
|
delay.delay = 0;
|
|
return true;
|
|
}
|
|
return false;
|
|
} else if (cell->type == id_DP16KD) {
|
|
if (fromPort == id_CLKA) {
|
|
if (toPort.str(this).substr(0, 3) == "DOA") {
|
|
delay.delay = 4260;
|
|
return true;
|
|
}
|
|
} else if (fromPort == id_CLKB) {
|
|
if (toPort.str(this).substr(0, 3) == "DOB") {
|
|
delay.delay = 4280;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
} else {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
|
|
{
|
|
auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
|
|
|
|
if (cell->type == id_TRELLIS_SLICE) {
|
|
int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
|
|
if (port == id_CLK || port == id_WCK)
|
|
return TMG_CLOCK_INPUT;
|
|
if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
|
|
port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
|
|
return TMG_COMB_INPUT;
|
|
if (port == id_F0 && disconnected(id_A0) && disconnected(id_B0) && disconnected(id_C0) && disconnected(id_D0) &&
|
|
disconnected(id_FCI))
|
|
return TMG_IGNORE; // LUT with no inputs is a constant
|
|
if (port == id_F1 && disconnected(id_A1) && disconnected(id_B1) && disconnected(id_C1) && disconnected(id_D1) &&
|
|
disconnected(id_FCI))
|
|
return TMG_IGNORE; // LUT with no inputs is a constant
|
|
|
|
if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
|
|
return TMG_COMB_OUTPUT;
|
|
if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
|
|
(sd1 == 1 && port == id_M1)) {
|
|
clockPort = id_CLK;
|
|
return TMG_REGISTER_INPUT;
|
|
}
|
|
if (port == id_M0 || port == id_M1)
|
|
return TMG_COMB_INPUT;
|
|
if (port == id_Q0 || port == id_Q1) {
|
|
clockPort = id_CLK;
|
|
return TMG_REGISTER_OUTPUT;
|
|
}
|
|
|
|
if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 ||
|
|
port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
|
|
return TMG_COMB_OUTPUT;
|
|
|
|
if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
|
|
port == id_WAD3 || port == id_WRE) {
|
|
clockPort = id_WCK;
|
|
return TMG_REGISTER_INPUT;
|
|
}
|
|
|
|
NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'");
|
|
} else if (cell->type == id_TRELLIS_IO) {
|
|
if (port == id_T || port == id_I)
|
|
return TMG_ENDPOINT;
|
|
if (port == id_O)
|
|
return TMG_STARTPOINT;
|
|
return TMG_IGNORE;
|
|
} else if (cell->type == id_DCCA) {
|
|
if (port == id_CLKI)
|
|
return TMG_COMB_INPUT;
|
|
if (port == id_CLKO)
|
|
return TMG_COMB_OUTPUT;
|
|
return TMG_IGNORE;
|
|
} else if (cell->type == id_DP16KD) {
|
|
if (port == id_CLKA || port == id_CLKB)
|
|
return TMG_CLOCK_INPUT;
|
|
std::string port_name = port.str(this);
|
|
for (auto c : boost::adaptors::reverse(port_name)) {
|
|
if (std::isdigit(c))
|
|
continue;
|
|
if (c == 'A')
|
|
clockPort = id_CLKA;
|
|
else if (c == 'B')
|
|
clockPort = id_CLKB;
|
|
else
|
|
NPNR_ASSERT_FALSE_STR("bad ram port");
|
|
return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
|
|
}
|
|
NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
|
|
} else if (cell->type == id_MULT18X18D) {
|
|
return TMG_IGNORE; // FIXME
|
|
} else if (cell->type == id_ALU54B) {
|
|
return TMG_IGNORE; // FIXME
|
|
} else if (cell->type == id_EHXPLLL) {
|
|
return TMG_IGNORE;
|
|
} else {
|
|
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
|
|
}
|
|
}
|
|
|
|
std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
|
|
{
|
|
std::vector<std::pair<std::string, std::string>> ret;
|
|
auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
|
|
for (int i = 0; i < tileloc.num_tiles; i++) {
|
|
ret.push_back(std::make_pair(tileloc.tile_names[i].name.get(),
|
|
chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()));
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
GlobalInfoPOD Arch::globalInfoAtLoc(Location loc)
|
|
{
|
|
int locidx = loc.y * chip_info->width + loc.x;
|
|
return chip_info->location_glbinfo[locidx];
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|