16 lines
244 B
Verilog
16 lines
244 B
Verilog
module top (
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input clk,
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output [3:0] led
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);
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(* keep *)
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wire led_unused;
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wire gclk;
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clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk));
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//assign gclk = clk;
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attosoc soc(.clk(gclk), .led({led_unused, led}));
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endmodule
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