438 lines
19 KiB
C++
438 lines
19 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021-22 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "fabric_parsing.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "viaduct_api.h"
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#include "viaduct_helpers.h"
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#include <fstream>
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#define GEN_INIT_CONSTIDS
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#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
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#include "viaduct_constids.h"
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#include "fab_cfg.h"
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#include "fab_defs.h"
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#include "fasm.h"
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#include "pack.h"
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#include "validity_check.h"
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#include <boost/filesystem.hpp>
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct FabulousImpl : ViaductAPI
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{
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FabulousImpl(const dict<std::string, std::string> &args)
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{
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for (auto a : args) {
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if (a.first == "fasm")
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fasm_file = a.second;
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else
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log_error("unrecognised fabulous option '%s'\n", a.first.c_str());
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}
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}
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~FabulousImpl(){};
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void init(Context *ctx) override
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{
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init_uarch_constids(ctx);
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ViaductAPI::init(ctx);
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h.init(ctx);
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fab_root = get_env_var("FAB_ROOT", ", set it to the fabulous build output or project path");
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if (boost::filesystem::exists(fab_root + "/.FABulous"))
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is_new_fab = true;
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else
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is_new_fab = false;
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log_info("Detected FABulous %s format project.\n", is_new_fab ? "2.0" : "1.0");
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// To consider: a faster serialised form of the device data (like bba that other arches use) so we don't have to
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// go through the whole csv parsing malarkey each time
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blk_trk = std::make_unique<BlockTracker>(ctx, cfg);
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is_new_fab ? init_bels_v2() : init_bels_v1();
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init_pips();
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ctx->setDelayScaling(0.25, 0.5);
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}
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void pack() override { fabulous_pack(ctx, cfg); }
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void postRoute() override
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{
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if (!fasm_file.empty())
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fabulous_write_fasm(ctx, cfg, fasm_file);
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}
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void prePlace() override { assign_cell_info(); }
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bool isBelLocationValid(BelId bel) const override { return blk_trk->check_validity(bel, cfg, cell_tags); }
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private:
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FabricConfig cfg; // TODO: non-default config
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ViaductHelpers h;
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WireId global_clk_wire;
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std::string fasm_file;
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std::unique_ptr<BlockTracker> blk_trk;
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std::string get_env_var(const std::string &name, const std::string &prompt = "")
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{
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const char *var = getenv(name.c_str());
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if (var == nullptr)
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log_error("environment variable '%s' is not set%s\n", name.c_str(), prompt.c_str());
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return std::string(var);
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}
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std::ifstream open_data_rel(const std::string &postfix)
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{
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const std::string filename(fab_root + postfix);
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std::ifstream in(filename);
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if (!in)
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log_error("failed to open data file '%s' (is FAB_ROOT set correctly?)\n", filename.c_str());
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return in;
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}
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std::string fab_root;
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bool is_new_fab;
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pool<IdString> warned_beltypes;
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void add_pseudo_pip(WireId src, WireId dst, IdString pip_type)
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{
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const auto &src_data = ctx->wire_info(src);
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IdStringList pip_name = IdStringList::concat(ctx->getWireName(src), ctx->getWireName(dst));
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ctx->addPip(pip_name, pip_type, src, dst, ctx->getDelayFromNS(0.05), Loc(src_data.x, src_data.y, 0));
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}
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void handle_bel_ports(BelId bel, IdString tile, IdString bel_type, const std::vector<parser_view> &ports)
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{
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// TODO: improve the scalability here as we support more bel types
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IdString idx = ctx->getBelName(bel)[1];
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Loc loc = ctx->getBelLocation(bel);
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if (bel_type == id_IO_1_bidirectional_frame_config_pass) {
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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WireId port_wire = get_wire(tile, port_id, ctx->idf("W_IO_%s", port_id.c_str(ctx)));
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IdString pin = p.back(1).to_id(ctx);
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ctx->addBelPin(bel, pin, port_wire, pin.in(id_I, id_T) ? PORT_IN : PORT_OUT);
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}
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} else if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) {
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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WireId port_wire = get_wire(tile, port_id, port_id);
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IdString pin = p.back(2).to_id(ctx);
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ctx->addBelPin(bel, pin, port_wire, bel_type == id_OutPass4_frame_config ? PORT_IN : PORT_OUT);
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}
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} else if (bel_type == id_RegFile_32x4) {
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WireId clk_wire = get_wire(tile, id_CLK, id_REG_CLK);
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ctx->addBelInput(bel, id_CLK, clk_wire);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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// TODO: nicer way of determining port type?
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if (p[0] == 'D') {
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ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_WRITE_DATA));
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} else if (p[0] == 'W') {
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ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_WRITE_ADDRESS));
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} else if (p[1] == 'D') {
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ctx->addBelOutput(bel, port_id, get_wire(tile, port_id, id_READ_DATA));
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} else {
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ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_READ_ADDRESS));
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}
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}
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} else if (bel_type == id_MULADD) {
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// TODO: do DSPs need a clock too like regfiles?
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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if (p[0] == 'Q') {
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ctx->addBelOutput(bel, port_id, get_wire(tile, port_id, id_DSP_DATA_OUT));
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} else if (port_id == id_clr) {
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ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_DSP_CLR));
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} else {
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ctx->addBelInput(bel, port_id, get_wire(tile, port_id, id_DSP_DATA_IN));
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}
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}
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} else if (bel_type == id_MUX8LUT_frame_config) {
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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ctx->addBelPin(bel, port_id, get_wire(tile, port_id, ctx->idf("LUTMUX_%s", port_id.c_str(ctx))),
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p[0] == 'M' ? PORT_OUT : PORT_IN);
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}
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} else if (bel_type == id_FABULOUS_LC) {
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// TODO: split LC mode, LUT permutation pseudo-switchbox, LUT thru pseudo-pips
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WireId clk_wire = get_wire(tile, ctx->idf("L%s_CLK", idx.c_str(ctx)), id_LUT_CLK);
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ctx->addBelInput(bel, id_CLK, clk_wire);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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blk_trk->set_bel_type(bel, BelFlags::BLOCK_CLB, BelFlags::FUNC_LC_COMB, loc.z);
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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WireId port_wire = get_wire(tile, port_id, ctx->idf("LUT_%s", port_id.c_str(ctx)));
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// TODO: more robust port name handling
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if (p[3] == 'S' || p[3] == 'E' || p[3] == 'I') { // set/reset, enable, LUT input
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ctx->addBelInput(bel, p.substr(3).to_id(ctx), port_wire);
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} else if (p[3] == 'O') { // LUT otuput
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ctx->addBelOutput(bel, p.substr(3, 1).to_id(ctx), port_wire);
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} else if (p[3] == 'C') { // carry chain
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if (p[4] == 'i') {
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ctx->addBelInput(bel, id_Ci, port_wire);
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} else {
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NPNR_ASSERT(p[4] == 'o');
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ctx->addBelOutput(bel, id_Co, port_wire);
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}
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} else {
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log_error("don't know what to do with LC port '%s'\n", port_id.c_str(ctx));
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}
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}
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} else {
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// ...
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if (!warned_beltypes.count(bel_type) && !ports.empty()) {
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log_warning("don't know how to handle ports for bel type '%s'\n", bel_type.c_str(ctx));
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warned_beltypes.insert(bel_type);
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}
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}
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}
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void init_global_clock()
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{
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// TODO: how do we extend this to more complex clocking topologies?
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BelId global_clk_bel =
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ctx->addBel(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_Global_Clock, Loc(0, 0, 0), true, false);
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global_clk_wire = ctx->addWire(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_CLK, 0, 0);
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ctx->addBelOutput(global_clk_bel, id_CLK, global_clk_wire);
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}
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// TODO: this is for legacy fabulous only, the new code path can be a lot simpler
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void init_bels_v1()
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{
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std::ifstream in = open_data_rel("/npnroutput/bel.txt");
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CsvParser csv(in);
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init_global_clock();
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while (csv.fetch_next_line()) {
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IdString tile = csv.next_field().to_id(ctx);
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int bel_x = csv.next_field().substr(1).to_int();
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int bel_y = csv.next_field().substr(1).to_int();
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auto bel_idx = csv.next_field();
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IdString bel_type = csv.next_field().to_id(ctx);
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NPNR_ASSERT(bel_idx.size() == 1);
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int bel_z = bel_idx[0] - 'A';
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NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
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/*
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In the future we will need to handle optionally splitting SLICEs into separate LUT/COMB and FF bels
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This is the preferred approach in nextpnr for arches where the LUT and FF can be used separately of
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each other (e.g. there is a way of routing the LUT and FF outputs individually, and some extra
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optional FF input).
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While this isn't yet the standard fabulous SLICE, it should be considered as a future option in fabulous.
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*/
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Loc loc(bel_x, bel_y, bel_z);
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BelId bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type, loc, false, false);
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std::vector<parser_view> ports;
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parser_view port;
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while (!(port = csv.next_field()).empty()) {
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ports.push_back(port);
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}
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handle_bel_ports(bel, tile, bel_type, ports);
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}
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postprocess_bels();
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}
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void init_bels_v2()
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{
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std::ifstream in = open_data_rel("/.FABulous/bel.v2.txt");
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CsvParser csv(in);
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init_global_clock();
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BelId curr_bel;
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while (csv.fetch_next_line()) {
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IdString cmd = csv.next_field().to_id(ctx);
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if (cmd == id_BelBegin) {
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IdString tile = csv.next_field().to_id(ctx);
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auto bel_idx = csv.next_field();
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IdString bel_type = csv.next_field().to_id(ctx);
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NPNR_ASSERT(bel_idx.size() == 1);
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int bel_z = bel_idx[0] - 'A';
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NPNR_ASSERT(bel_z >= 0 && bel_z < 26);
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Loc loc = tile_loc(tile);
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curr_bel = ctx->addBel(IdStringList::concat(tile, bel_idx.to_id(ctx)), bel_type,
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Loc(loc.x, loc.y, bel_z), false, false);
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} else if (cmd.in(id_I, id_O)) {
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IdString port = csv.next_field().to_id(ctx);
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auto wire_name = csv.next_field().split('.');
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WireId wire =
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get_wire(wire_name.first.to_id(ctx), wire_name.second.to_id(ctx), wire_name.second.to_id(ctx));
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ctx->addBelPin(curr_bel, port, wire, cmd == id_O ? PORT_OUT : PORT_IN);
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} else if (cmd == id_GlobalClk) {
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IdStringList bel_name = ctx->getBelName(curr_bel);
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WireId clk_wire = get_wire(bel_name[0], ctx->idf("%s_CLK", bel_name[1].c_str(ctx)), id_REG_CLK);
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ctx->addBelInput(curr_bel, id_CLK, clk_wire);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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} else if (cmd == id_CFG) {
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// TODO...
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} else if (cmd == id_BelEnd) {
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curr_bel = BelId();
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} else if (cmd != IdString()) {
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log_error("unsupported command %s in definition of bel %s\n", cmd.c_str(ctx),
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curr_bel == BelId() ? "<none>" : ctx->nameOfBel(curr_bel));
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}
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}
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postprocess_bels();
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}
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void generate_split_mux8(BelId bel)
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{
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// _don't_ take a reference here because it might be invalidated by adding bels
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auto data = ctx->bel_info(bel);
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const std::array<IdString, 4> mux_outs{id_M_AB, id_M_AD, id_M_EF, id_M_AH};
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for (unsigned k = 1; k <= 3; k++) {
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// create MUX2 through 8
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unsigned m = (1U << k);
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for (unsigned i = 0; i < 8; i += m) {
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// mux indexing scheme
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// - MUX2s are at (z % 2) == 0
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// - MUX4s are at (z % 4) == 1
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// - MUX8s are at (z % 8) == 7
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int idx = (m == 2) ? i : (m == 4) ? (i + 1) : (i + 7);
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BelId mux =
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ctx->addBel(IdStringList::concat(data.name[0], ctx->idf("MUX%d_%d", m, i)),
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ctx->idf("FABULOUS_MUX%d", m), Loc(data.x, data.y, data.z + 1 + idx), false, false);
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blk_trk->set_bel_type(mux, BelFlags::BLOCK_CLB, BelFlags::FUNC_MUX, idx);
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// M data inputs
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for (unsigned j = 0; j < m; j++) {
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ctx->addBelInput(mux, ctx->idf("I%d", j), data.pins.at(ctx->idf("%c", char('A' + i + j))).wire);
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}
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// K select inputs
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for (unsigned j = 0; j < k; j++) {
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ctx->addBelInput(mux, ctx->idf("S%d", j),
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data.pins.at(ctx->idf("S%d", (m == 8 && j == 2) ? 3 : ((i / m) * k + j))).wire);
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}
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// Output
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IdString output = (m == 2) ? mux_outs.at(i / m)
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: (m == 4) ? mux_outs.at((i / m) * k + 1)
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: mux_outs.at(3);
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ctx->addBelOutput(mux, id_O, data.pins.at(output).wire);
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}
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}
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}
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void postprocess_bels()
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{
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// This does some post-processing on bels to make them useful for nextpnr place-and-route regardless of the code
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// path that creates them. In the future, splitting muxes and creating split LCs would be done here, too
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for (auto bel : ctx->getBels()) {
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// _don't_ take a reference here because it might be invalidated by adding bels
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auto data = ctx->bel_info(bel);
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if (data.type == id_FABULOUS_LC) {
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if (!data.pins.count(id_Q)) {
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// Add a Q pseudo-pin and pseudo-pip from Q to O
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WireId o_wire = ctx->getBelPinWire(bel, id_O);
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IdString q_name = ctx->idf("%s_Q", data.name[1].c_str(ctx));
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WireId q_wire = get_wire(data.name[0], q_name, q_name);
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ctx->addBelOutput(bel, id_Q, q_wire);
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// Pseudo-pip for FF mode
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add_pseudo_pip(q_wire, o_wire, id_O2Q);
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}
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} else if (data.type.in(id_MUX8LUT_frame_config, id_MUX8LUT_frame_config_mux)) {
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generate_split_mux8(bel);
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ctx->bel_info(bel).hidden = true;
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} else if (data.type == id_IO_1_bidirectional_frame_config_pass) {
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if (!data.pins.count(id_PAD)) {
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// Add a PAD pseudo-pin for the top level
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ctx->addBelInout(bel, id_PAD,
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get_wire(data.name[0], ctx->idf("PAD_%s", data.name[1].c_str(ctx)), id_PAD));
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}
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}
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}
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}
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void init_pips()
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{
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std::ifstream in = open_data_rel(is_new_fab ? "/.FABulous/pips.txt" : "/npnroutput/pips.txt");
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CsvParser csv(in);
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while (csv.fetch_next_line()) {
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IdString src_tile = csv.next_field().to_id(ctx);
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IdString src_port = csv.next_field().to_id(ctx);
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IdString dst_tile = csv.next_field().to_id(ctx);
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IdString dst_port = csv.next_field().to_id(ctx);
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int delay = csv.next_field().to_int();
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IdString pip_name = csv.next_field().to_id(ctx);
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WireId src_wire = get_wire(src_tile, src_port, src_port);
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WireId dst_wire = get_wire(dst_tile, dst_port, dst_port);
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ctx->addPip(IdStringList::concat(src_tile, pip_name), pip_name, src_wire, dst_wire,
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ctx->getDelayFromNS(0.01 * delay), tile_loc(src_tile));
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}
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}
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// Fast lookup of tile names to XY pairs
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dict<IdString, Loc> tile2loc;
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Loc tile_loc(IdString tile)
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{
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if (!tile2loc.count(tile)) {
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std::string tile_name = tile.str(ctx);
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parser_view view(tile_name);
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NPNR_ASSERT(view[0] == 'X');
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size_t ypos = view.find('Y');
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NPNR_ASSERT(ypos != parser_view::npos);
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int x = view.substr(1, ypos - 1).to_int();
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int y = view.substr(ypos + 1).to_int();
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tile2loc[tile] = Loc(x, y, 0);
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}
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return tile2loc.at(tile);
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}
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// Create a wire if it doesn't exist, otherwise just return it
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WireId get_wire(IdString tile, IdString wire, IdString type)
|
|
{
|
|
// Create a wire name by using the built-in IdStringList mechanism to store a (tile, wire) pair
|
|
// this way we don't store a full string in memory of every concatenated wire name, reducing the memory
|
|
// footprint and start time significantly beyond the ~1k LUT scale
|
|
auto wire_name = IdStringList::concat(tile, wire);
|
|
auto found = ctx->wire_by_name.find(wire_name);
|
|
if (found != ctx->wire_by_name.end())
|
|
return found->second;
|
|
// doesn't exist
|
|
Loc loc = tile_loc(tile);
|
|
return ctx->addWire(wire_name, type, loc.x, loc.y);
|
|
}
|
|
|
|
CellTagger cell_tags;
|
|
void assign_cell_info()
|
|
{
|
|
for (auto &cell : ctx->cells) {
|
|
cell_tags.assign_for(ctx, cfg, cell.second.get());
|
|
}
|
|
}
|
|
void notifyBelChange(BelId bel, CellInfo *cell)
|
|
{
|
|
CellInfo *old = ctx->getBoundBelCell(bel);
|
|
blk_trk->update_bel(bel, old, cell);
|
|
}
|
|
};
|
|
|
|
struct FabulousArch : ViaductArch
|
|
{
|
|
FabulousArch() : ViaductArch("fabulous"){};
|
|
std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
|
|
{
|
|
return std::make_unique<FabulousImpl>(args);
|
|
}
|
|
} fabulousArch;
|
|
} // namespace
|
|
|
|
NEXTPNR_NAMESPACE_END
|