116 lines
4.1 KiB
C
116 lines
4.1 KiB
C
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#ifndef ICE40_CELLS_H
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#define ICE40_CELLS_H
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NEXTPNR_NAMESPACE_BEGIN
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// Create a standard iCE40 cell and return it
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// Name will be automatically assigned if not specified
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CellInfo *create_ice_cell(Context *ctx, IdString type,
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IdString name = IdString());
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// Return true if a cell is a LUT
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inline bool is_lut(const Context *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("SB_LUT4");
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}
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// Return true if a cell is a flipflop
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inline bool is_ff(const Context *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("SB_DFF") ||
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cell->type == ctx->id("SB_DFFE") ||
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cell->type == ctx->id("SB_DFFSR") ||
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cell->type == ctx->id("SB_DFFR") ||
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cell->type == ctx->id("SB_DFFSS") ||
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cell->type == ctx->id("SB_DFFS") ||
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cell->type == ctx->id("SB_DFFESR") ||
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cell->type == ctx->id("SB_DFFER") ||
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cell->type == ctx->id("SB_DFFESS") ||
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cell->type == ctx->id("SB_DFFES") ||
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cell->type == ctx->id("SB_DFFN") ||
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cell->type == ctx->id("SB_DFFNE") ||
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cell->type == ctx->id("SB_DFFNSR") ||
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cell->type == ctx->id("SB_DFFNR") ||
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cell->type == ctx->id("SB_DFFNSS") ||
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cell->type == ctx->id("SB_DFFNS") ||
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cell->type == ctx->id("SB_DFFNESR") ||
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cell->type == ctx->id("SB_DFFNER") ||
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cell->type == ctx->id("SB_DFFNESS") ||
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cell->type == ctx->id("SB_DFFNES");
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}
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// Return true if a cell is a SB_IO
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inline bool is_sb_io(const Context *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("SB_IO");
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}
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// Return true if a cell is a global buffer
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inline bool is_gbuf(const Context *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("SB_GB");
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}
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// Return true if a cell is a RAM
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inline bool is_ram(const Context *ctx, const CellInfo *cell)
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{
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return cell->type == ctx->id("SB_RAM40_4K") ||
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cell->type == ctx->id("SB_RAM40_4KNR") ||
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cell->type == ctx->id("SB_RAM40_4KNW") ||
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cell->type == ctx->id("SB_RAM40_4KNRNW");
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}
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// Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports
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// as needed. Set no_dff if a DFF is not being used, so that the output
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// can be reconnected
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc,
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bool no_dff = true);
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// Convert a SB_DFFx primitive to (part of) an ICESTORM_LC, setting parameters
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// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
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// be configured as pass through and D connected to I0, otherwise D will be
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// ignored
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void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
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bool pass_thru_lut = false);
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// Convert a nextpnr IO buffer to a SB_IO
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void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio);
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// Return true if a net is a global net
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bool is_global_net(const Context *ctx, const NetInfo *net);
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// Return true if a port is a clock port
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bool is_clock_port(const Context *ctx, const PortRef &port);
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// Return true if a port is a reset port
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bool is_reset_port(const Context *ctx, const PortRef &port);
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// Return true if a port is a clock enable port
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bool is_enable_port(const Context *ctx, const PortRef &port);
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NEXTPNR_NAMESPACE_END
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#endif
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