77 lines
2.1 KiB
Markdown
77 lines
2.1 KiB
Markdown
## FPGA interchange instructions
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These are instructions on how to get the dependencies, generate the FPGA interchange architecture build system and
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run some example designs.
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### Installing dependencies
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Install java and javac if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install openjdk-10-jdk
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```
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Install capnproto if not already installed. Version 0.8.0 is required.
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As stated in the [official instructions](https://capnproto.org/install.html), the version on the common package managers
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might not be up to date with the latest version, hence it is suggested to install
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from the archive or, in alternative, directly from the git repository.
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Install capnproto-java if not already installed:
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```
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git clone https://github.com/capnproto/capnproto-java.git
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cd capnproto-java
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make
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sudo make install
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```
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Install python-fpga-interchange if not already installed:
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```
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git clone https://github.com/SymbiFlow/python-fpga-interchange.git
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cd python-fpga-interchange.git
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#
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# Note: Recommend checking out a specific release, for example:
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#
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# git checkout v0.0.5
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#
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# Release of python-fpga-interchange library does have to match nextpnr
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# implementation.
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python -m pip install -e .
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```
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Clone RapidWright, if not already cloned:
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```
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git clone https://github.com/Xilinx/RapidWright.git
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cd RapidWright
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make update_jars
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```
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### Build instructions
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Once dependencies are installed/cloned, configure the build system for the FPGA interchange.
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From the nextpnr root dir run:
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```
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mkdir build
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cd build
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cmake .. --DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=<RapidWright path> -DINTERCHANGE_SCHEMA_PATH=<fpga-interchange-schema path> -DPYTHON_INTERCHANGE_PATH=<python-fpga-interchange path>
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```
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To build the xc7a35t architecture, run:
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```
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make chipdb-xc7a35t-bin
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```
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To build the example designs run:
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```
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make test-fpga_interchange-wire_arty-dcp
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```
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The make targets for the example designs follow the same pattern: `test-fpga_interchange-<test_name>-<output>`, where `output` is the name of the intermediate step of the build which can be:
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- `json`: synthesis output
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- `netlist`: logical netlist
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- `phys`: physical netlist
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- `dcp`: design checkpoint
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