411 lines
19 KiB
C++
411 lines
19 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct MistralBitgen
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{
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MistralBitgen(Context *ctx) : ctx(ctx), cv(ctx->cyclonev){};
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Context *ctx;
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CycloneV *cv;
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void init()
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{
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ctx->init_base_bitstream();
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// Default options
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cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
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if (!ctx->setting<bool>("compress_rbf", false))
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cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
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cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
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cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
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cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
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cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
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cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
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cv->opt_b_set(CycloneV::NCEO_DIS, true);
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cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
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cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
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if (!ctx->setting<bool>("compress_rbf", false))
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cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
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else
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cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
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cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
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cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
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cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
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// Default inversion
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write_default_inv();
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}
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void write_default_inv()
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{
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// Some PNODEs are inverted by default. Set them up here.
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for (const auto &pn2r : cv->get_all_p2r()) {
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const auto &pn = pn2r.first;
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auto pt = CycloneV::pn2pt(pn);
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auto pi = CycloneV::pn2pi(pn);
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switch (CycloneV::pn2bt(pn)) {
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case CycloneV::HMC: {
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// HMC OE are inverted to set OE=0, i.e. unused pins floating
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// TODO: handle the case when we are using the HMC or HMC bypass
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std::string name(CycloneV::port_type_names[pt]);
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if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
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continue;
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cv->inv_set(pn2r.second, true);
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break;
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};
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// HPS IO - TODO: what about when we actually support the HPS primitives?
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case CycloneV::HPS_BOOT: {
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switch (pt) {
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case CycloneV::CSEL_EN:
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case CycloneV::BSEL_EN:
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case CycloneV::BOOT_FROM_FPGA_READY:
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case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
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cv->inv_set(pn2r.second, true);
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break;
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case CycloneV::CSEL:
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if (pi < 2)
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cv->inv_set(pn2r.second, true);
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break;
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case CycloneV::BSEL:
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if (pi < 3)
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cv->inv_set(pn2r.second, true);
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break;
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default:
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break;
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};
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break;
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};
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case CycloneV::HPS_CROSS_TRIGGER: {
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if (pt == CycloneV::CLK_EN)
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cv->inv_set(pn2r.second, true);
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break;
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};
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case CycloneV::HPS_TEST: {
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if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
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cv->inv_set(pn2r.second, true);
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break;
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};
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case CycloneV::GPIO: {
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// Ignore GPIO used by the design
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BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
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CycloneV::pn2bi(pn));
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if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
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continue;
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// Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
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// Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
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// GND, presumably for power/EMI reasons
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bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
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if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
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continue;
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if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
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continue;
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cv->inv_set(pn2r.second, true);
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break;
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};
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case CycloneV::FPLL: {
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if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
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cv->inv_set(pn2r.second, true);
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break;
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};
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default:
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break;
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}
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}
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}
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void write_dqs()
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{
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for (auto pos : cv->dqs16_get_pos()) {
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int x = CycloneV::pos2x(pos), y = CycloneV::pos2y(pos);
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// DQS bypass for used output pins
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for (int z = 0; z < 16; z++) {
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int ioy = y + (z / 4) - 2;
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if (ioy < 0 || ioy >= int(cv->get_tile_sy()))
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continue;
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BelId bel = ctx->bel_by_block_idx(x, ioy, id_MISTRAL_IO, z % 4);
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if (bel == BelId())
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continue;
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CellInfo *ci = ctx->getBoundBelCell(bel);
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if (ci == nullptr || (ci->type != id_MISTRAL_IO && ci->type != id_MISTRAL_OB))
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continue; // not an output
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cv->bmux_m_set(CycloneV::DQS16, pos, CycloneV::INPUT_REG4_SEL, z, CycloneV::SEL_LOCKED_DPA);
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cv->bmux_r_set(CycloneV::DQS16, pos, CycloneV::RB_T9_SEL_EREG_CFF_DELAY, z, 0x1f);
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}
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}
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}
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void write_routing()
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{
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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for (auto &wire : ni->wires) {
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PipId pip = wire.second.pip;
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if (pip == PipId())
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continue;
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WireId src = ctx->getPipSrcWire(pip), dst = ctx->getPipDstWire(pip);
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// Only write out routes that are entirely in the Mistral domain. Everything else is dealt with
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// specially
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if (src.is_nextpnr_created() || dst.is_nextpnr_created())
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continue;
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cv->rnode_link(src.node, dst.node);
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}
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}
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}
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void write_io_cell(CellInfo *ci, int x, int y, int bi)
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{
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bool is_output =
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(ci->type == id_MISTRAL_OB || (ci->type == id_MISTRAL_IO && get_net_or_empty(ci, id_OE) != nullptr));
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auto pos = CycloneV::xy2pos(x, y);
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// TODO: configurable pull, IO standard, etc
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cv->bmux_b_set(CycloneV::GPIO, pos, CycloneV::USE_WEAK_PULLUP, bi, false);
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if (is_output) {
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cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::DRIVE_STRENGTH, bi, CycloneV::V3P3_LVTTL_16MA_LVCMOS_2MA);
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cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::IOCSR_STD, bi, CycloneV::DIS);
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}
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// There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
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// prevent a single bitflip from turning inputs to outputs and messing up other devices on the boards, notably
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// ECP5 does similar. OEIN.0 inverted for outputs; OEIN.1 for inputs
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cv->inv_set(cv->pnode_to_rnode(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, is_output ? 0 : 1)),
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true);
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}
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void write_clkbuf_cell(CellInfo *ci, int x, int y, int bi)
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{
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(void)ci; // currently unused
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auto pos = CycloneV::xy2pos(x, y);
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cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing
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cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
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}
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void write_cells()
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{
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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Loc loc = ctx->getBelLocation(ci->bel);
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int bi = ctx->bel_data(ci->bel).block_index;
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if (ctx->is_io_cell(ci->type))
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write_io_cell(ci, loc.x, loc.y, bi);
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else if (ctx->is_clkbuf_cell(ci->type))
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write_clkbuf_cell(ci, loc.x, loc.y, bi);
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}
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}
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bool write_alm(uint32_t lab, uint8_t alm)
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{
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auto &alm_data = ctx->labs.at(lab).alms.at(alm);
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auto block_type = ctx->labs.at(lab).is_mlab ? CycloneV::MLAB : CycloneV::LAB;
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std::array<CellInfo *, 2> luts{ctx->getBoundBelCell(alm_data.lut_bels[0]),
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ctx->getBoundBelCell(alm_data.lut_bels[1])};
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std::array<CellInfo *, 4> ffs{
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ctx->getBoundBelCell(alm_data.ff_bels[0]), ctx->getBoundBelCell(alm_data.ff_bels[1]),
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ctx->getBoundBelCell(alm_data.ff_bels[2]), ctx->getBoundBelCell(alm_data.ff_bels[3])};
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// Skip empty ALMs
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if (std::all_of(luts.begin(), luts.end(), [](CellInfo *c) { return !c; }) &&
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std::all_of(ffs.begin(), ffs.end(), [](CellInfo *c) { return !c; }))
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return false;
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bool is_lutram =
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(luts[0] && luts[0]->combInfo.mlab_group != -1) || (luts[1] && luts[1]->combInfo.mlab_group != -1);
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auto pos = alm_data.lut_bels[0].pos;
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if (is_lutram) {
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for (int i = 0; i < 10; i++) {
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// Many MLAB settings apply to the whole LAB, not just the ALM
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cv->bmux_m_set(block_type, pos, CycloneV::MODE, i, CycloneV::RAM);
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cv->bmux_n_set(block_type, pos, CycloneV::T_FEEDBACK_SEL, i, 1);
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}
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cv->bmux_r_set(block_type, pos, CycloneV::LUT_MASK, alm, 0xFFFFFFFFFFFFFFFFULL); // TODO: LUTRAM init
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cv->bmux_b_set(block_type, pos, CycloneV::BPKREG1, alm, true);
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cv->bmux_b_set(block_type, pos, CycloneV::TPKREG0, alm, true);
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cv->bmux_m_set(block_type, pos, CycloneV::MCRG_VOLTAGE, 0, CycloneV::VCCL);
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cv->bmux_b_set(block_type, pos, CycloneV::RAM_DIS, 0, false);
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cv->bmux_b_set(block_type, pos, CycloneV::WRITE_EN, 0, true);
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cv->bmux_n_set(block_type, pos, CycloneV::WRITE_PULSE_LENGTH, 0, 650); // picoseconds, presumably
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// TODO: understand how these enables really work
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cv->bmux_b_set(block_type, pos, CycloneV::EN2_EN, 0, false);
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cv->bmux_b_set(block_type, pos, CycloneV::EN_SCLK_LOAD_WHAT, 0, true);
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cv->bmux_m_set(block_type, pos, CycloneV::SCLR_MUX, 0, CycloneV::GIN2);
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} else {
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// Combinational mode - TODO: flop feedback
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cv->bmux_m_set(block_type, pos, CycloneV::MODE, alm, alm_data.l6_mode ? CycloneV::L6 : CycloneV::L5);
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// LUT function
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cv->bmux_r_set(block_type, pos, CycloneV::LUT_MASK, alm, ctx->compute_lut_mask(lab, alm));
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}
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// DFF/LUT output selection
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const std::array<CycloneV::bmux_type_t, 6> mux_settings{CycloneV::TDFF0, CycloneV::TDFF1, CycloneV::TDFF1L,
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CycloneV::BDFF0, CycloneV::BDFF1, CycloneV::BDFF1L};
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const std::array<CycloneV::port_type_t, 6> mux_port{CycloneV::FFT0, CycloneV::FFT1, CycloneV::FFT1L,
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CycloneV::FFB0, CycloneV::FFB1, CycloneV::FFB1L};
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for (int i = 0; i < 6; i++) {
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if (ctx->wires_connected(alm_data.comb_out[i / 3], ctx->get_port(block_type, CycloneV::pos2x(pos),
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CycloneV::pos2y(pos), alm, mux_port[i])))
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cv->bmux_m_set(block_type, pos, mux_settings[i], alm, CycloneV::NLUT);
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}
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bool is_carry = (luts[0] && luts[0]->combInfo.is_carry) || (luts[1] && luts[1]->combInfo.is_carry);
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if (is_carry)
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cv->bmux_m_set(block_type, pos, CycloneV::ARITH_SEL, alm, CycloneV::ADDER);
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// The carry in/out enable bits
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if (is_carry && alm == 0 && !luts[0]->combInfo.carry_start)
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cv->bmux_b_set(block_type, pos, CycloneV::TTO_DIS, 0, true);
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if (is_carry && alm == 5)
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cv->bmux_b_set(block_type, pos, CycloneV::BTO_DIS, 0, true);
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// Flipflop configuration
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const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL};
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// This isn't a typo; the *PKREG* bits really are mirrored.
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const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG1, CycloneV::TPKREG0, CycloneV::BPKREG1,
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CycloneV::BPKREG0};
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const std::array<CycloneV::bmux_type_t, 2> clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL},
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clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS},
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sload_en{CycloneV::TSLOAD_EN, CycloneV::BSLOAD_EN};
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const std::array<CycloneV::bmux_type_t, 3> clk_choice{CycloneV::CLK0, CycloneV::CLK1, CycloneV::CLK2};
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const std::array<CycloneV::bmux_type_t, 3> clk_inv{CycloneV::CLK0_INV, CycloneV::CLK1_INV, CycloneV::CLK2_INV},
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en_en{CycloneV::EN0_EN, CycloneV::EN1_EN, CycloneV::EN2_EN},
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en_ninv{CycloneV::EN0_NINV, CycloneV::EN1_NINV, CycloneV::EN2_NINV};
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const std::array<CycloneV::bmux_type_t, 2> aclr_inv{CycloneV::ACLR0_INV, CycloneV::ACLR1_INV};
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for (int i = 0; i < 2; i++) {
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// EF selection mux
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if (ctx->wires_connected(ctx->getBelPinWire(alm_data.lut_bels[i], i ? id_F0 : id_F1), alm_data.sel_ef[i]))
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cv->bmux_m_set(block_type, pos, ef_sel[i], alm, CycloneV::bmux_type_t::F);
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}
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for (int i = 0; i < 4; i++) {
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CellInfo *ff = ffs[i];
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if (!ff)
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continue;
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// PKREG (input selection)
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if (ctx->wires_connected(alm_data.sel_ef[i / 2], alm_data.ff_in[i]))
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cv->bmux_b_set(block_type, pos, pkreg[i], alm, true);
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// Control set
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// CLK+ENA
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int ce_idx = alm_data.clk_ena_idx[i / 2];
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cv->bmux_m_set(block_type, pos, clk_sel[i / 2], alm, clk_choice[ce_idx]);
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if (ff->ffInfo.ctrlset.clk.inverted)
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cv->bmux_b_set(block_type, pos, clk_inv[ce_idx], 0, true);
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if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to
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// ensure different constants don't collide
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cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, true);
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cv->bmux_b_set(block_type, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted);
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} else {
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cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, false);
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}
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// ACLR
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int aclr_idx = alm_data.aclr_idx[i / 2];
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cv->bmux_b_set(block_type, pos, clr_sel[i / 2], alm, aclr_idx == 1);
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if (ff->ffInfo.ctrlset.aclr.inverted)
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cv->bmux_b_set(block_type, pos, aclr_inv[aclr_idx], 0, true);
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// SCLR
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if (ff->ffInfo.ctrlset.sclr.net != nullptr) {
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cv->bmux_b_set(block_type, pos, CycloneV::SCLR_INV, 0, ff->ffInfo.ctrlset.sclr.inverted);
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} else {
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cv->bmux_b_set(block_type, pos, sclr_dis[i / 2], alm, true);
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}
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// SLOAD
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if (ff->ffInfo.ctrlset.sload.net != nullptr) {
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cv->bmux_b_set(block_type, pos, sload_en[i / 2], alm, true);
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cv->bmux_b_set(block_type, pos, CycloneV::SLOAD_INV, 0, ff->ffInfo.ctrlset.sload.inverted);
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}
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}
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if (is_lutram) {
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for (int i = 0; i < 2; i++) {
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CellInfo *lut = luts[i];
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if (!lut || lut->combInfo.mlab_group == -1)
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continue;
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int ce_idx = alm_data.clk_ena_idx[1];
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cv->bmux_m_set(block_type, pos, clk_sel[1], alm, clk_choice[ce_idx]);
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if (lut->combInfo.wclk.inverted)
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cv->bmux_b_set(block_type, pos, clk_inv[ce_idx], 0, true);
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if (get_net_or_empty(lut, id_A1EN) != nullptr) {
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cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, true);
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cv->bmux_b_set(block_type, pos, en_ninv[ce_idx], 0, lut->combInfo.we.inverted);
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} else {
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cv->bmux_b_set(block_type, pos, en_en[ce_idx], 0, false);
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}
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// TODO: understand what these are doing
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cv->bmux_b_set(block_type, pos, sclr_dis[0], alm, true);
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cv->bmux_b_set(block_type, pos, sclr_dis[1], alm, true);
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}
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}
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return true;
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}
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void write_ff_routing(uint32_t lab)
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{
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auto &lab_data = ctx->labs.at(lab);
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auto pos = lab_data.alms.at(0).lut_bels[0].pos;
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auto block_type = ctx->labs.at(lab).is_mlab ? CycloneV::MLAB : CycloneV::LAB;
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|
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const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL};
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for (int i = 0; i < 2; i++) {
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// Quartus seems to set unused ACLRs to CLKI2...
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if (!lab_data.aclr_used[i])
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cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, CycloneV::CLKI2);
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else
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cv->bmux_m_set(block_type, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1);
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}
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for (int i = 0; i < 3; i++) {
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|
// Check for fabric->clock routing
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|
if (ctx->wires_connected(
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ctx->get_port(block_type, CycloneV::pos2x(pos), CycloneV::pos2y(pos), -1, CycloneV::DATAIN, 0),
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|
lab_data.clk_wires[i]))
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cv->bmux_m_set(block_type, pos, CycloneV::CLKA_SEL, 0, CycloneV::GIN2);
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}
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|
}
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|
|
|
void write_labs()
|
|
{
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|
for (size_t lab = 0; lab < ctx->labs.size(); lab++) {
|
|
bool used = false;
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|
for (uint8_t alm = 0; alm < 10; alm++)
|
|
used |= write_alm(lab, alm);
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|
if (used)
|
|
write_ff_routing(lab);
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|
}
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|
}
|
|
|
|
void run()
|
|
{
|
|
cv->clear();
|
|
init();
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|
write_routing();
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|
write_dqs();
|
|
write_cells();
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|
write_labs();
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|
}
|
|
};
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|
} // namespace
|
|
|
|
void Arch::build_bitstream()
|
|
{
|
|
MistralBitgen gen(getCtx());
|
|
gen.run();
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|