nextpnr/himbaechel/uarch/gowin
YRabbit eb099a9244 Gowin. Bugfix.
The statement in the Gowin documentation that in the reading mode
"READ_MODE=0" the output register is not used and the OCE signal is
ignored is not confirmed by practice - if the OCE was left unconnected
or connected to the constant network, then a change in output data was
observed even with CE=0, as well as the absence of such at CE=1.

Synchronizing CE and OCE helps and the memory works properly in complex
systems such as RISC-V emulation and i8080 emulation (with 32K RAM and
16K BSRAM based ROM), but there is no theoretical basis for this fix, so
it is a hack.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-07-09 14:18:35 +02:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Add support for DSP primitives. 2024-03-22 09:47:10 +00:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin_utils.cc Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin_utils.h Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin.cc Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin.h Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
pack.cc Gowin. Bugfix. 2024-07-09 14:18:35 +02:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00