256 lines
10 KiB
C++
256 lines
10 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Symbiflow Authors
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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void Arch::place_iobufs(WireId pad_wire, NetInfo *net, const pool<CellInfo *, hash_ptr_ops> &tightly_attached_bels,
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pool<CellInfo *, hash_ptr_ops> *placed_cells)
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{
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for (BelPin bel_pin : getWireBelPins(pad_wire)) {
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BelId bel = bel_pin.bel;
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for (CellInfo *cell : tightly_attached_bels) {
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if (isValidBelForCellType(cell->type, bel)) {
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NPNR_ASSERT(cell->bel == BelId());
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NPNR_ASSERT(placed_cells->count(cell) == 0);
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bindBel(bel, cell, STRENGTH_FIXED);
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placed_cells->emplace(cell);
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IdString cell_port;
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for (auto pin_pair : cell->cell_bel_pins) {
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for (IdString a_bel_pin : pin_pair.second) {
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if (a_bel_pin == bel_pin.pin) {
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NPNR_ASSERT(cell_port == IdString());
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cell_port = pin_pair.first;
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}
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}
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}
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NPNR_ASSERT(cell_port != IdString());
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const PortInfo &port = cell->ports.at(cell_port);
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NPNR_ASSERT(port.net == net);
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}
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}
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}
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}
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void Arch::pack_ports()
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{
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dict<IdString, const TileInstInfoPOD *> tile_type_prototypes;
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for (size_t i = 0; i < chip_info->tiles.size(); ++i) {
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const auto &tile = chip_info->tiles[i];
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const auto &tile_type = chip_info->tile_types[tile.type];
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IdString tile_type_name(tile_type.name);
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tile_type_prototypes.emplace(tile_type_name, &tile);
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}
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// set(site_types) for package pins
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pool<IdString> package_sites;
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// Package pin -> (Site type -> BelId)
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dict<IdString, std::vector<std::pair<IdString, BelId>>> package_pin_bels;
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for (const PackagePinPOD &package_pin : chip_info->packages[package_index].pins) {
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IdString pin(package_pin.package_pin);
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IdString bel(package_pin.bel);
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IdString site(package_pin.site);
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package_sites.emplace(site);
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for (size_t i = 0; i < chip_info->tiles.size(); ++i) {
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const auto &tile = chip_info->tiles[i];
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pool<uint32_t> package_pin_sites;
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for (size_t j = 0; j < tile.sites.size(); ++j) {
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auto &site_data = chip_info->sites[tile.sites[j]];
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if (site == id(site_data.site_name.get())) {
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package_pin_sites.emplace(j);
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}
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}
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const auto &tile_type = chip_info->tile_types[tile.type];
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for (size_t j = 0; j < tile_type.bel_data.size(); ++j) {
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const BelInfoPOD &bel_data = tile_type.bel_data[j];
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if (bel == IdString(bel_data.name) && package_pin_sites.count(bel_data.site)) {
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auto &site_data = chip_info->sites[tile.sites[bel_data.site]];
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IdString site_type(site_data.site_type);
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BelId bel;
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bel.tile = i;
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bel.index = j;
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package_pin_bels[pin].push_back(std::make_pair(site_type, bel));
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}
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}
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}
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}
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// Determine for each package site type, which site types are possible.
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pool<IdString> package_pin_site_types;
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dict<IdString, pool<IdString>> possible_package_site_types;
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for (const TileInstInfoPOD &tile : chip_info->tiles) {
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for (size_t site_index : tile.sites) {
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const SiteInstInfoPOD &site = chip_info->sites[site_index];
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IdString site_name = getCtx()->id(site.site_name.get());
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if (package_sites.count(site_name) == 1) {
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possible_package_site_types[site_name].emplace(IdString(site.site_type));
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package_pin_site_types.emplace(IdString(site.site_type));
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}
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}
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}
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// IO sites are usually pretty weird, so see if we can define some
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// constraints between the port cell create by nextpnr and cells that are
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// immediately attached to that port cell.
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for (auto port_pair : port_cells) {
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IdString port_name = port_pair.first;
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CellInfo *port_cell = port_pair.second;
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pool<CellInfo *, hash_ptr_ops> tightly_attached_bels;
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for (auto port_pair : port_cell->ports) {
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const PortInfo &port_info = port_pair.second;
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const NetInfo *net = port_info.net;
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if (net->driver.cell) {
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tightly_attached_bels.emplace(net->driver.cell);
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}
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for (const PortRef &port_ref : net->users) {
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if (port_ref.cell) {
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tightly_attached_bels.emplace(port_ref.cell);
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}
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}
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}
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if (getCtx()->verbose) {
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log_info("Tightly attached BELs for port %s\n", port_name.c_str(getCtx()));
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for (CellInfo *cell : tightly_attached_bels) {
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log_info(" - %s : %s\n", cell->name.c_str(getCtx()), cell->type.c_str(getCtx()));
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}
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}
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NPNR_ASSERT(tightly_attached_bels.erase(port_cell) == 1);
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pool<IdString> cell_types_in_io_group;
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for (CellInfo *cell : tightly_attached_bels) {
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NPNR_ASSERT(port_cells.find(cell->name) == port_cells.end());
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cell_types_in_io_group.emplace(cell->type);
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}
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// Get possible placement locations for tightly coupled BELs with
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// port.
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pool<IdString> possible_site_types;
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for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
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IdString tile_type_name(tile_type.name);
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for (const BelInfoPOD &bel_info : tile_type.bel_data) {
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if (bel_info.category != BEL_CATEGORY_LOGIC) {
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break;
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}
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for (IdString cell_type : cell_types_in_io_group) {
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size_t cell_type_index = get_cell_type_index(cell_type);
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if (bel_info.category == BEL_CATEGORY_LOGIC && bel_info.pin_map[cell_type_index] != -1) {
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auto *tile = tile_type_prototypes.at(tile_type_name);
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const SiteInstInfoPOD &site = chip_info->sites[tile->sites[bel_info.site]];
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IdString site_type(site.site_type);
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if (package_pin_site_types.count(site_type)) {
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possible_site_types.emplace(site_type);
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}
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}
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}
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}
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}
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if (possible_site_types.empty()) {
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log_error("Port '%s' has no possible site types!\n", port_name.c_str(getCtx()));
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}
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if (getCtx()->verbose) {
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log_info("Possible site types for port %s\n", port_name.c_str(getCtx()));
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for (IdString site_type : possible_site_types) {
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log_info(" - %s\n", site_type.c_str(getCtx()));
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}
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}
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auto iter = port_cell->attrs.find(id("PACKAGE_PIN"));
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if (iter == port_cell->attrs.end()) {
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iter = port_cell->attrs.find(id("LOC"));
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if (iter == port_cell->attrs.end()) {
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log_error("Port '%s' is missing PACKAGE_PIN or LOC property\n", port_cell->name.c_str(getCtx()));
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}
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}
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// dict<IdString, dict<IdString, BelId>> package_pin_bels;
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IdString package_pin_id = id(iter->second.as_string());
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auto pin_iter = package_pin_bels.find(package_pin_id);
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if (pin_iter == package_pin_bels.end()) {
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log_error("Package pin '%s' not found in part %s\n", package_pin_id.c_str(getCtx()), get_part().c_str());
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}
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NPNR_ASSERT(pin_iter != package_pin_bels.end());
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// Select the first BEL from package_bel_pins that is a legal site
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// type.
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//
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// This is likely the most generic (versus specialized) site type.
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BelId package_bel;
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for (auto site_type_and_bel : pin_iter->second) {
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IdString legal_site_type = site_type_and_bel.first;
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BelId bel = site_type_and_bel.second;
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if (possible_site_types.count(legal_site_type)) {
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// FIXME: Need to handle case where a port can be in multiple
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// modes, but only one of the modes works.
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package_bel = bel;
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break;
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}
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}
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if (package_bel == BelId()) {
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log_info("Failed to find BEL for package pin '%s' in any possible site types:\n",
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package_pin_id.c_str(getCtx()));
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for (IdString site_type : possible_site_types) {
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log_info(" - %s\n", site_type.c_str(getCtx()));
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}
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log_error("Failed to find BEL for package pin '%s'\n", package_pin_id.c_str(getCtx()));
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}
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if (getCtx()->verbose) {
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log_info("Binding port %s to BEL %s\n", port_name.c_str(getCtx()), getCtx()->nameOfBel(package_bel));
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}
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pool<CellInfo *, hash_ptr_ops> placed_cells;
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bindBel(package_bel, port_cell, STRENGTH_FIXED);
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placed_cells.emplace(port_cell);
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IdStringRange package_bel_pins = getBelPins(package_bel);
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IdString pad_pin = get_only_value(package_bel_pins);
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WireId pad_wire = getBelPinWire(package_bel, pad_pin);
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place_iobufs(pad_wire, ports[port_pair.first].net, tightly_attached_bels, &placed_cells);
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for (CellInfo *cell : placed_cells) {
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NPNR_ASSERT(cell->bel != BelId());
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if (!isBelLocationValid(cell->bel)) {
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log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
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}
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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