nextpnr/himbaechel/uarch/gowin
YRabbit f17caa2379 Gowin. BUGFIX. Fix placement checks
It was not taken into account that there are only 6 ALUs per cell. As a
result, on complex designs where ALUs and LUT-based memory are involved
and there are many LUTs (like in the RISCV emulator), there were
sometimes false positives about placement conflicts.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-07-29 11:31:59 +01:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Add support for DSP primitives. 2024-03-22 09:47:10 +00:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin_utils.cc Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin_utils.h Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
gowin.cc Gowin. BUGFIX. Fix placement checks 2024-07-29 11:31:59 +01:00
gowin.h Gowin. Implement power saving primitive 2024-07-08 16:44:49 +02:00
pack.cc Gowin. Bugfix. 2024-07-09 14:18:35 +02:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00