nextpnr/fpga_interchange/examples/remap_xilinx.v
gatecat 49caad0b7b interchange/nexus: Add counter example
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 14:15:37 +01:00

12 lines
199 B
Verilog

module INV(input I, output O);
LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
endmodule
module BUF(input I, output O);
LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
endmodule