nextpnr/ice40
ZipCPU f32b9622d5 Initial (random) placer capability
This commit also includes changes to jsonparse to allow it to
1) recognize ports with no connection, and set their net pointers to NULL
2) recognize designs with a ports node rather than a ports_direction

The rule checker has also been modified to accommodate possible NULL netlists

The ice40 chip now also has iterator operations ++bi and bi++.
2018-06-07 09:38:14 -04:00
..
.gitignore Fix race condition and optimise the build 2018-06-02 14:17:31 +02:00
blinky_map.v Add iCE40 blinky example 2018-05-31 18:10:36 +02:00
blinky.v Add iCE40 blinky example 2018-05-31 18:10:36 +02:00
blinky.ys Add iCE40 blinky example 2018-05-31 18:10:36 +02:00
chip.cc clang-format for design and chip codebase 2018-06-07 12:56:49 +02:00
chip.h Initial (random) placer capability 2018-06-07 09:38:14 -04:00
chipdb.py Add ice40 geometry information 2018-06-06 16:42:42 +02:00
family.cmake cmake: Add HX1K-only builds support 2018-06-07 13:20:16 +02:00
main.cc Preliminary placer changes to main 2018-06-07 07:52:05 -04:00
pybindings.cc Reformat Python bindings and ice40 main 2018-06-07 13:10:53 +02:00