nextpnr/docs/faq.md

FAQ

Terminology

For nextpnr we are using the following terminology.

Design Database Terminology

• Cell: an instantiation of a physical block inside the netlist. The packer may combine or otherwise modify cells; and the placer places them onto Bels.
• Port: an input or output of a Cell, can be connected to a single net.
• Net: a connection between cell ports inside the netlist. One net will be routed using one or more wires inside the chip. Nets are always one bit in size, multibit nets are always split.
• Source: The cell output port driving a given net
• Sink: A cell input port driven by a given net
• Arc: A source-sink-pair on a net

Architecture Database Terminology

• Bel: Basic Element, the functional blocks of an FPGA such as logic cells, IO cells, blockrams, etc. Up to one cell may be placed at each Bel.
• Pin: an input or output of a Bel, permanently connected to a single wire.
• Pip: Programmable Interconnect Point, a configurable connection in one direction between two wires
• Wire: a fixed physical connection inside the FPGA between Pips and/or Bel pins.
• Alias: a special automatic-on Pip to represent a permanent connection between two wires

Flow Terminology

• Packing: The action of grouping cells in synthesis output into larger (logic) cells
• Placing: The action of binding packed cells to bels
• Routing: The action of binding nets to wires

Other Terminology

• Binding: Assigning nets to wires and cells to bels
• Path: All the arcs connecting a FF output (or primary input) to a FF input (or primary output)

Adding new architectures to nextpnr

TBD

Nextpnr and other tools

Which tool chain should I use and why?

• If you wish to do new research into FPGA architectures, place and route algorithms or other similar topics, we suggest you look at using Verilog to Routing.

• If you are developing FPGA code in Verilog for a Lattice iCE40 and need an open source toolchain, we suggest you use nextpnr.

• If you are developing FPGA code in Verilog for a Lattice iCE40 with the existing Arachne-PNR toolchain, we suggest you start thinking about migrating to nextpnr.

• If you are developing Verilog FPGA code targeted at the Lattice ECP5 and need an open source toolchain, you may consider the extremely experimental ECP5 support in nextpnr.

• If you are developing FPGA code in VHDL you will need to use either a version of Yosys with Verific support or the vendor provided tools due to the lack of open source VHDL support in Yosys.

Why didn't you just improve Arachne-PNR?

Arachne-PNR was originally developed as part of Project IceStorm to demonstrate it was possible to create an open source place and route tool for the iCE40 FPGAs that actually produced valid bitstreams.

For it's original purpose it has served the community extremely well. However, it was never designed to support multiple different FPGA devices, nor more complicated timing driven routing used by most commercial place and route tools.

It felt like extending Arachne-PNR was not going to be the best path forward, so it was decided to build nextpnr as replacement.

Arachne-PNR does X better!

If you have a use case which prevents you from switching to nextpnr from Arachne, we want to hear about it! Please create an issue following the Arachne-PNR regression template and we will do our best to solve the problem!

We want nextpnr to be a suitable replacement for anyone who is currently a user of Arachne.

Why are you not just contributing to Verilog to Routing?

We believe that Verilog to Routing is a great tool and many of the nextpnr developers have made (and continue to make) contributions to the project.

VtR is an extremely flexible tool but focuses on research around FPGA architecture and algorithm development. If your goal is research, then we very much encourage you to look into VtR further!

nextpnr takes a different approach by focusing on users developing FPGA code for current FPGAs.

We also believe that support for real architectures will enable interesting new research. nextpnr (like all place and route systems). depends heavily on research groups like the VtR developers to investigate and push forward FPGA algorithms in new and exciting ways.

What is VPR?

VPR is the "place and route" tool from Verilog To Routing. It has a similar role in an FPGA development flow as nextpnr.

What about SymbiFlow?

For the moment SymbiFlow is concentrating on extending Verilog to Routing tool to work with real world architectures. nextpnr may or may not become a part of SymbiFlow in the future.

What is Project Trellis?

Project Trellis is the effort to document the bitstream format for the Lattice ECP5 series of FPGAs. It also includes tooling around bitstream creation.

Project Trellis is used by nextpnr to enable support for creation of bitstreams for these parts.

What is Project X-Ray?

Project X-Ray is the effort to document the bitstream format for the Xilinx Series 7 series of FPGAs. It also includes tooling around bitstream generation for these parts.

While nextpnr currently does not support these Xilinx parts, we expect it will soon by using Project X Ray in a similar manner to Project Trellis.

What is Project IceStorm?

Project IceStorm was both a project to document the bitstream for the Lattice iCE40 series of parts and a full flow including Yosys and Arachne-PNR for converting Verilog into a bitstream for these parts.

As the open source community now has support for multiple different FPGA parts, in the nextpnr documentation we generally use Project IceStorm to mean the tools that fulfil the same role as Project Trellis or Project X-Ray.