13 lines
173 B
Verilog
13 lines
173 B
Verilog
module top(input clk, rst, output reg [7:0] leds);
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reg [7:0] ctr;
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always @(posedge clk)
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if (rst)
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ctr <= 8'h00;
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else
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ctr <= ctr + 1'b1;
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assign leds = ctr;
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endmodule
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