
- wires, nodes and whites are generated from bases - apicula; - roting of SN and EW bidirectional wires is supported; - supports "wrapping" the wires at the edges of the chip; - LUT1-4 and two types of DFF(R) are supported; - simple IO is supported. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
145 lines
5.4 KiB
C++
145 lines
5.4 KiB
C++
#include "himbaechel_api.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "himbaechel_helpers.h"
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#define GEN_INIT_CONSTIDS
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct GowinImpl : HimbaechelAPI
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{
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~GowinImpl(){};
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void init_constids(Arch *arch) override { init_uarch_constids(arch); }
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void init(Context *ctx) override
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{
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h.init(ctx);
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HimbaechelAPI::init(ctx);
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}
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void prePlace() override {
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ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X46Y14/IOBA"));
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ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
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ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
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assign_cell_info();
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}
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void pack() override
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{
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_IBUF, id_I),
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CellTypePort(id_OBUF, id_O),
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};
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h.remove_nextpnr_iobs(top_ports);
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// Replace constants with LUTs
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const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
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const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
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h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
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// Constrain directly connected LUTs and FFs together to use dedicated resources
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int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
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lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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}
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bool isBelLocationValid(BelId bel, bool explain_invalid) const override
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{
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Loc l = ctx->getBelLocation(bel);
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if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
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return slice_valid(l.x, l.y, l.z / 2);
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} else {
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return true;
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}
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}
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// Bel bucket functions
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IdString getBelBucketForCellType(IdString cell_type) const override
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{
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if (cell_type.in(id_IBUF, id_OBUF)) {
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return id_IOB;
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}
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if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
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return id_LUT4;
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}
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return cell_type;
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}
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override
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{
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB) {
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return cell_type.in(id_IBUF, id_OBUF);
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}
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if (bel_type == id_LUT4) {
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return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
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}
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if (bel_type == id_DFF) {
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return cell_type.in(id_DFF, id_DFFR);
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}
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return (bel_type == cell_type);
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}
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private:
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HimbaechelHelpers h;
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// Validity checking
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struct GowinCellInfo
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{
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const NetInfo *lut_f = nullptr, *ff_d = nullptr;
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};
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std::vector<GowinCellInfo> fast_cell_info;
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void assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
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fc.lut_f = ci->getPort(id_F);
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} else if (ci->type.in(id_DFF, id_DFFR)) {
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fc.ff_d = ci->getPort(id_D);
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}
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}
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}
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bool slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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if (!lut || !ff)
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return true; // always valid if only LUT or FF used
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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if (ff_data.ff_d == lut_data.lut_f)
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return true;
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return false;
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}
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};
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struct GowinArch : HimbaechelArch
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{
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GowinArch() : HimbaechelArch("gowin"){};
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std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
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{
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return std::make_unique<GowinImpl>();
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}
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} exampleArch;
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} // namespace
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NEXTPNR_NAMESPACE_END
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