380 lines
17 KiB
C++
380 lines
17 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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// This file contains functions related to our custom LAB structure, including creating the LAB bels; checking the
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// legality of LABs; and manipulating LUT inputs and equations
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// LAB/ALM structure creation functions
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namespace {
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static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
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{
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auto &lab = arch->labs.at(lab_idx);
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// Create the combinational part of ALMs.
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// There are two of these, for the two LUT outputs, and these also contain the carry chain and associated logic
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// Each one has all 8 ALM inputs as input pins. In many cases only a subset of these are used; depending on mode;
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// and the bel-cell pin mappings are used to handle this post-placement without losing flexibility
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for (int i = 0; i < 2; i++) {
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// Carry/share wires are a bit tricky due to all the different permutations
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WireId carry_in, share_in;
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WireId carry_out, share_out;
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if (z == 0 && i == 0) {
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if (y == 0) {
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// Base case
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carry_in = arch->add_wire(x, y, id_CARRY_START);
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share_in = arch->add_wire(x, y, id_CARRY_START);
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} else {
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// Output of last tile
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carry_in = arch->add_wire(x, y - 1, id_COUT);
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share_in = arch->add_wire(x, y - 1, id_SHAREOUT);
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}
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} else {
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// Output from last combinational unit
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carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1)));
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share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1)));
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}
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if (z == 9 && i == 1) {
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carry_out = arch->add_wire(x, y, id_COUT);
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share_out = arch->add_wire(x, y, id_SHAREOUT);
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} else {
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carry_out = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", z * 2 + i)));
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share_out = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", z * 2 + i)));
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}
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BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_COMB%d", z, i)), id_MISTRAL_COMB);
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// LUT/MUX inputs
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arch->add_bel_pin(bel, id_A, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::A));
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arch->add_bel_pin(bel, id_B, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::B));
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arch->add_bel_pin(bel, id_C, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::C));
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arch->add_bel_pin(bel, id_D, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::D));
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arch->add_bel_pin(bel, id_E0, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::E0));
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arch->add_bel_pin(bel, id_E1, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::E1));
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arch->add_bel_pin(bel, id_F0, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::F0));
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arch->add_bel_pin(bel, id_F1, PORT_IN, arch->get_port(CycloneV::LAB, x, y, z, CycloneV::F1));
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// Carry/share chain
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arch->add_bel_pin(bel, id_CIN, PORT_IN, carry_in);
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arch->add_bel_pin(bel, id_SHAREIN, PORT_IN, share_in);
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arch->add_bel_pin(bel, id_COUT, PORT_OUT, carry_out);
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arch->add_bel_pin(bel, id_SHAREOUT, PORT_OUT, share_out);
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// Combinational output
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WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", z * 2 + i)));
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arch->add_bel_pin(bel, id_COMBOUT, PORT_OUT, comb_out);
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// Assign indexing
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lab.alms.at(z).lut_bels.at(i) = bel;
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auto &b = arch->bel_data(bel);
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b.lab_data.lab = lab_idx;
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b.lab_data.alm = z;
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b.lab_data.idx = i;
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}
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// Create the control set and E/F selection - which is per pair of FF
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std::array<WireId, 2> sel_clk, sel_ena, sel_aclr, sel_ef;
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for (int i = 0; i < 2; i++) {
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// Wires
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sel_clk[i] = arch->add_wire(x, y, arch->id(stringf("CLK%c[%d]", i ? 'B' : 'T', z)));
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sel_ena[i] = arch->add_wire(x, y, arch->id(stringf("ENA%c[%d]", i ? 'B' : 'T', z)));
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sel_aclr[i] = arch->add_wire(x, y, arch->id(stringf("ACLR%c[%d]", i ? 'B' : 'T', z)));
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sel_ef[i] = arch->add_wire(x, y, arch->id(stringf("%cEF[%d]", i ? 'B' : 'T', z)));
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// Muxes - three CLK/ENA per LAB, two ACLR
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for (int j = 0; j < 3; j++) {
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arch->add_pip(lab.clk_wires[j], sel_clk[i]);
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arch->add_pip(lab.ena_wires[j], sel_ena[i]);
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if (j < 2)
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arch->add_pip(lab.aclr_wires[j], sel_aclr[i]);
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}
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// E/F pips
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arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::E1 : CycloneV::E0), sel_ef[i]);
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arch->add_pip(arch->get_port(CycloneV::LAB, x, y, z, i ? CycloneV::F1 : CycloneV::F0), sel_ef[i]);
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}
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// Create the flipflops and associated routing
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const CycloneV::port_type_t outputs[4] = {CycloneV::FFT0, CycloneV::FFT1, CycloneV::FFB0, CycloneV::FFB1};
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const CycloneV::port_type_t l_outputs[4] = {CycloneV::FFT1L, CycloneV::FFB1L};
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for (int i = 0; i < 4; i++) {
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// FF input, selected by *PKREG*
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WireId comb_out = arch->add_wire(x, y, arch->id(stringf("COMBOUT[%d]", (z * 2) + (i / 2))));
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WireId ff_in = arch->add_wire(x, y, arch->id(stringf("FFIN[%d]", (z * 4) + i)));
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arch->add_pip(comb_out, ff_in);
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arch->add_pip(sel_ef[i / 2], ff_in);
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// FF bel
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BelId bel = arch->add_bel(x, y, arch->id(stringf("ALM%d_FF%d", z, i)), id_MISTRAL_FF);
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arch->add_bel_pin(bel, id_CLK, PORT_IN, sel_clk[i / 2]);
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arch->add_bel_pin(bel, id_ENA, PORT_IN, sel_ena[i / 2]);
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arch->add_bel_pin(bel, id_ACLR, PORT_IN, sel_aclr[i / 2]);
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arch->add_bel_pin(bel, id_SCLR, PORT_IN, lab.sclr_wire);
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arch->add_bel_pin(bel, id_SLOAD, PORT_IN, lab.sload_wire);
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arch->add_bel_pin(bel, id_DATAIN, PORT_IN, ff_in);
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arch->add_bel_pin(bel, id_SDATA, PORT_IN, sel_ef[i / 2]);
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// FF output
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WireId ff_out = arch->add_wire(x, y, arch->id(stringf("FFOUT[%d]", (z * 4) + i)));
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arch->add_bel_pin(bel, id_Q, PORT_OUT, ff_out);
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// Output mux (*DFF*)
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WireId out = arch->get_port(CycloneV::LAB, x, y, z, outputs[i]);
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arch->add_pip(ff_out, out);
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arch->add_pip(comb_out, out);
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// 'L' output mux where applicable
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if (i == 1 || i == 3) {
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WireId l_out = arch->get_port(CycloneV::LAB, x, y, z, l_outputs[i / 2]);
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arch->add_pip(ff_out, l_out);
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arch->add_pip(comb_out, l_out);
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}
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lab.alms.at(z).ff_bels.at(i) = bel;
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auto &b = arch->bel_data(bel);
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b.lab_data.lab = lab_idx;
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b.lab_data.alm = z;
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b.lab_data.idx = i;
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}
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}
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} // namespace
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void Arch::create_lab(int x, int y)
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{
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uint32_t lab_idx = labs.size();
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labs.emplace_back();
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auto &lab = labs.back();
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// Create common control set configuration. This is actually a subset of what's possible, but errs on the side of
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// caution due to incomplete documentation
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// Clocks - hardcode to CLKA choices, as both CLKA and CLKB coming from general routing causes unexpected
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// permutations
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for (int i = 0; i < 3; i++) {
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lab.clk_wires[i] = add_wire(x, y, id(stringf("CLK%d", i)));
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add_pip(get_port(CycloneV::LAB, x, y, -1, CycloneV::CLKIN, 0), lab.clk_wires[i]); // dedicated routing
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add_pip(get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 0), lab.clk_wires[i]); // general routing
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}
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// Enables - while it looks from the config like there are choices for these, it seems like EN0_SEL actually selects
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// SCLR not ENA0 and EN1_SEL actually selects SLOAD?
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lab.ena_wires[0] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 2);
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lab.ena_wires[1] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.ena_wires[2] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 0);
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// ACLRs - only consider general routing for now
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lab.aclr_wires[0] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.aclr_wires[1] = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 2);
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// SCLR and SLOAD - as above it seems like these might be selectable using the "EN*_SEL" bits but play it safe for
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// now
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lab.sclr_wire = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 3);
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lab.sload_wire = get_port(CycloneV::LAB, x, y, -1, CycloneV::DATAIN, 1);
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for (int i = 0; i < 10; i++) {
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create_alm(this, x, y, i, lab_idx);
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}
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}
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// Cell handling and annotation functions
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namespace {
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ControlSig get_ctrlsig(const CellInfo *cell, IdString port)
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{
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ControlSig result;
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result.net = get_net_or_empty(cell, port);
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if (cell->pin_data.count(port))
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result.inverted = cell->pin_data.at(port).inverted;
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else
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result.inverted = false;
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return result;
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}
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} // namespace
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bool Arch::is_comb_cell(IdString cell_type) const
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{
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// Return true if a cell is a combinational cell type, to be a placed at a MISTRAL_COMB location
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switch (cell_type.index) {
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case ID_MISTRAL_ALUT6:
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case ID_MISTRAL_ALUT5:
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case ID_MISTRAL_ALUT4:
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case ID_MISTRAL_ALUT3:
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case ID_MISTRAL_ALUT2:
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case ID_MISTRAL_NOT:
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case ID_MISTRAL_CONST:
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case ID_MISTRAL_ALUT_ARITH:
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return true;
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default:
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return false;
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}
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}
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void Arch::assign_comb_info(CellInfo *cell) const
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{
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cell->combInfo.is_carry = false;
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cell->combInfo.is_shared = false;
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cell->combInfo.is_extended = false;
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if (cell->type == id_MISTRAL_ALUT_ARITH) {
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cell->combInfo.is_carry = true;
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cell->combInfo.lut_input_count = 5;
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cell->combInfo.lut_bits_count = 32;
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// This is a special case in terms of naming
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int i = 0;
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for (auto pin : {id_A, id_B, id_C, id_D0, id_D1}) {
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cell->combInfo.lut_in[i++] = get_net_or_empty(cell, pin);
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}
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cell->combInfo.comb_out = get_net_or_empty(cell, id_SO);
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} else {
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cell->combInfo.lut_input_count = 0;
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switch (cell->type.index) {
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case ID_MISTRAL_ALUT6:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[5] = get_net_or_empty(cell, id_F);
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[[fallthrough]];
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case ID_MISTRAL_ALUT5:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[4] = get_net_or_empty(cell, id_E);
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[[fallthrough]];
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case ID_MISTRAL_ALUT4:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[3] = get_net_or_empty(cell, id_D);
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[[fallthrough]];
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case ID_MISTRAL_ALUT3:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[2] = get_net_or_empty(cell, id_C);
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[[fallthrough]];
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case ID_MISTRAL_ALUT2:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[1] = get_net_or_empty(cell, id_B);
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[[fallthrough]];
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case ID_MISTRAL_NOT:
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++cell->combInfo.lut_input_count;
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cell->combInfo.lut_in[0] = get_net_or_empty(cell, id_A);
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[[fallthrough]];
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case ID_MISTRAL_CONST:
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// MISTRAL_CONST is a nextpnr-inserted cell type for 0-input, constant-generating LUTs
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break;
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default:
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log_error("unexpected combinational cell type %s\n", getCtx()->nameOf(cell->type));
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}
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// Note that this relationship won't hold for extended mode, when that is supported
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cell->combInfo.lut_bits_count = (1 << cell->combInfo.lut_input_count);
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}
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}
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void Arch::assign_ff_info(CellInfo *cell) const
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{
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cell->ffInfo.ctrlset.clk = get_ctrlsig(cell, id_CLK);
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cell->ffInfo.ctrlset.ena = get_ctrlsig(cell, id_ENA);
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cell->ffInfo.ctrlset.aclr = get_ctrlsig(cell, id_ACLR);
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cell->ffInfo.ctrlset.sclr = get_ctrlsig(cell, id_SCLR);
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cell->ffInfo.ctrlset.sload = get_ctrlsig(cell, id_SLOAD);
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cell->ffInfo.sdata = get_net_or_empty(cell, id_SDATA);
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cell->ffInfo.datain = get_net_or_empty(cell, id_DATAIN);
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}
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// Validity checking functions
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bool Arch::is_alm_legal(uint32_t lab, uint8_t alm) const
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{
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auto &alm_data = labs.at(lab).alms.at(alm);
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// Get cells into an array for fast access
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std::array<const CellInfo *, 2> luts{getBoundBelCell(alm_data.lut_bels[0]), getBoundBelCell(alm_data.lut_bels[1])};
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std::array<const CellInfo *, 4> ffs{getBoundBelCell(alm_data.ff_bels[0]), getBoundBelCell(alm_data.ff_bels[1]),
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getBoundBelCell(alm_data.ff_bels[2]), getBoundBelCell(alm_data.ff_bels[3])};
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int used_lut_bits = 0;
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int total_lut_inputs = 0;
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// TODO: for more complex modes like extended/arithmetic, it might not always be possible for any LUT input to map
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// to any of the ALM half inputs particularly shared and extended mode will need more thought and probably for this
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// to be revisited
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for (int i = 0; i < 2; i++) {
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if (!luts[i])
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continue;
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total_lut_inputs += luts[i]->combInfo.lut_input_count;
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used_lut_bits += luts[i]->combInfo.lut_bits_count;
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}
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// An ALM only has 64 bits of storage. In theory some of these cases might be legal because of overlap between the
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// two functions, but the current placer is unlikely to stumble upon these cases frequently without anything to
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// guide it, and the cost of checking them here almost certainly outweighs any marginal benefit in supporting them,
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// at least for now.
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if (used_lut_bits > 64)
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return false;
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if (total_lut_inputs > 8) {
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NPNR_ASSERT(luts[0] && luts[1]); // something has gone badly wrong if this fails!
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// Make sure that LUT inputs are not overprovisioned
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int shared_lut_inputs = 0;
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// Even though this N^2 search looks inefficient, it's unlikely a set lookup or similar is going to be much
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// better given the low N.
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for (int i = 0; i < luts[1]->combInfo.lut_input_count; i++) {
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const NetInfo *sig = luts[1]->combInfo.lut_in[i];
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for (int j = 0; j < luts[0]->combInfo.lut_input_count; j++) {
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if (sig == luts[0]->combInfo.lut_in[j]) {
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++shared_lut_inputs;
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break;
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}
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}
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}
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if ((total_lut_inputs - shared_lut_inputs) > 8)
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return false;
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}
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// For each ALM half; check FF control set sharing and input routeability
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for (int i = 0; i < 2; i++) {
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// There are two ways to route from the fabric into FF data - either routing through a LUT or using the E/F
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// signals and SLOAD=1 (*PKREF*)
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bool route_thru_lut_avail = !luts[i] && (total_lut_inputs < 8) && (used_lut_bits < 64);
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// E/F is available if the LUT is using less than 6 inputs - TODO: is this correct considering all possible LUT
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// sharing
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bool ef_available = (!luts[i] || luts[i]->combInfo.lut_input_count < 6);
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// Control set checking
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bool found_ff = false;
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FFControlSet ctrlset;
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for (int j = 0; j < 2; j++) {
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const CellInfo *ff = ffs[i * 2 + j];
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if (!ff)
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continue;
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if (found_ff) {
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// Two FFs in the same half with an incompatible control set
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if (ctrlset != ff->ffInfo.ctrlset)
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return false;
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} else {
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ctrlset = ff->ffInfo.ctrlset;
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}
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// SDATA must use the E/F input
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// TODO: rare case of two FFs with the same SDATA in the same ALM half
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if (ff->ffInfo.sdata) {
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if (!ef_available)
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return false;
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ef_available = false;
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}
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// Find a way of routing the input through fabric, if it's not driven by the LUT
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if (ff->ffInfo.datain && (!luts[i] || (ff->ffInfo.datain != luts[i]->combInfo.comb_out))) {
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if (route_thru_lut_avail)
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route_thru_lut_avail = false;
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else if (ef_available)
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ef_available = false;
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else
|
|
return false;
|
|
}
|
|
found_ff = true;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END |