499 lines
16 KiB
C++
499 lines
16 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2021 William D. Jones <wjones@wdj-consulting.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <iostream>
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#include <math.h>
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#include "embed.h"
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#include "gfx.h"
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#include "machxo2_available.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// ---------------------------------------------------------------
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static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
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const char **device_name, const char **package_name)
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{
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std::stringstream ss(available_devices);
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std::string name;
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while (getline(ss, name, ';')) {
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std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
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auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
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if (!db_ptr)
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continue; // chipdb not available
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for (auto &chip : db_ptr->get()->variants) {
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for (auto &pkg : chip.packages) {
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for (auto &speedgrade : chip.speed_grades) {
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for (auto &rating : chip.suffixes) {
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std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
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pkg.short_name.get(), rating.suffix.get());
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if (device == devname) {
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*chip_info = db_ptr->get();
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*package_info = nullptr;
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*package_name = pkg.name.get();
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*device_name = chip.name.get();
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for (auto &pi : db_ptr->get()->package_info) {
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if (pkg.name.get() == pi.name.get()) {
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*package_info = π
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break;
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}
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}
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return;
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}
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}
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}
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}
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}
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}
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}
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// ---------------------------------------------------------------
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Arch::Arch(ArchArgs args) : args(args)
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{
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get_chip_info(args.device, &chip_info, &package_info, &device_name, &package_name);
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if (chip_info == nullptr)
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log_error("Unsupported MachXO2 chip type.\n");
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if (chip_info->const_id_count != DB_CONST_ID_COUNT)
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log_error("Chip database 'bba' and nextpnr code are out of sync; please rebuild (or contact distribution "
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"maintainer)!\n");
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if (!package_info)
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log_error("Unsupported package '%s' for '%s'.\n", package_name, getChipName().c_str());
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BaseArch::init_cell_types();
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BaseArch::init_bel_buckets();
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for (int i = 0; i < chip_info->width; i++)
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x_ids.push_back(idf("X%d", i));
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for (int i = 0; i < chip_info->height; i++)
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y_ids.push_back(idf("Y%d", i));
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for (int i = 0; i < chip_info->width; i++) {
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IdString x_id = idf("X%d", i);
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x_ids.push_back(x_id);
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id_to_x[x_id] = i;
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}
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for (int i = 0; i < chip_info->height; i++) {
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IdString y_id = idf("Y%d", i);
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y_ids.push_back(y_id);
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id_to_y[y_id] = i;
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}
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}
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void Arch::list_devices()
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{
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log("Supported devices: \n");
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std::stringstream ss(available_devices);
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std::string name;
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while (getline(ss, name, ';')) {
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std::string chipdb = stringf("machxo2/chipdb-%s.bin", name.c_str());
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auto db_ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
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if (!db_ptr)
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continue; // chipdb not available
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for (auto &chip : db_ptr->get()->variants) {
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for (auto &pkg : chip.packages) {
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for (auto &speedgrade : chip.speed_grades) {
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for (auto &rating : chip.suffixes) {
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log(" %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(),
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rating.suffix.get());
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}
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}
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}
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}
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}
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const { return args.device; }
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IdString Arch::archArgsToId(ArchArgs args) const { return id(args.device); }
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// ---------------------------------------------------------------
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BelId Arch::getBelByName(IdStringList name) const
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{
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if (name.size() != 3)
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return BelId();
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BelId ret;
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Location loc;
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loc.x = id_to_x.at(name[0]);
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loc.y = id_to_y.at(name[1]);
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ret.location = loc;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->bel_data.ssize(); i++) {
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if (std::strcmp(loci->bel_data[i].name.get(), name[2].c_str(this)) == 0) {
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId ret;
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if (loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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ret.location.x = loc.x;
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ret.location.y = loc.y;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->bel_data.ssize(); i++) {
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if (loci->bel_data[i].z == loc.z) {
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor_tile = y * chip_info->width + x;
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br.e.cursor_tile = y * chip_info->width + x;
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br.b.cursor_index = 0;
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br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].bel_data.ssize() - 1;
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br.b.chip = chip_info;
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br.e.chip = chip_info;
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if (br.e.cursor_index == -1)
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++br.e.cursor_index;
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else
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++br.e;
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return br;
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}
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bool Arch::getBelGlobalBuf(BelId bel) const { return false; }
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
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if (bw.port == pin.index) {
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WireId ret;
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ret.location.x = bw.rel_wire_loc.x;
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ret.location.y = bw.rel_wire_loc.y;
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ret.index = bw.wire_index;
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return ret;
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}
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return WireId();
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires)
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if (bw.port == pin.index)
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return PortType(bw.type);
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return PORT_INOUT;
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) {
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IdString id;
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id.index = bw.port;
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ret.push_back(id);
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}
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return ret;
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}
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// ---------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (auto &ppin : package_info->pin_data) {
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if (ppin.name.get() == pin) {
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BelId bel;
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bel.location = ppin.abs_loc;
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bel.index = ppin.bel_index;
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return bel;
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}
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}
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return BelId();
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}
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// ---------------------------------------------------------------
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WireId Arch::getWireByName(IdStringList name) const
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{
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if (name.size() != 3)
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return WireId();
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WireId ret;
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Location loc;
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loc.x = id_to_x.at(name[0]);
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loc.y = id_to_y.at(name[1]);
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ret.location = loc;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->wire_data.ssize(); i++) {
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if (std::strcmp(loci->wire_data[i].name.get(), name[2].c_str(this)) == 0) {
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ret.index = i;
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return ret;
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}
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}
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return WireId();
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}
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// ---------------------------------------------------------------
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PipId Arch::getPipByName(IdStringList name) const
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{
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if (name.size() != 3)
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return PipId();
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auto it = pip_by_name.find(name);
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if (it != pip_by_name.end())
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return it->second;
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PipId ret;
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Location loc;
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std::string basename;
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loc.x = id_to_x.at(name[0]);
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loc.y = id_to_y.at(name[1]);
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ret.location = loc;
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const TileTypePOD *loci = tile_info(ret);
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for (int i = 0; i < loci->pip_data.ssize(); i++) {
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PipId curr;
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curr.location = loc;
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curr.index = i;
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pip_by_name[getPipName(curr)] = curr;
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}
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if (pip_by_name.find(name) == pip_by_name.end())
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NPNR_ASSERT_FALSE_STR("no pip named " + name.str(getCtx()));
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return pip_by_name[name];
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}
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IdStringList Arch::getPipName(PipId pip) const
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{
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auto &pip_data = tile_info(pip)->pip_data[pip.index];
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WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
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std::string pip_name =
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stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x, pip_data.src.y, get_wire_basename(src).c_str(this),
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pip_data.dst.x, pip_data.dst.y, get_wire_basename(dst).c_str(this));
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std::array<IdString, 3> ids{x_ids.at(pip.location.x), y_ids.at(pip.location.y), id(pip_name)};
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return IdStringList(ids);
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}
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// ---------------------------------------------------------------
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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// Taxicab distance multiplied by pipDelay (0.01) and fake wireDelay (0.01).
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// TODO: This function will not work well for entrance to global routing,
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// as the entrances are located physically far from the DCCAs.
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return (abs(dst.location.x - src.location.x) + abs(dst.location.y - src.location.y)) * (0.01 + 0.01);
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}
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delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
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{
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NPNR_UNUSED(src_pin);
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NPNR_UNUSED(dst_pin);
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NPNR_ASSERT(src_bel != BelId());
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NPNR_ASSERT(dst_bel != BelId());
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// TODO: Same deal applies here as with estimateDelay.
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return (abs(dst_bel.location.x - src_bel.location.x) + abs(dst_bel.location.y - src_bel.location.y)) *
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(0.01 + 0.01);
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}
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BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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BoundingBox bb;
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bb.x0 = std::min(src.location.x, dst.location.x);
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bb.y0 = std::min(src.location.y, dst.location.y);
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bb.x1 = std::max(src.location.x, dst.location.x);
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bb.y1 = std::max(src.location.y, dst.location.y);
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return bb;
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}
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// ---------------------------------------------------------------
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bool Arch::place()
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{
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std::string placer = str_or_default(settings, id_placer, defaultPlacer);
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if (placer == "sa") {
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bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
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getCtx()->settings[id_place] = 1;
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archInfoToAttributes();
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return retVal;
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} else if (placer == "heap") {
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PlacerHeapCfg cfg(getCtx());
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cfg.ioBufTypes.insert(id_TRELLIS_IO);
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bool retVal = placer_heap(getCtx(), cfg);
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getCtx()->settings[id_place] = 1;
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archInfoToAttributes();
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return retVal;
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} else {
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log_error("MachXO2 architecture does not support placer '%s'\n", placer.c_str());
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}
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}
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bool Arch::route()
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{
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std::string router = str_or_default(settings, id_router, defaultRouter);
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bool result;
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if (router == "router1") {
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result = router1(getCtx(), Router1Cfg(getCtx()));
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} else if (router == "router2") {
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router2(getCtx(), Router2Cfg(getCtx()));
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result = true;
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} else {
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log_error("MachXO2 architecture does not support router '%s'\n", router.c_str());
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}
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getCtx()->settings[id_route] = 1;
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archInfoToAttributes();
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return result;
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}
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// -----------------------------------------------------------------------
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std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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{
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std::vector<GraphicElement> ret;
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if (decal.type == DecalId::TYPE_WIRE) {
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WireId wire;
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wire.index = decal.z;
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wire.location = decal.location;
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auto wire_type = getWireType(wire);
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int x = decal.location.x;
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int y = decal.location.y;
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GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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GfxTileWireId tilewire = GfxTileWireId(tile_info(wire)->wire_data[wire.index].tile_wire);
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gfxTileWire(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, wire_type, tilewire, style);
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} else if (decal.type == DecalId::TYPE_PIP) {
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PipId pip;
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pip.index = decal.z;
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pip.location = decal.location;
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WireId src_wire = getPipSrcWire(pip);
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WireId dst_wire = getPipDstWire(pip);
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int x = decal.location.x;
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int y = decal.location.y;
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GfxTileWireId src_id = GfxTileWireId(tile_info(src_wire)->wire_data[src_wire.index].tile_wire);
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GfxTileWireId dst_id = GfxTileWireId(tile_info(dst_wire)->wire_data[dst_wire.index].tile_wire);
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GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
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gfxTilePip(ret, x, chip_info->height - y - 1, chip_info->width, chip_info->height, src_wire,
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getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire), dst_id, style);
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} else if (decal.type == DecalId::TYPE_BEL) {
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BelId bel;
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bel.index = decal.z;
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bel.location = decal.location;
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auto bel_type = getBelType(bel);
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int x = decal.location.x;
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int y = decal.location.y;
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int z = tile_info(bel)->bel_data[bel.index].z;
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GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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gfxTileBel(ret, x, chip_info->height - y - 1, z, chip_info->width, chip_info->height, bel_type, style);
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}
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return ret;
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}
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DecalXY Arch::getBelDecal(BelId bel) const
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{
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DecalXY decalxy;
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decalxy.decal.type = DecalId::TYPE_BEL;
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decalxy.decal.location = bel.location;
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decalxy.decal.z = bel.index;
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decalxy.decal.active = getBoundBelCell(bel) != nullptr;
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return decalxy;
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}
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DecalXY Arch::getWireDecal(WireId wire) const
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{
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DecalXY decalxy;
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decalxy.decal.type = DecalId::TYPE_WIRE;
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decalxy.decal.location = wire.location;
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decalxy.decal.z = wire.index;
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decalxy.decal.active = getBoundWireNet(wire) != nullptr;
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return decalxy;
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}
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DecalXY Arch::getPipDecal(PipId pip) const
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{
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DecalXY decalxy;
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decalxy.decal.type = DecalId::TYPE_PIP;
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decalxy.decal.location = pip.location;
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decalxy.decal.z = pip.index;
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decalxy.decal.active = getBoundPipNet(pip) != nullptr;
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return decalxy;
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};
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// ---------------------------------------------------------------
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bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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// FIXME: Same deal as isValidBelForCell.
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return true;
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}
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const std::string Arch::defaultPlacer = "heap";
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const std::vector<std::string> Arch::availablePlacers = {"sa", "heap"};
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const std::string Arch::defaultRouter = "router1";
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const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
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bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; }
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std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row, int col)
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{
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std::vector<std::pair<std::string, std::string>> ret;
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auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
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for (auto &tn : tileloc.tile_names) {
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ret.push_back(std::make_pair(tn.name.get(), chip_info->tiletype_names[tn.type_idx].get()));
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}
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return ret;
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}
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NEXTPNR_NAMESPACE_END
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