YRabbit fe5a7bda44 Gowin. BUGFIX. Create all Clock Pips. ... Some Clocks PIPS were not created due to a check for the presence of a delay class, now all wires are attributed to the class so that there is no longer any need for this check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>		2024-09-06 05:47:56 +10:00
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example	Make example more like other arch	2024-04-05 12:25:52 +02:00
gowin	Gowin. BUGFIX. Create all Clock Pips.	2024-09-06 05:47:56 +10:00
xilinx	Himbaechel xilinx : Fix regex to parse Zynq device names	2024-08-19 21:06:45 +01:00