192 lines
7.8 KiB
C++
192 lines
7.8 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2019 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*
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* Generic Frontend Framework
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*
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* This is designed to make it possible to build frontends for parsing any format isomorphic to Yosys JSON [1]
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* with maximal inlining and minimal need for overhead such as runtime polymorphism or extra wrapper types.
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*
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* [1] http://www.clifford.at/yosys/cmd_write_json.html
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*
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* The frontend should implement a class referred to as FrontendType that defines the following type(def)s and
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* functions:
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*
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* Types:
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* ModuleDataType: corresponds to a single entry in "modules"
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* ModulePortDataType: corresponds to a single entry in "ports" of a module
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* CellDataType: corresponds to a single entry in "cells"
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* NetnameDataType: corresponds to a single entry in "netnames"
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* BitVectorDataType: corresponds to a signal/constant bit vector (e.g. a "connections" field)
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*
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* Functions:
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*
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* void foreach_module(Func);
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* calls Func(const std::string &name, const ModuleDataType &mod);
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* for each module in the netlist
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*
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* void foreach_port(const ModuleDataType &mod, Func);
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* calls Func(const std::string &name, const ModulePortDataType &port);
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* for each port of mod
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*
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* void foreach_cell(const ModuleDataType &mod, Func);
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* calls Func(const std::string &name, const CellDataType &cell);
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* for each cell of mod
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*
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* void foreach_netname(const ModuleDataType &mod, Func);
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* calls Func(const std::string &name, const NetnameDataType &cell);
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* for each netname entry of mod
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*
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* PortType get_port_dir(const ModulePortDataType &port);
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* gets the PortType direction of a module port
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*
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* int get_port_offset(const ModulePortDataType &port);
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* gets the start bit number of a port
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*
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* bool is_port_upto(const ModulePortDataType &port);
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* returns true if a port is an "upto" type port
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*
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* const BitVectorDataType &get_port_bits(const ModulePortDataType &port);
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* gets the bit vector of a module port
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*
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* const std::string& get_cell_type(const CellDataType &cell);
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* gets the type of a cell
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*
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* void foreach_attr(const {ModuleDataType|CellDataType|ModulePortDataType|NetnameDataType} &obj, Func);
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* calls Func(const std::string &name, const Property &value);
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* for each attribute on a module, cell, module port or net
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*
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* void foreach_param(const CellDataType &obj, Func);
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* calls Func(const std::string &name, const Property &value);
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* for each parameter of a cell
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*
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* void foreach_port_dir(const CellDataType &cell, Func);
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* calls Func(const std::string &name, PortType dir);
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* for each port direction of a cell
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*
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* void foreach_port_conn(const CellDataType &cell, Func);
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* calls Func(const std::string &name, const BitVectorDataType &conn);
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* for each port connection of a cell
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*
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* const BitVectorDataType &get_net_bits(const NetnameDataType &net);
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* gets the BitVector corresponding to the bits entry of a netname field
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*
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* int get_vector_length(const BitVectorDataType &bits);
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* gets the length of a BitVector
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*
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* bool is_vector_bit_constant(const BitVectorDataType &bits, int i);
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* returns true if bit <i> of bits is constant
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*
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* char get_vector_bit_constval(const BitVectorDataType &bits, int i);
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* returns a char [01xz] corresponding to the constant value of bit <i>
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*
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* int get_vector_bit_signal(const BitVectorDataType &bits, int i);
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* returns the signal number of vector bit <i>
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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template <typename FrontendType> struct GenericFrontend
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{
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GenericFrontend(Context *ctx, const FrontendType &impl) : ctx(ctx), impl(impl) {}
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Context *ctx;
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const FrontendType &impl;
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using mod_dat_t = typename FrontendType::ModuleDataType;
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using mod_port_dat_t = typename FrontendType::ModulePortDataType;
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using cell_dat_t = typename FrontendType::CellDataType;
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using netname_dat_t = typename FrontendType::NetnameDataType;
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using bitvector_t = typename FrontendType::BitVectorDataType;
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// Used for hierarchy resolution
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struct ModuleInfo
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{
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mod_dat_t *mod_data;
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bool is_top = false, is_blackbox = false, is_whitebox = false;
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inline bool is_box() const { return is_blackbox || is_whitebox; }
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std::unordered_set<IdString> instantiated_celltypes;
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};
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std::unordered_map<IdString, ModuleInfo> mods;
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IdString top;
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// Process the list of modules and determine
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// the top module
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void find_top_module()
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{
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impl.foreach_module([&](const std::string &name, const mod_dat_t &mod) {
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IdString mod_id = ctx->id(name);
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auto &mi = mods[mod_id];
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mi.mod_data = &mod;
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impl.foreach_attr(mod, [&](const std::string &name, const Property &value) {
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if (name == "top")
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mi.is_top = (value.intval != 0);
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else if (name == "blackbox")
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mi.is_blackbox = (value.intval != 0);
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else if (name == "whitebox")
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mi.is_whitebox = (value.intval != 0);
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});
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impl.foreach_cell(mod, [&](const std::string &name, const cell_dat_t &cell) {
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mi.instantiated_cells.insert(ctx->id(impl.get_cell_type(cell)));
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});
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});
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// First of all, see if a top module has been manually specified
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if (ctx->settings.count(ctx->id("frontend/top"))) {
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IdString user_top = ctx->id(ctx->settings.at(ctx->id("frontend/top")).as_string());
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if (!mods.count(user_top))
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log_error("Top module '%s' not found!\n", ctx->nameOf(user_top));
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top = user_top;
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return;
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}
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// If not, look for a module with the top attribute set
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IdString top_by_attr;
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for (auto &mod : mods) {
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if (mod.second.is_top && !mod.second.is_box()) {
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if (top_by_attr != IdString())
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log_error("Found multiple modules with (* top *) set (including %s and %s).\n",
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ctx->nameOf(top_by_attr), ctx->nameOf(mod.first));
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top_by_attr = mod.first;
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}
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}
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if (top_by_attr != IdString()) {
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top = top_by_attr;
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return;
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}
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// Finally, attempt to autodetect the top module using hierarchy
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// (a module that is not a box and is not used as a cell by any other module)
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std::unordered_set<IdString> candidate_top;
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for (auto &mod : mods)
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if (!mod.second.is_box())
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candidate_top.insert(mod.first);
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for (auto &mod : mods)
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for (auto &c : mod.second.instantiated_celltypes)
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candidate_top.erase(c);
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if (candidate_top.size() != 1)
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log_error("Failed to autodetect top module, please specify using --top.\n");
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top = *(candidate_top.begin());
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}
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};
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} // namespace
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template <typename FrontendType> void run_frontend(Context *ctx, const FrontendType &impl) {}
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NEXTPNR_NAMESPACE_END |