Ignore band-edge and DC bins
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2c76c5cbe3
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@ -349,12 +349,18 @@ class HackRFSweepThread(RtlPowerBaseThread):
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# Skip first run through in case it was incomplete
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# otherwise the data_storage array sizes are setup incorrectly and mismatch later
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if not self.skip:
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sorted_data = sorted(zip(self.databuffer["x"], self.databuffer["y"]))
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self.databuffer["x"], self.databuffer["y"] = [list(x) for x in zip(*sorted_data)]
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self.data_storage.update(self.databuffer)
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self.skip = False
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self.databuffer = {"timestamp": [], "x": [], "y": []}
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self.databuffer["x"] += [centre_freq + i * 20e6 / self.fft_size for i in range(int(-self.fft_size/2), int(self.fft_size/2))]
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self.databuffer["y"] += [self.filter_nan(x) for x in data[1:]]
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fft_size_eighth = int(self.fft_size / 8)
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valid_bins = list(range(fft_size_eighth, fft_size_eighth * 3)) + list(range(fft_size_eighth * 5, fft_size_eighth * 7))
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for i in valid_bins:
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self.databuffer["x"].append(centre_freq + (i - self.fft_size/2) * 20e6 / self.fft_size)
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self.databuffer["y"].append(self.filter_nan(data[1+i]))
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self.prev_freq = centre_freq
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