440 lines
23 KiB
Plaintext
440 lines
23 KiB
Plaintext
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*** Running vivado
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with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
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****** Vivado v2022.2 (64-bit)
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**** SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
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**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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source design_1_wrapper.tcl -notrace
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'.
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Command: link_design -top design_1_wrapper -part xc7z010clg400-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-454] Reading design checkpoint 'd:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0'
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 819.957 ; gain = 0.000
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INFO: [Project 1-479] Netlist was created with Vivado 2022.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 949.297 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 949.297 ; gain = 534.078
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 974.305 ; gain = 25.008
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: 981f6d8d
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Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1435.113 ; gain = 460.809
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 122f0b1b6
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 122f0b1b6
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: f26bc340
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: f26bc340
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
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Phase 5 Shift Register Optimization | Checksum: f26bc340
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: f26bc340
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 24 | 0 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 1 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 15449c801
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1768.855 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 15449c801
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1768.855 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 15449c801
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1768.855 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 15449c801
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1768.855 ; gain = 819.559
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1768.855 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
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Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.396 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found.
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Phase 1.3 Build Placer Netlist Model | Checksum: 11ddc6f74
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.535 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 11ddc6f74
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.540 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 1 Placer Initialization | Checksum: 11ddc6f74
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.542 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Phase 2 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.544 . Memory (MB): peak = 1772.094 ; gain = 0.000
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INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
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Ending Placer Task | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1772.094 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1772.094 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1772.094 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1772.094 ; gain = 0.000
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Command: phys_opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
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Starting Initial Update Timing Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1776.805 ; gain = 4.711
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INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
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INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
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INFO: [Common 17-83] Releasing license: Implementation
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54 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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phys_opt_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1780.828 ; gain = 4.023
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Phase 1 Build RT Design
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Checksum: PlaceDB: 401615bb ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0
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Post Restoration Checksum: NetGraph: 752172cc NumContArr: 683b9ea3 Constraints: 0 Timing: 0
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Phase 1 Build RT Design | Checksum: dd5d116f
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Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1820.727 ; gain = 30.844
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Phase 2 Router Initialization
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: dd5d116f
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Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: dd5d116f
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Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871
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Number of Nodes with overlaps = 0
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Phase 2.3 Update Timing
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Phase 2.3 Update Timing | Checksum: f1e72516
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Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1828.551 ; gain = 38.668
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||
|
|
|
||
|
|
Router Utilization Summary
|
||
|
|
Global Vertical Routing Utilization = 0 %
|
||
|
|
Global Horizontal Routing Utilization = 0 %
|
||
|
|
Routable Net Status*
|
||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
||
|
|
Run report_route_status for detailed report.
|
||
|
|
Number of Failed Nets = 130
|
||
|
|
(Failed Nets is the sum of unrouted and partially routed nets)
|
||
|
|
Number of Unrouted Nets = 130
|
||
|
|
Number of Partially Routed Nets = 0
|
||
|
|
Number of Node Overlaps = 0
|
||
|
|
|
||
|
|
Phase 2 Router Initialization | Checksum: f1e72516
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 3 Initial Routing
|
||
|
|
|
||
|
|
Phase 3.1 Global Routing
|
||
|
|
Phase 3.1 Global Routing | Checksum: f1e72516
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
Number of Nodes with overlaps = 0
|
||
|
|
Phase 3 Initial Routing | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 4 Rip-up And Reroute
|
||
|
|
|
||
|
|
Phase 4.1 Global Iteration 0
|
||
|
|
Phase 4.1 Global Iteration 0 | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
Phase 4 Rip-up And Reroute | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 5 Delay and Skew Optimization
|
||
|
|
|
||
|
|
Phase 5.1 Delay CleanUp
|
||
|
|
Phase 5.1 Delay CleanUp | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 5.2 Clock Skew Optimization
|
||
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
Phase 5 Delay and Skew Optimization | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 6 Post Hold Fix
|
||
|
|
|
||
|
|
Phase 6.1 Hold Fix Iter
|
||
|
|
|
||
|
|
Phase 6.1.1 Update Timing
|
||
|
|
Phase 6.1.1 Update Timing | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
Phase 6.1 Hold Fix Iter | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
Phase 6 Post Hold Fix | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 7 Route finalize
|
||
|
|
|
||
|
|
Router Utilization Summary
|
||
|
|
Global Vertical Routing Utilization = 0 %
|
||
|
|
Global Horizontal Routing Utilization = 0 %
|
||
|
|
Routable Net Status*
|
||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
||
|
|
Run report_route_status for detailed report.
|
||
|
|
Number of Failed Nets = 0
|
||
|
|
(Failed Nets is the sum of unrouted and partially routed nets)
|
||
|
|
Number of Unrouted Nets = 0
|
||
|
|
Number of Partially Routed Nets = 0
|
||
|
|
Number of Node Overlaps = 0
|
||
|
|
|
||
|
|
Phase 7 Route finalize | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410
|
||
|
|
|
||
|
|
Phase 8 Verifying routed nets
|
||
|
|
|
||
|
|
Verification completed successfully
|
||
|
|
Phase 8 Verifying routed nets | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398
|
||
|
|
|
||
|
|
Phase 9 Depositing Routes
|
||
|
|
Phase 9 Depositing Routes | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398
|
||
|
|
|
||
|
|
Phase 10 Post Router Timing
|
||
|
|
Phase 10 Post Router Timing | Checksum: 9afecd01
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398
|
||
|
|
INFO: [Route 35-16] Router Completed Successfully
|
||
|
|
|
||
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398
|
||
|
|
|
||
|
|
Routing Is Done.
|
||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
||
|
|
63 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||
|
|
route_design completed successfully
|
||
|
|
route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1830.281 ; gain = 49.453
|
||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||
|
|
Writing XDEF routing.
|
||
|
|
Writing XDEF routing logical nets.
|
||
|
|
Writing XDEF routing special nets.
|
||
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1844.137 ; gain = 13.855
|
||
|
|
INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
|
||
|
|
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
||
|
|
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
||
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
||
|
|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt.
|
||
|
|
report_drc completed successfully
|
||
|
|
INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
||
|
|
Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||
|
|
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||
|
|
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
|
||
|
|
report_methodology completed successfully
|
||
|
|
INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
||
|
|
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||
|
|
Running Vector-less Activity Propagation...
|
||
|
|
|
||
|
|
Finished Running Vector-less Activity Propagation
|
||
|
|
75 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||
|
|
report_power completed successfully
|
||
|
|
INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
|
||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
|
||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
|
||
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
|
||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
|
||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||
|
|
Command: write_bitstream -force design_1_wrapper.bit
|
||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||
|
|
Running DRC as a precondition to command write_bitstream
|
||
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
||
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors
|
||
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||
|
|
Loading data files...
|
||
|
|
Loading site data...
|
||
|
|
Loading route data...
|
||
|
|
Processing options...
|
||
|
|
Creating bitmap...
|
||
|
|
Creating bitstream...
|
||
|
|
Writing bitstream ./design_1_wrapper.bit...
|
||
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||
|
|
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
||
|
|
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||
|
|
write_bitstream completed successfully
|
||
|
|
write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2295.570 ; gain = 432.406
|
||
|
|
INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:22:26 2024...
|