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zynq lvgl init

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zcy 2024-10-20 23:34:36 +08:00
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun Oct 20 22:20:28 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="0163bad0787f46ce826c3743d9378f81" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
</section>
</application>
</document>

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<?xml version="1.0" encoding="utf-8"?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">design_1</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0"/>
<edge id="e1" source="n0" target="n1"/>
</graph>
</graphml>

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<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1729431264"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1729431264"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1729431264"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1729431264"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="design_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="design_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\design_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\design_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
</CompositeFile>
</Root>

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project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc Normal file
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################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name processing_system7_0_FCLK_CLK0 -period 20 [get_pins processing_system7_0/FCLK_CLK0]
################################################################################

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project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v Normal file
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024
//Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule

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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
############################################################################
## File name : ps7_constraints.xdc
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: xc7z010clg400-1
## Device Size: xc7z010
## Package: clg400
## Speedgrade: -1
##
##
############################################################################
############################################################################
############################################################################
# Clock constraints #
############################################################################
create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.6
#The clocks are asynchronous, user should constrain them appropriately.#
############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################
# SPI 0 / mosi / MIO[21]
set_property iostandard "LVCMOS33" [get_ports "MIO[21]"]
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
set_property slew "slow" [get_ports "MIO[21]"]
set_property drive "8" [get_ports "MIO[21]"]
set_property pullup "TRUE" [get_ports "MIO[21]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"]
# SPI 0 / ss[0] / MIO[18]
set_property iostandard "LVCMOS33" [get_ports "MIO[18]"]
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
set_property slew "slow" [get_ports "MIO[18]"]
set_property drive "8" [get_ports "MIO[18]"]
set_property pullup "TRUE" [get_ports "MIO[18]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[18]"]
# SPI 0 / miso / MIO[17]
set_property iostandard "LVCMOS33" [get_ports "MIO[17]"]
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
set_property slew "slow" [get_ports "MIO[17]"]
set_property drive "8" [get_ports "MIO[17]"]
set_property pullup "TRUE" [get_ports "MIO[17]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[17]"]
# SPI 0 / sclk / MIO[16]
set_property iostandard "LVCMOS33" [get_ports "MIO[16]"]
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
set_property slew "slow" [get_ports "MIO[16]"]
set_property drive "8" [get_ports "MIO[16]"]
set_property pullup "TRUE" [get_ports "MIO[16]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"]
# UART 1 / rx / MIO[13]
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
set_property slew "slow" [get_ports "MIO[13]"]
set_property drive "8" [get_ports "MIO[13]"]
set_property pullup "TRUE" [get_ports "MIO[13]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[13]"]
# UART 1 / tx / MIO[12]
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
set_property slew "slow" [get_ports "MIO[12]"]
set_property drive "8" [get_ports "MIO[12]"]
set_property pullup "TRUE" [get_ports "MIO[12]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[12]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
set_property slew "FAST" [get_ports "DDR_VRP"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
set_property slew "FAST" [get_ports "DDR_VRN"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
set_property slew "SLOW" [get_ports "DDR_WEB"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
set_property slew "SLOW" [get_ports "DDR_ODT"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
set_property slew "FAST" [get_ports "DDR_DRSTB"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
set_property slew "FAST" [get_ports "DDR_DM[3]"]
set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
set_property slew "FAST" [get_ports "DDR_DM[2]"]
set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
set_property slew "FAST" [get_ports "DDR_DM[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
set_property slew "FAST" [get_ports "DDR_DM[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
set_property slew "SLOW" [get_ports "DDR_CS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
set_property slew "SLOW" [get_ports "DDR_CKE"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
set_property slew "FAST" [get_ports "DDR_Clk"]
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
set_property slew "FAST" [get_ports "DDR_Clk_n"]
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
set_property slew "fast" [get_ports "PS_PORB"]
set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
set_property slew "fast" [get_ports "PS_SRSTB"]
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
set_property slew "fast" [get_ports "PS_CLK"]

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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
// Date : Sun Oct 20 21:35:16 2024
// Host : destop1 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *)
module design_1_processing_system7_0_0(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n,
DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr,
DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule

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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
-- Date : Sun Oct 20 21:35:16 2024
-- Host : destop1 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl
-- Design : design_1_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_processing_system7_0_0 is
Port (
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end design_1_processing_system7_0_0;
architecture stub of design_1_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2022.2";
begin
end;

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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}

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/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
<designInfo version="1.0" >
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
<PARAMETERS >
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 18" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 16 .. 21" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="6" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 12 .. 13" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="54.563" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.239" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="79.5025" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="60.536" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="71.7715" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="104.5365" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="70.676" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="59.1615" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="81.319" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
</PARAMETERS>
<BUSINTERFACES >
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="0" />
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
</BUSINTERFACES>
<CLOCKOUTS >
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
</CLOCKOUTS>
</MODULE>
</designInfo>

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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include "design_1_processing_system7_0_0_sc.h"
#include "design_1_processing_system7_0_0.h"
#include "processing_system7_v5_5_tlm.h"
#include <map>
#include <string>
#ifdef XILINX_SIMULATOR
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void design_1_processing_system7_0_0::before_end_of_elaboration()
{
}
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void design_1_processing_system7_0_0::before_end_of_elaboration()
{
}
#endif // XM_SYSTEMC
#ifdef RIVIERA
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void design_1_processing_system7_0_0::before_end_of_elaboration()
{
}
#endif // RIVIERA
#ifdef VCSSYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
// Instantiate Socket Stubs
}
void design_1_processing_system7_0_0::before_end_of_elaboration()
{
}
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
// Instantiate Socket Stubs
}
void design_1_processing_system7_0_0::before_end_of_elaboration()
{
}
#endif // MTI_SYSTEMC
design_1_processing_system7_0_0::~design_1_processing_system7_0_0()
{
}
#ifdef MTI_SYSTEMC
SC_MODULE_EXPORT(design_1_processing_system7_0_0);
#endif
#ifdef XM_SYSTEMC
XMSC_MODULE_EXPORT(design_1_processing_system7_0_0);
#endif
#ifdef RIVIERA
SC_MODULE_EXPORT(design_1_processing_system7_0_0);
SC_REGISTER_BV(54);
#endif

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#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
#include "design_1_processing_system7_0_0_sc.h"
#ifdef XILINX_SIMULATOR
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
{
public:
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
{
public:
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout< bool > DDR_CAS_n;
sc_core::sc_inout< bool > DDR_CKE;
sc_core::sc_inout< bool > DDR_Clk_n;
sc_core::sc_inout< bool > DDR_Clk;
sc_core::sc_inout< bool > DDR_CS_n;
sc_core::sc_inout< bool > DDR_DRSTB;
sc_core::sc_inout< bool > DDR_ODT;
sc_core::sc_inout< bool > DDR_RAS_n;
sc_core::sc_inout< bool > DDR_WEB;
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout< bool > DDR_VRN;
sc_core::sc_inout< bool > DDR_VRP;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout< bool > PS_SRSTB;
sc_core::sc_inout< bool > PS_CLK;
sc_core::sc_inout< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // XM_SYSTEMC
#ifdef RIVIERA
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
{
public:
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // RIVIERA
#ifdef VCSSYSTEMC
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
{
public:
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
// Transactor stubs
// Socket stubs
};
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
{
public:
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
// Transactor stubs
// Socket stubs
};
#endif // MTI_SYSTEMC
#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_

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`timescale 1ns/1ps
//PORTS
bit CAN0_PHY_TX;
bit CAN0_PHY_RX;
bit CAN1_PHY_TX;
bit CAN1_PHY_RX;
bit [0 : 0] ENET0_GMII_TX_EN;
bit [0 : 0] ENET0_GMII_TX_ER;
bit ENET0_MDIO_MDC;
bit ENET0_MDIO_O;
bit ENET0_MDIO_T;
bit ENET0_PTP_DELAY_REQ_RX;
bit ENET0_PTP_DELAY_REQ_TX;
bit ENET0_PTP_PDELAY_REQ_RX;
bit ENET0_PTP_PDELAY_REQ_TX;
bit ENET0_PTP_PDELAY_RESP_RX;
bit ENET0_PTP_PDELAY_RESP_TX;
bit ENET0_PTP_SYNC_FRAME_RX;
bit ENET0_PTP_SYNC_FRAME_TX;
bit ENET0_SOF_RX;
bit ENET0_SOF_TX;
bit [7 : 0] ENET0_GMII_TXD;
bit ENET0_GMII_COL;
bit ENET0_GMII_CRS;
bit ENET0_GMII_RX_CLK;
bit ENET0_GMII_RX_DV;
bit ENET0_GMII_RX_ER;
bit ENET0_GMII_TX_CLK;
bit ENET0_MDIO_I;
bit ENET0_EXT_INTIN;
bit [7 : 0] ENET0_GMII_RXD;
bit [0 : 0] ENET1_GMII_TX_EN;
bit [0 : 0] ENET1_GMII_TX_ER;
bit ENET1_MDIO_MDC;
bit ENET1_MDIO_O;
bit ENET1_MDIO_T;
bit ENET1_PTP_DELAY_REQ_RX;
bit ENET1_PTP_DELAY_REQ_TX;
bit ENET1_PTP_PDELAY_REQ_RX;
bit ENET1_PTP_PDELAY_REQ_TX;
bit ENET1_PTP_PDELAY_RESP_RX;
bit ENET1_PTP_PDELAY_RESP_TX;
bit ENET1_PTP_SYNC_FRAME_RX;
bit ENET1_PTP_SYNC_FRAME_TX;
bit ENET1_SOF_RX;
bit ENET1_SOF_TX;
bit [7 : 0] ENET1_GMII_TXD;
bit ENET1_GMII_COL;
bit ENET1_GMII_CRS;
bit ENET1_GMII_RX_CLK;
bit ENET1_GMII_RX_DV;
bit ENET1_GMII_RX_ER;
bit ENET1_GMII_TX_CLK;
bit ENET1_MDIO_I;
bit ENET1_EXT_INTIN;
bit [7 : 0] ENET1_GMII_RXD;
bit [63 : 0] GPIO_I;
bit [63 : 0] GPIO_O;
bit [63 : 0] GPIO_T;
bit I2C0_SDA_I;
bit I2C0_SDA_O;
bit I2C0_SDA_T;
bit I2C0_SCL_I;
bit I2C0_SCL_O;
bit I2C0_SCL_T;
bit I2C1_SDA_I;
bit I2C1_SDA_O;
bit I2C1_SDA_T;
bit I2C1_SCL_I;
bit I2C1_SCL_O;
bit I2C1_SCL_T;
bit PJTAG_TCK;
bit PJTAG_TMS;
bit PJTAG_TDI;
bit PJTAG_TDO;
bit SDIO0_CLK;
bit SDIO0_CLK_FB;
bit SDIO0_CMD_O;
bit SDIO0_CMD_I;
bit SDIO0_CMD_T;
bit [3 : 0] SDIO0_DATA_I;
bit [3 : 0] SDIO0_DATA_O;
bit [3 : 0] SDIO0_DATA_T;
bit SDIO0_LED;
bit SDIO0_CDN;
bit SDIO0_WP;
bit SDIO0_BUSPOW;
bit [2 : 0] SDIO0_BUSVOLT;
bit SDIO1_CLK;
bit SDIO1_CLK_FB;
bit SDIO1_CMD_O;
bit SDIO1_CMD_I;
bit SDIO1_CMD_T;
bit [3 : 0] SDIO1_DATA_I;
bit [3 : 0] SDIO1_DATA_O;
bit [3 : 0] SDIO1_DATA_T;
bit SDIO1_LED;
bit SDIO1_CDN;
bit SDIO1_WP;
bit SDIO1_BUSPOW;
bit [2 : 0] SDIO1_BUSVOLT;
bit SPI0_SCLK_I;
bit SPI0_SCLK_O;
bit SPI0_SCLK_T;
bit SPI0_MOSI_I;
bit SPI0_MOSI_O;
bit SPI0_MOSI_T;
bit SPI0_MISO_I;
bit SPI0_MISO_O;
bit SPI0_MISO_T;
bit SPI0_SS_I;
bit SPI0_SS_O;
bit SPI0_SS1_O;
bit SPI0_SS2_O;
bit SPI0_SS_T;
bit SPI1_SCLK_I;
bit SPI1_SCLK_O;
bit SPI1_SCLK_T;
bit SPI1_MOSI_I;
bit SPI1_MOSI_O;
bit SPI1_MOSI_T;
bit SPI1_MISO_I;
bit SPI1_MISO_O;
bit SPI1_MISO_T;
bit SPI1_SS_I;
bit SPI1_SS_O;
bit SPI1_SS1_O;
bit SPI1_SS2_O;
bit SPI1_SS_T;
bit UART0_DTRN;
bit UART0_RTSN;
bit UART0_TX;
bit UART0_CTSN;
bit UART0_DCDN;
bit UART0_DSRN;
bit UART0_RIN;
bit UART0_RX;
bit UART1_DTRN;
bit UART1_RTSN;
bit UART1_TX;
bit UART1_CTSN;
bit UART1_DCDN;
bit UART1_DSRN;
bit UART1_RIN;
bit UART1_RX;
bit TTC0_WAVE0_OUT;
bit TTC0_WAVE1_OUT;
bit TTC0_WAVE2_OUT;
bit TTC0_CLK0_IN;
bit TTC0_CLK1_IN;
bit TTC0_CLK2_IN;
bit TTC1_WAVE0_OUT;
bit TTC1_WAVE1_OUT;
bit TTC1_WAVE2_OUT;
bit TTC1_CLK0_IN;
bit TTC1_CLK1_IN;
bit TTC1_CLK2_IN;
bit WDT_CLK_IN;
bit WDT_RST_OUT;
bit TRACE_CLK;
bit TRACE_CLK_OUT;
bit TRACE_CTL;
bit [1 : 0] TRACE_DATA;
bit [1 : 0] USB0_PORT_INDCTL;
bit USB0_VBUS_PWRSELECT;
bit USB0_VBUS_PWRFAULT;
bit [1 : 0] USB1_PORT_INDCTL;
bit USB1_VBUS_PWRSELECT;
bit USB1_VBUS_PWRFAULT;
bit SRAM_INTIN;
bit M_AXI_GP0_ARVALID;
bit M_AXI_GP0_AWVALID;
bit M_AXI_GP0_BREADY;
bit M_AXI_GP0_RREADY;
bit M_AXI_GP0_WLAST;
bit M_AXI_GP0_WVALID;
bit [11 : 0] M_AXI_GP0_ARID;
bit [11 : 0] M_AXI_GP0_AWID;
bit [11 : 0] M_AXI_GP0_WID;
bit [1 : 0] M_AXI_GP0_ARBURST;
bit [1 : 0] M_AXI_GP0_ARLOCK;
bit [2 : 0] M_AXI_GP0_ARSIZE;
bit [1 : 0] M_AXI_GP0_AWBURST;
bit [1 : 0] M_AXI_GP0_AWLOCK;
bit [2 : 0] M_AXI_GP0_AWSIZE;
bit [2 : 0] M_AXI_GP0_ARPROT;
bit [2 : 0] M_AXI_GP0_AWPROT;
bit [31 : 0] M_AXI_GP0_ARADDR;
bit [31 : 0] M_AXI_GP0_AWADDR;
bit [31 : 0] M_AXI_GP0_WDATA;
bit [3 : 0] M_AXI_GP0_ARCACHE;
bit [3 : 0] M_AXI_GP0_ARLEN;
bit [3 : 0] M_AXI_GP0_ARQOS;
bit [3 : 0] M_AXI_GP0_AWCACHE;
bit [3 : 0] M_AXI_GP0_AWLEN;
bit [3 : 0] M_AXI_GP0_AWQOS;
bit [3 : 0] M_AXI_GP0_WSTRB;
bit M_AXI_GP0_ACLK;
bit M_AXI_GP0_ARREADY;
bit M_AXI_GP0_AWREADY;
bit M_AXI_GP0_BVALID;
bit M_AXI_GP0_RLAST;
bit M_AXI_GP0_RVALID;
bit M_AXI_GP0_WREADY;
bit [11 : 0] M_AXI_GP0_BID;
bit [11 : 0] M_AXI_GP0_RID;
bit [1 : 0] M_AXI_GP0_BRESP;
bit [1 : 0] M_AXI_GP0_RRESP;
bit [31 : 0] M_AXI_GP0_RDATA;
bit M_AXI_GP1_ARVALID;
bit M_AXI_GP1_AWVALID;
bit M_AXI_GP1_BREADY;
bit M_AXI_GP1_RREADY;
bit M_AXI_GP1_WLAST;
bit M_AXI_GP1_WVALID;
bit [11 : 0] M_AXI_GP1_ARID;
bit [11 : 0] M_AXI_GP1_AWID;
bit [11 : 0] M_AXI_GP1_WID;
bit [1 : 0] M_AXI_GP1_ARBURST;
bit [1 : 0] M_AXI_GP1_ARLOCK;
bit [2 : 0] M_AXI_GP1_ARSIZE;
bit [1 : 0] M_AXI_GP1_AWBURST;
bit [1 : 0] M_AXI_GP1_AWLOCK;
bit [2 : 0] M_AXI_GP1_AWSIZE;
bit [2 : 0] M_AXI_GP1_ARPROT;
bit [2 : 0] M_AXI_GP1_AWPROT;
bit [31 : 0] M_AXI_GP1_ARADDR;
bit [31 : 0] M_AXI_GP1_AWADDR;
bit [31 : 0] M_AXI_GP1_WDATA;
bit [3 : 0] M_AXI_GP1_ARCACHE;
bit [3 : 0] M_AXI_GP1_ARLEN;
bit [3 : 0] M_AXI_GP1_ARQOS;
bit [3 : 0] M_AXI_GP1_AWCACHE;
bit [3 : 0] M_AXI_GP1_AWLEN;
bit [3 : 0] M_AXI_GP1_AWQOS;
bit [3 : 0] M_AXI_GP1_WSTRB;
bit M_AXI_GP1_ACLK;
bit M_AXI_GP1_ARREADY;
bit M_AXI_GP1_AWREADY;
bit M_AXI_GP1_BVALID;
bit M_AXI_GP1_RLAST;
bit M_AXI_GP1_RVALID;
bit M_AXI_GP1_WREADY;
bit [11 : 0] M_AXI_GP1_BID;
bit [11 : 0] M_AXI_GP1_RID;
bit [1 : 0] M_AXI_GP1_BRESP;
bit [1 : 0] M_AXI_GP1_RRESP;
bit [31 : 0] M_AXI_GP1_RDATA;
bit S_AXI_GP0_ARREADY;
bit S_AXI_GP0_AWREADY;
bit S_AXI_GP0_BVALID;
bit S_AXI_GP0_RLAST;
bit S_AXI_GP0_RVALID;
bit S_AXI_GP0_WREADY;
bit [1 : 0] S_AXI_GP0_BRESP;
bit [1 : 0] S_AXI_GP0_RRESP;
bit [31 : 0] S_AXI_GP0_RDATA;
bit [5 : 0] S_AXI_GP0_BID;
bit [5 : 0] S_AXI_GP0_RID;
bit S_AXI_GP0_ACLK;
bit S_AXI_GP0_ARVALID;
bit S_AXI_GP0_AWVALID;
bit S_AXI_GP0_BREADY;
bit S_AXI_GP0_RREADY;
bit S_AXI_GP0_WLAST;
bit S_AXI_GP0_WVALID;
bit [1 : 0] S_AXI_GP0_ARBURST;
bit [1 : 0] S_AXI_GP0_ARLOCK;
bit [2 : 0] S_AXI_GP0_ARSIZE;
bit [1 : 0] S_AXI_GP0_AWBURST;
bit [1 : 0] S_AXI_GP0_AWLOCK;
bit [2 : 0] S_AXI_GP0_AWSIZE;
bit [2 : 0] S_AXI_GP0_ARPROT;
bit [2 : 0] S_AXI_GP0_AWPROT;
bit [31 : 0] S_AXI_GP0_ARADDR;
bit [31 : 0] S_AXI_GP0_AWADDR;
bit [31 : 0] S_AXI_GP0_WDATA;
bit [3 : 0] S_AXI_GP0_ARCACHE;
bit [3 : 0] S_AXI_GP0_ARLEN;
bit [3 : 0] S_AXI_GP0_ARQOS;
bit [3 : 0] S_AXI_GP0_AWCACHE;
bit [3 : 0] S_AXI_GP0_AWLEN;
bit [3 : 0] S_AXI_GP0_AWQOS;
bit [3 : 0] S_AXI_GP0_WSTRB;
bit [5 : 0] S_AXI_GP0_ARID;
bit [5 : 0] S_AXI_GP0_AWID;
bit [5 : 0] S_AXI_GP0_WID;
bit S_AXI_GP1_ARREADY;
bit S_AXI_GP1_AWREADY;
bit S_AXI_GP1_BVALID;
bit S_AXI_GP1_RLAST;
bit S_AXI_GP1_RVALID;
bit S_AXI_GP1_WREADY;
bit [1 : 0] S_AXI_GP1_BRESP;
bit [1 : 0] S_AXI_GP1_RRESP;
bit [31 : 0] S_AXI_GP1_RDATA;
bit [5 : 0] S_AXI_GP1_BID;
bit [5 : 0] S_AXI_GP1_RID;
bit S_AXI_GP1_ACLK;
bit S_AXI_GP1_ARVALID;
bit S_AXI_GP1_AWVALID;
bit S_AXI_GP1_BREADY;
bit S_AXI_GP1_RREADY;
bit S_AXI_GP1_WLAST;
bit S_AXI_GP1_WVALID;
bit [1 : 0] S_AXI_GP1_ARBURST;
bit [1 : 0] S_AXI_GP1_ARLOCK;
bit [2 : 0] S_AXI_GP1_ARSIZE;
bit [1 : 0] S_AXI_GP1_AWBURST;
bit [1 : 0] S_AXI_GP1_AWLOCK;
bit [2 : 0] S_AXI_GP1_AWSIZE;
bit [2 : 0] S_AXI_GP1_ARPROT;
bit [2 : 0] S_AXI_GP1_AWPROT;
bit [31 : 0] S_AXI_GP1_ARADDR;
bit [31 : 0] S_AXI_GP1_AWADDR;
bit [31 : 0] S_AXI_GP1_WDATA;
bit [3 : 0] S_AXI_GP1_ARCACHE;
bit [3 : 0] S_AXI_GP1_ARLEN;
bit [3 : 0] S_AXI_GP1_ARQOS;
bit [3 : 0] S_AXI_GP1_AWCACHE;
bit [3 : 0] S_AXI_GP1_AWLEN;
bit [3 : 0] S_AXI_GP1_AWQOS;
bit [3 : 0] S_AXI_GP1_WSTRB;
bit [5 : 0] S_AXI_GP1_ARID;
bit [5 : 0] S_AXI_GP1_AWID;
bit [5 : 0] S_AXI_GP1_WID;
bit S_AXI_ACP_ARREADY;
bit S_AXI_ACP_AWREADY;
bit S_AXI_ACP_BVALID;
bit S_AXI_ACP_RLAST;
bit S_AXI_ACP_RVALID;
bit S_AXI_ACP_WREADY;
bit [1 : 0] S_AXI_ACP_BRESP;
bit [1 : 0] S_AXI_ACP_RRESP;
bit [2 : 0] S_AXI_ACP_BID;
bit [2 : 0] S_AXI_ACP_RID;
bit [63 : 0] S_AXI_ACP_RDATA;
bit S_AXI_ACP_ACLK;
bit S_AXI_ACP_ARVALID;
bit S_AXI_ACP_AWVALID;
bit S_AXI_ACP_BREADY;
bit S_AXI_ACP_RREADY;
bit S_AXI_ACP_WLAST;
bit S_AXI_ACP_WVALID;
bit [2 : 0] S_AXI_ACP_ARID;
bit [2 : 0] S_AXI_ACP_ARPROT;
bit [2 : 0] S_AXI_ACP_AWID;
bit [2 : 0] S_AXI_ACP_AWPROT;
bit [2 : 0] S_AXI_ACP_WID;
bit [31 : 0] S_AXI_ACP_ARADDR;
bit [31 : 0] S_AXI_ACP_AWADDR;
bit [3 : 0] S_AXI_ACP_ARCACHE;
bit [3 : 0] S_AXI_ACP_ARLEN;
bit [3 : 0] S_AXI_ACP_ARQOS;
bit [3 : 0] S_AXI_ACP_AWCACHE;
bit [3 : 0] S_AXI_ACP_AWLEN;
bit [3 : 0] S_AXI_ACP_AWQOS;
bit [1 : 0] S_AXI_ACP_ARBURST;
bit [1 : 0] S_AXI_ACP_ARLOCK;
bit [2 : 0] S_AXI_ACP_ARSIZE;
bit [1 : 0] S_AXI_ACP_AWBURST;
bit [1 : 0] S_AXI_ACP_AWLOCK;
bit [2 : 0] S_AXI_ACP_AWSIZE;
bit [4 : 0] S_AXI_ACP_ARUSER;
bit [4 : 0] S_AXI_ACP_AWUSER;
bit [63 : 0] S_AXI_ACP_WDATA;
bit [7 : 0] S_AXI_ACP_WSTRB;
bit S_AXI_HP0_ARREADY;
bit S_AXI_HP0_AWREADY;
bit S_AXI_HP0_BVALID;
bit S_AXI_HP0_RLAST;
bit S_AXI_HP0_RVALID;
bit S_AXI_HP0_WREADY;
bit [1 : 0] S_AXI_HP0_BRESP;
bit [1 : 0] S_AXI_HP0_RRESP;
bit [5 : 0] S_AXI_HP0_BID;
bit [5 : 0] S_AXI_HP0_RID;
bit [63 : 0] S_AXI_HP0_RDATA;
bit [7 : 0] S_AXI_HP0_RCOUNT;
bit [7 : 0] S_AXI_HP0_WCOUNT;
bit [2 : 0] S_AXI_HP0_RACOUNT;
bit [5 : 0] S_AXI_HP0_WACOUNT;
bit S_AXI_HP0_ACLK;
bit S_AXI_HP0_ARVALID;
bit S_AXI_HP0_AWVALID;
bit S_AXI_HP0_BREADY;
bit S_AXI_HP0_RDISSUECAP1_EN;
bit S_AXI_HP0_RREADY;
bit S_AXI_HP0_WLAST;
bit S_AXI_HP0_WRISSUECAP1_EN;
bit S_AXI_HP0_WVALID;
bit [1 : 0] S_AXI_HP0_ARBURST;
bit [1 : 0] S_AXI_HP0_ARLOCK;
bit [2 : 0] S_AXI_HP0_ARSIZE;
bit [1 : 0] S_AXI_HP0_AWBURST;
bit [1 : 0] S_AXI_HP0_AWLOCK;
bit [2 : 0] S_AXI_HP0_AWSIZE;
bit [2 : 0] S_AXI_HP0_ARPROT;
bit [2 : 0] S_AXI_HP0_AWPROT;
bit [31 : 0] S_AXI_HP0_ARADDR;
bit [31 : 0] S_AXI_HP0_AWADDR;
bit [3 : 0] S_AXI_HP0_ARCACHE;
bit [3 : 0] S_AXI_HP0_ARLEN;
bit [3 : 0] S_AXI_HP0_ARQOS;
bit [3 : 0] S_AXI_HP0_AWCACHE;
bit [3 : 0] S_AXI_HP0_AWLEN;
bit [3 : 0] S_AXI_HP0_AWQOS;
bit [5 : 0] S_AXI_HP0_ARID;
bit [5 : 0] S_AXI_HP0_AWID;
bit [5 : 0] S_AXI_HP0_WID;
bit [63 : 0] S_AXI_HP0_WDATA;
bit [7 : 0] S_AXI_HP0_WSTRB;
bit S_AXI_HP1_ARREADY;
bit S_AXI_HP1_AWREADY;
bit S_AXI_HP1_BVALID;
bit S_AXI_HP1_RLAST;
bit S_AXI_HP1_RVALID;
bit S_AXI_HP1_WREADY;
bit [1 : 0] S_AXI_HP1_BRESP;
bit [1 : 0] S_AXI_HP1_RRESP;
bit [5 : 0] S_AXI_HP1_BID;
bit [5 : 0] S_AXI_HP1_RID;
bit [63 : 0] S_AXI_HP1_RDATA;
bit [7 : 0] S_AXI_HP1_RCOUNT;
bit [7 : 0] S_AXI_HP1_WCOUNT;
bit [2 : 0] S_AXI_HP1_RACOUNT;
bit [5 : 0] S_AXI_HP1_WACOUNT;
bit S_AXI_HP1_ACLK;
bit S_AXI_HP1_ARVALID;
bit S_AXI_HP1_AWVALID;
bit S_AXI_HP1_BREADY;
bit S_AXI_HP1_RDISSUECAP1_EN;
bit S_AXI_HP1_RREADY;
bit S_AXI_HP1_WLAST;
bit S_AXI_HP1_WRISSUECAP1_EN;
bit S_AXI_HP1_WVALID;
bit [1 : 0] S_AXI_HP1_ARBURST;
bit [1 : 0] S_AXI_HP1_ARLOCK;
bit [2 : 0] S_AXI_HP1_ARSIZE;
bit [1 : 0] S_AXI_HP1_AWBURST;
bit [1 : 0] S_AXI_HP1_AWLOCK;
bit [2 : 0] S_AXI_HP1_AWSIZE;
bit [2 : 0] S_AXI_HP1_ARPROT;
bit [2 : 0] S_AXI_HP1_AWPROT;
bit [31 : 0] S_AXI_HP1_ARADDR;
bit [31 : 0] S_AXI_HP1_AWADDR;
bit [3 : 0] S_AXI_HP1_ARCACHE;
bit [3 : 0] S_AXI_HP1_ARLEN;
bit [3 : 0] S_AXI_HP1_ARQOS;
bit [3 : 0] S_AXI_HP1_AWCACHE;
bit [3 : 0] S_AXI_HP1_AWLEN;
bit [3 : 0] S_AXI_HP1_AWQOS;
bit [5 : 0] S_AXI_HP1_ARID;
bit [5 : 0] S_AXI_HP1_AWID;
bit [5 : 0] S_AXI_HP1_WID;
bit [63 : 0] S_AXI_HP1_WDATA;
bit [7 : 0] S_AXI_HP1_WSTRB;
bit S_AXI_HP2_ARREADY;
bit S_AXI_HP2_AWREADY;
bit S_AXI_HP2_BVALID;
bit S_AXI_HP2_RLAST;
bit S_AXI_HP2_RVALID;
bit S_AXI_HP2_WREADY;
bit [1 : 0] S_AXI_HP2_BRESP;
bit [1 : 0] S_AXI_HP2_RRESP;
bit [5 : 0] S_AXI_HP2_BID;
bit [5 : 0] S_AXI_HP2_RID;
bit [63 : 0] S_AXI_HP2_RDATA;
bit [7 : 0] S_AXI_HP2_RCOUNT;
bit [7 : 0] S_AXI_HP2_WCOUNT;
bit [2 : 0] S_AXI_HP2_RACOUNT;
bit [5 : 0] S_AXI_HP2_WACOUNT;
bit S_AXI_HP2_ACLK;
bit S_AXI_HP2_ARVALID;
bit S_AXI_HP2_AWVALID;
bit S_AXI_HP2_BREADY;
bit S_AXI_HP2_RDISSUECAP1_EN;
bit S_AXI_HP2_RREADY;
bit S_AXI_HP2_WLAST;
bit S_AXI_HP2_WRISSUECAP1_EN;
bit S_AXI_HP2_WVALID;
bit [1 : 0] S_AXI_HP2_ARBURST;
bit [1 : 0] S_AXI_HP2_ARLOCK;
bit [2 : 0] S_AXI_HP2_ARSIZE;
bit [1 : 0] S_AXI_HP2_AWBURST;
bit [1 : 0] S_AXI_HP2_AWLOCK;
bit [2 : 0] S_AXI_HP2_AWSIZE;
bit [2 : 0] S_AXI_HP2_ARPROT;
bit [2 : 0] S_AXI_HP2_AWPROT;
bit [31 : 0] S_AXI_HP2_ARADDR;
bit [31 : 0] S_AXI_HP2_AWADDR;
bit [3 : 0] S_AXI_HP2_ARCACHE;
bit [3 : 0] S_AXI_HP2_ARLEN;
bit [3 : 0] S_AXI_HP2_ARQOS;
bit [3 : 0] S_AXI_HP2_AWCACHE;
bit [3 : 0] S_AXI_HP2_AWLEN;
bit [3 : 0] S_AXI_HP2_AWQOS;
bit [5 : 0] S_AXI_HP2_ARID;
bit [5 : 0] S_AXI_HP2_AWID;
bit [5 : 0] S_AXI_HP2_WID;
bit [63 : 0] S_AXI_HP2_WDATA;
bit [7 : 0] S_AXI_HP2_WSTRB;
bit S_AXI_HP3_ARREADY;
bit S_AXI_HP3_AWREADY;
bit S_AXI_HP3_BVALID;
bit S_AXI_HP3_RLAST;
bit S_AXI_HP3_RVALID;
bit S_AXI_HP3_WREADY;
bit [1 : 0] S_AXI_HP3_BRESP;
bit [1 : 0] S_AXI_HP3_RRESP;
bit [5 : 0] S_AXI_HP3_BID;
bit [5 : 0] S_AXI_HP3_RID;
bit [63 : 0] S_AXI_HP3_RDATA;
bit [7 : 0] S_AXI_HP3_RCOUNT;
bit [7 : 0] S_AXI_HP3_WCOUNT;
bit [2 : 0] S_AXI_HP3_RACOUNT;
bit [5 : 0] S_AXI_HP3_WACOUNT;
bit S_AXI_HP3_ACLK;
bit S_AXI_HP3_ARVALID;
bit S_AXI_HP3_AWVALID;
bit S_AXI_HP3_BREADY;
bit S_AXI_HP3_RDISSUECAP1_EN;
bit S_AXI_HP3_RREADY;
bit S_AXI_HP3_WLAST;
bit S_AXI_HP3_WRISSUECAP1_EN;
bit S_AXI_HP3_WVALID;
bit [1 : 0] S_AXI_HP3_ARBURST;
bit [1 : 0] S_AXI_HP3_ARLOCK;
bit [2 : 0] S_AXI_HP3_ARSIZE;
bit [1 : 0] S_AXI_HP3_AWBURST;
bit [1 : 0] S_AXI_HP3_AWLOCK;
bit [2 : 0] S_AXI_HP3_AWSIZE;
bit [2 : 0] S_AXI_HP3_ARPROT;
bit [2 : 0] S_AXI_HP3_AWPROT;
bit [31 : 0] S_AXI_HP3_ARADDR;
bit [31 : 0] S_AXI_HP3_AWADDR;
bit [3 : 0] S_AXI_HP3_ARCACHE;
bit [3 : 0] S_AXI_HP3_ARLEN;
bit [3 : 0] S_AXI_HP3_ARQOS;
bit [3 : 0] S_AXI_HP3_AWCACHE;
bit [3 : 0] S_AXI_HP3_AWLEN;
bit [3 : 0] S_AXI_HP3_AWQOS;
bit [5 : 0] S_AXI_HP3_ARID;
bit [5 : 0] S_AXI_HP3_AWID;
bit [5 : 0] S_AXI_HP3_WID;
bit [63 : 0] S_AXI_HP3_WDATA;
bit [7 : 0] S_AXI_HP3_WSTRB;
bit IRQ_P2F_DMAC_ABORT;
bit IRQ_P2F_DMAC0;
bit IRQ_P2F_DMAC1;
bit IRQ_P2F_DMAC2;
bit IRQ_P2F_DMAC3;
bit IRQ_P2F_DMAC4;
bit IRQ_P2F_DMAC5;
bit IRQ_P2F_DMAC6;
bit IRQ_P2F_DMAC7;
bit IRQ_P2F_SMC;
bit IRQ_P2F_QSPI;
bit IRQ_P2F_CTI;
bit IRQ_P2F_GPIO;
bit IRQ_P2F_USB0;
bit IRQ_P2F_ENET0;
bit IRQ_P2F_ENET_WAKE0;
bit IRQ_P2F_SDIO0;
bit IRQ_P2F_I2C0;
bit IRQ_P2F_SPI0;
bit IRQ_P2F_UART0;
bit IRQ_P2F_CAN0;
bit IRQ_P2F_USB1;
bit IRQ_P2F_ENET1;
bit IRQ_P2F_ENET_WAKE1;
bit IRQ_P2F_SDIO1;
bit IRQ_P2F_I2C1;
bit IRQ_P2F_SPI1;
bit IRQ_P2F_UART1;
bit IRQ_P2F_CAN1;
bit [0 : 0] IRQ_F2P;
bit Core0_nFIQ;
bit Core0_nIRQ;
bit Core1_nFIQ;
bit Core1_nIRQ;
bit [1 : 0] DMA0_DATYPE;
bit DMA0_DAVALID;
bit DMA0_DRREADY;
bit [1 : 0] DMA1_DATYPE;
bit DMA1_DAVALID;
bit DMA1_DRREADY;
bit [1 : 0] DMA2_DATYPE;
bit DMA2_DAVALID;
bit DMA2_DRREADY;
bit [1 : 0] DMA3_DATYPE;
bit DMA3_DAVALID;
bit DMA3_DRREADY;
bit DMA0_ACLK;
bit DMA0_DAREADY;
bit DMA0_DRLAST;
bit DMA0_DRVALID;
bit DMA1_ACLK;
bit DMA1_DAREADY;
bit DMA1_DRLAST;
bit DMA1_DRVALID;
bit DMA2_ACLK;
bit DMA2_DAREADY;
bit DMA2_DRLAST;
bit DMA2_DRVALID;
bit DMA3_ACLK;
bit DMA3_DAREADY;
bit DMA3_DRLAST;
bit DMA3_DRVALID;
bit [1 : 0] DMA0_DRTYPE;
bit [1 : 0] DMA1_DRTYPE;
bit [1 : 0] DMA2_DRTYPE;
bit [1 : 0] DMA3_DRTYPE;
bit FCLK_CLK0;
bit FCLK_CLK1;
bit FCLK_CLK2;
bit FCLK_CLK3;
bit FCLK_CLKTRIG0_N;
bit FCLK_CLKTRIG1_N;
bit FCLK_CLKTRIG2_N;
bit FCLK_CLKTRIG3_N;
bit FCLK_RESET0_N;
bit FCLK_RESET1_N;
bit FCLK_RESET2_N;
bit FCLK_RESET3_N;
bit [31 : 0] FTMD_TRACEIN_DATA;
bit FTMD_TRACEIN_VALID;
bit FTMD_TRACEIN_CLK;
bit [3 : 0] FTMD_TRACEIN_ATID;
bit FTMT_F2P_TRIG_0;
bit FTMT_F2P_TRIGACK_0;
bit FTMT_F2P_TRIG_1;
bit FTMT_F2P_TRIGACK_1;
bit FTMT_F2P_TRIG_2;
bit FTMT_F2P_TRIGACK_2;
bit FTMT_F2P_TRIG_3;
bit FTMT_F2P_TRIGACK_3;
bit [31 : 0] FTMT_F2P_DEBUG;
bit FTMT_P2F_TRIGACK_0;
bit FTMT_P2F_TRIG_0;
bit FTMT_P2F_TRIGACK_1;
bit FTMT_P2F_TRIG_1;
bit FTMT_P2F_TRIGACK_2;
bit FTMT_P2F_TRIG_2;
bit FTMT_P2F_TRIGACK_3;
bit FTMT_P2F_TRIG_3;
bit [31 : 0] FTMT_P2F_DEBUG;
bit FPGA_IDLE_N;
bit EVENT_EVENTO;
bit [1 : 0] EVENT_STANDBYWFE;
bit [1 : 0] EVENT_STANDBYWFI;
bit EVENT_EVENTI;
bit [3 : 0] DDR_ARB;
bit [53 : 0] MIO;
bit DDR_CAS_n;
bit DDR_CKE;
bit DDR_Clk_n;
bit DDR_Clk;
bit DDR_CS_n;
bit DDR_DRSTB;
bit DDR_ODT;
bit DDR_RAS_n;
bit DDR_WEB;
bit [2 : 0] DDR_BankAddr;
bit [14 : 0] DDR_Addr;
bit DDR_VRN;
bit DDR_VRP;
bit [3 : 0] DDR_DM;
bit [31 : 0] DDR_DQ;
bit [3 : 0] DDR_DQS_n;
bit [3 : 0] DDR_DQS;
bit PS_SRSTB;
bit PS_CLK;
bit PS_PORB;
//MODULE DECLARATION
module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
//PARAMETERS
parameter C_EN_EMIO_PJTAG = 0;
parameter C_EN_EMIO_ENET0 = 0;
parameter C_EN_EMIO_ENET1 = 0;
parameter C_EN_EMIO_TRACE = 0;
parameter C_INCLUDE_TRACE_BUFFER = 0;
parameter C_TRACE_BUFFER_FIFO_SIZE = 128;
parameter USE_TRACE_DATA_EDGE_DETECTOR = 0;
parameter C_TRACE_PIPELINE_WIDTH = 8;
parameter C_TRACE_BUFFER_CLOCK_DELAY = 12;
parameter C_EMIO_GPIO_WIDTH = 64;
parameter C_INCLUDE_ACP_TRANS_CHECK = 0;
parameter C_USE_DEFAULT_ACP_USER_VAL = 0;
parameter C_S_AXI_ACP_ARUSER_VAL = 31;
parameter C_S_AXI_ACP_AWUSER_VAL = 31;
parameter C_M_AXI_GP0_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ID_WIDTH = 12;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
parameter C_S_AXI_GP0_ID_WIDTH = 6;
parameter C_S_AXI_GP1_ID_WIDTH = 6;
parameter C_S_AXI_ACP_ID_WIDTH = 3;
parameter C_S_AXI_HP0_ID_WIDTH = 6;
parameter C_S_AXI_HP0_DATA_WIDTH = 64;
parameter C_S_AXI_HP1_ID_WIDTH = 6;
parameter C_S_AXI_HP1_DATA_WIDTH = 64;
parameter C_S_AXI_HP2_ID_WIDTH = 6;
parameter C_S_AXI_HP2_DATA_WIDTH = 64;
parameter C_S_AXI_HP3_ID_WIDTH = 6;
parameter C_S_AXI_HP3_DATA_WIDTH = 64;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_NUM_F2P_INTR_INPUTS = 1;
parameter C_IRQ_F2P_MODE = "DIRECT";
parameter C_DQ_WIDTH = 32;
parameter C_DQS_WIDTH = 4;
parameter C_DM_WIDTH = 4;
parameter C_MIO_PRIMITIVE = 54;
parameter C_TRACE_INTERNAL_WIDTH = 2;
parameter C_USE_AXI_NONSECURE = 0;
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 0;
parameter C_USE_S_AXI_GP1 = 0;
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_USE_S_AXI_ACP = 0;
parameter C_PS7_SI_REV = "PRODUCTION";
parameter C_FCLK_CLK0_BUF = "TRUE";
parameter C_FCLK_CLK1_BUF = "FALSE";
parameter C_FCLK_CLK2_BUF = "FALSE";
parameter C_FCLK_CLK3_BUF = "FALSE";
parameter C_PACKAGE_NAME = "clg400";
parameter C_GP0_EN_MODIFIABLE_TXN = "1";
parameter C_GP1_EN_MODIFIABLE_TXN = "1";
//INPUT AND OUTPUT PORTS
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53 : 0] MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2 : 0] DDR_BankAddr;
inout [14 : 0] DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3 : 0] DDR_DM;
inout [31 : 0] DDR_DQ;
inout [3 : 0] DDR_DQS_n;
inout [3 : 0] DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
//REG DECLARATIONS
reg FCLK_CLK0;
reg FCLK_RESET0_N;
string ip_name;
reg disable_port;
//DPI DECLARATIONS
import "DPI-C" function void ps7_set_ip_context(input string ip_name);
import "DPI-C" function void ps7_set_str_param(input string name,input string val);
import "DPI-C" function void ps7_set_int_param(input string name,input longint val);
import "DPI-C" function void ps7_init_c_model();
import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0();
export "DPI-C" function ps7_stop_sim;
function void ps7_stop_sim();
$display("End of simulation");
$finish(0);
endfunction
export "DPI-C" function ps7_get_time;
function real ps7_get_time();
ps7_get_time = $time;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET0_N;
function void ps7_set_output_pins_FCLK_RESET0_N(int value);
FCLK_RESET0_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET1_N;
function void ps7_set_output_pins_FCLK_RESET1_N(int value);
FCLK_RESET1_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET2_N;
function void ps7_set_output_pins_FCLK_RESET2_N(int value);
FCLK_RESET2_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET3_N;
function void ps7_set_output_pins_FCLK_RESET3_N(int value);
FCLK_RESET3_N = value;
endfunction
//INITIAL BLOCK
initial
begin
$sformat(ip_name,"%m");
ps7_set_ip_context(ip_name);
ps7_set_int_param ( "C_EN_EMIO_PJTAG",C_EN_EMIO_PJTAG );
ps7_set_int_param ( "C_EN_EMIO_ENET0",C_EN_EMIO_ENET0 );
ps7_set_int_param ( "C_EN_EMIO_ENET1",C_EN_EMIO_ENET1 );
ps7_set_int_param ( "C_EN_EMIO_TRACE",C_EN_EMIO_TRACE );
ps7_set_int_param ( "C_INCLUDE_TRACE_BUFFER",C_INCLUDE_TRACE_BUFFER );
ps7_set_int_param ( "C_TRACE_BUFFER_FIFO_SIZE",C_TRACE_BUFFER_FIFO_SIZE );
ps7_set_int_param ( "USE_TRACE_DATA_EDGE_DETECTOR",USE_TRACE_DATA_EDGE_DETECTOR );
ps7_set_int_param ( "C_TRACE_PIPELINE_WIDTH",C_TRACE_PIPELINE_WIDTH );
ps7_set_int_param ( "C_TRACE_BUFFER_CLOCK_DELAY",C_TRACE_BUFFER_CLOCK_DELAY );
ps7_set_int_param ( "C_EMIO_GPIO_WIDTH",C_EMIO_GPIO_WIDTH );
ps7_set_int_param ( "C_INCLUDE_ACP_TRANS_CHECK",C_INCLUDE_ACP_TRANS_CHECK );
ps7_set_int_param ( "C_USE_DEFAULT_ACP_USER_VAL",C_USE_DEFAULT_ACP_USER_VAL );
ps7_set_int_param ( "C_S_AXI_ACP_ARUSER_VAL",C_S_AXI_ACP_ARUSER_VAL );
ps7_set_int_param ( "C_S_AXI_ACP_AWUSER_VAL",C_S_AXI_ACP_AWUSER_VAL );
ps7_set_int_param ( "C_M_AXI_GP0_ID_WIDTH",C_M_AXI_GP0_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP0_ENABLE_STATIC_REMAP",C_M_AXI_GP0_ENABLE_STATIC_REMAP );
ps7_set_int_param ( "C_M_AXI_GP1_ID_WIDTH",C_M_AXI_GP1_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP1_ENABLE_STATIC_REMAP",C_M_AXI_GP1_ENABLE_STATIC_REMAP );
ps7_set_int_param ( "C_S_AXI_GP0_ID_WIDTH",C_S_AXI_GP0_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_GP1_ID_WIDTH",C_S_AXI_GP1_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_ACP_ID_WIDTH",C_S_AXI_ACP_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP0_ID_WIDTH",C_S_AXI_HP0_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP0_DATA_WIDTH",C_S_AXI_HP0_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP1_ID_WIDTH",C_S_AXI_HP1_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP1_DATA_WIDTH",C_S_AXI_HP1_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP2_ID_WIDTH",C_S_AXI_HP2_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP2_DATA_WIDTH",C_S_AXI_HP2_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP3_ID_WIDTH",C_S_AXI_HP3_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP3_DATA_WIDTH",C_S_AXI_HP3_DATA_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP0_THREAD_ID_WIDTH",C_M_AXI_GP0_THREAD_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP1_THREAD_ID_WIDTH",C_M_AXI_GP1_THREAD_ID_WIDTH );
ps7_set_int_param ( "C_NUM_F2P_INTR_INPUTS",C_NUM_F2P_INTR_INPUTS );
ps7_set_str_param ( "C_IRQ_F2P_MODE",C_IRQ_F2P_MODE );
ps7_set_int_param ( "C_DQ_WIDTH",C_DQ_WIDTH );
ps7_set_int_param ( "C_DQS_WIDTH",C_DQS_WIDTH );
ps7_set_int_param ( "C_DM_WIDTH",C_DM_WIDTH );
ps7_set_int_param ( "C_MIO_PRIMITIVE",C_MIO_PRIMITIVE );
ps7_set_int_param ( "C_TRACE_INTERNAL_WIDTH",C_TRACE_INTERNAL_WIDTH );
ps7_set_int_param ( "C_USE_AXI_NONSECURE",C_USE_AXI_NONSECURE );
ps7_set_int_param ( "C_USE_M_AXI_GP0",C_USE_M_AXI_GP0 );
ps7_set_int_param ( "C_USE_M_AXI_GP1",C_USE_M_AXI_GP1 );
ps7_set_int_param ( "C_USE_S_AXI_GP0",C_USE_S_AXI_GP0 );
ps7_set_int_param ( "C_USE_S_AXI_GP1",C_USE_S_AXI_GP1 );
ps7_set_int_param ( "C_USE_S_AXI_HP0",C_USE_S_AXI_HP0 );
ps7_set_int_param ( "C_USE_S_AXI_HP1",C_USE_S_AXI_HP1 );
ps7_set_int_param ( "C_USE_S_AXI_HP2",C_USE_S_AXI_HP2 );
ps7_set_int_param ( "C_USE_S_AXI_HP3",C_USE_S_AXI_HP3 );
ps7_set_int_param ( "C_USE_S_AXI_ACP",C_USE_S_AXI_ACP );
ps7_set_str_param ( "C_PS7_SI_REV",C_PS7_SI_REV );
ps7_set_str_param ( "C_FCLK_CLK0_BUF",C_FCLK_CLK0_BUF );
ps7_set_str_param ( "C_FCLK_CLK1_BUF",C_FCLK_CLK1_BUF );
ps7_set_str_param ( "C_FCLK_CLK2_BUF",C_FCLK_CLK2_BUF );
ps7_set_str_param ( "C_FCLK_CLK3_BUF",C_FCLK_CLK3_BUF );
ps7_set_str_param ( "C_PACKAGE_NAME",C_PACKAGE_NAME );
ps7_set_str_param ( "C_GP0_EN_MODIFIABLE_TXN",C_GP0_EN_MODIFIABLE_TXN );
ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN );
ps7_init_c_model();
end
initial
begin
FCLK_CLK0 = 1'b0;
end
always #(10.0) FCLK_CLK0 <= ~FCLK_CLK0;
always@(posedge FCLK_CLK0)
begin
ps7_set_ip_context(ip_name);
ps7_simulate_single_cycle_FCLK_CLK0();
end
endmodule

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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v Normal file
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@ -0,0 +1,500 @@
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_vip_v1_0_15 #(
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(50.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule

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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include "design_1_processing_system7_0_0_sc.h"
#include "processing_system7_v5_5_tlm.h"
#include <map>
#include <string>
design_1_processing_system7_0_0_sc::design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
{
// configure connectivity manager
xsc::utils::xsc_sim_manager::addInstance("design_1_processing_system7_0_0", this);
// initialize module
xsc::common_cpp::properties model_param_props;
model_param_props.addLong("C_EN_EMIO_PJTAG", "0");
model_param_props.addLong("C_EN_EMIO_ENET0", "0");
model_param_props.addLong("C_EN_EMIO_ENET1", "0");
model_param_props.addLong("C_EN_EMIO_TRACE", "0");
model_param_props.addLong("C_INCLUDE_TRACE_BUFFER", "0");
model_param_props.addLong("C_TRACE_BUFFER_FIFO_SIZE", "128");
model_param_props.addLong("USE_TRACE_DATA_EDGE_DETECTOR", "0");
model_param_props.addLong("C_TRACE_PIPELINE_WIDTH", "8");
model_param_props.addLong("C_TRACE_BUFFER_CLOCK_DELAY", "12");
model_param_props.addLong("C_EMIO_GPIO_WIDTH", "64");
model_param_props.addLong("C_INCLUDE_ACP_TRANS_CHECK", "0");
model_param_props.addLong("C_USE_DEFAULT_ACP_USER_VAL", "0");
model_param_props.addLong("C_S_AXI_ACP_ARUSER_VAL", "31");
model_param_props.addLong("C_S_AXI_ACP_AWUSER_VAL", "31");
model_param_props.addLong("C_M_AXI_GP0_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP0_ENABLE_STATIC_REMAP", "0");
model_param_props.addLong("C_M_AXI_GP1_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP1_ENABLE_STATIC_REMAP", "0");
model_param_props.addLong("C_S_AXI_GP0_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_GP1_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_ACP_ID_WIDTH", "3");
model_param_props.addLong("C_S_AXI_HP0_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP0_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP1_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP1_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP2_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP2_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP3_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "1");
model_param_props.addLong("C_DQ_WIDTH", "32");
model_param_props.addLong("C_DQS_WIDTH", "4");
model_param_props.addLong("C_DM_WIDTH", "4");
model_param_props.addLong("C_MIO_PRIMITIVE", "54");
model_param_props.addLong("C_TRACE_INTERNAL_WIDTH", "2");
model_param_props.addLong("C_USE_AXI_NONSECURE", "0");
model_param_props.addLong("C_USE_M_AXI_GP0", "0");
model_param_props.addLong("C_USE_M_AXI_GP1", "0");
model_param_props.addLong("C_USE_S_AXI_GP0", "0");
model_param_props.addLong("C_USE_S_AXI_GP1", "0");
model_param_props.addLong("C_USE_S_AXI_HP0", "0");
model_param_props.addLong("C_USE_S_AXI_HP1", "0");
model_param_props.addLong("C_USE_S_AXI_HP2", "0");
model_param_props.addLong("C_USE_S_AXI_HP3", "0");
model_param_props.addLong("C_USE_S_AXI_ACP", "0");
model_param_props.addLong("C_GP0_EN_MODIFIABLE_TXN", "1");
model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE");
model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");
model_param_props.addString("C_PACKAGE_NAME", "clg400");
model_param_props.addString("COMPONENT_NAME", "design_1_processing_system7_0_0");
mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);
}
design_1_processing_system7_0_0_sc::~design_1_processing_system7_0_0_sc()
{
xsc::utils::xsc_sim_manager::clean();
delete mp_impl;
}

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#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
class processing_system7_v5_5_tlm;
class DllExport design_1_processing_system7_0_0_sc : public sc_core::sc_module
{
public:
design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
virtual ~design_1_processing_system7_0_0_sc();
// module socket-to-socket AXI TLM interfaces
// module socket-to-socket TLM interfaces
protected:
processing_system7_v5_5_tlm* mp_impl;
private:
design_1_processing_system7_0_0_sc(const design_1_processing_system7_0_0_sc&);
const design_1_processing_system7_0_0_sc& operator=(const design_1_processing_system7_0_0_sc&);
};
#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_

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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
//------------------------------------------------------------------------------------
// Filename: design_1_processing_system7_0_0_stub.sv
// Description: This HDL file is intended to be used with following simulators only:
//
// Vivado Simulator (XSim)
// Cadence Xcelium Simulator
//
//------------------------------------------------------------------------------------
`timescale 1ps/1ps
`ifdef XILINX_SIMULATOR
`ifndef XILINX_SIMULATOR_BITASBOOL
`define XILINX_SIMULATOR_BITASBOOL
typedef bit bit_as_bool;
`endif
(* SC_MODULE_EXPORT *)
module design_1_processing_system7_0_0 (
output bit_as_bool FCLK_CLK0,
output bit_as_bool FCLK_RESET0_N,
output bit [53 : 0] MIO,
output bit_as_bool DDR_CAS_n,
output bit_as_bool DDR_CKE,
output bit_as_bool DDR_Clk_n,
output bit_as_bool DDR_Clk,
output bit_as_bool DDR_CS_n,
output bit_as_bool DDR_DRSTB,
output bit_as_bool DDR_ODT,
output bit_as_bool DDR_RAS_n,
output bit_as_bool DDR_WEB,
output bit [2 : 0] DDR_BankAddr,
output bit [14 : 0] DDR_Addr,
output bit_as_bool DDR_VRN,
output bit_as_bool DDR_VRP,
output bit [3 : 0] DDR_DM,
output bit [31 : 0] DDR_DQ,
output bit [3 : 0] DDR_DQS_n,
output bit [3 : 0] DDR_DQS,
output bit_as_bool PS_SRSTB,
output bit_as_bool PS_CLK,
output bit_as_bool PS_PORB
);
endmodule
`endif
`ifdef XCELIUM
(* XMSC_MODULE_EXPORT *)
module design_1_processing_system7_0_0 (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
(* integer foreign = "SystemC";
*);
output wire FCLK_CLK0;
output wire FCLK_RESET0_N;
inout wire [53 : 0] MIO;
inout wire DDR_CAS_n;
inout wire DDR_CKE;
inout wire DDR_Clk_n;
inout wire DDR_Clk;
inout wire DDR_CS_n;
inout wire DDR_DRSTB;
inout wire DDR_ODT;
inout wire DDR_RAS_n;
inout wire DDR_WEB;
inout wire [2 : 0] DDR_BankAddr;
inout wire [14 : 0] DDR_Addr;
inout wire DDR_VRN;
inout wire DDR_VRP;
inout wire [3 : 0] DDR_DM;
inout wire [31 : 0] DDR_DQ;
inout wire [3 : 0] DDR_DQS_n;
inout wire [3 : 0] DDR_DQS;
inout wire PS_SRSTB;
inout wire PS_CLK;
inout wire PS_PORB;
endmodule
`endif

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
#ifndef _B_TRANSPORT_CONVERTER_H_
#define _B_TRANSPORT_CONVERTER_H_
#include <systemc>
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/simple_initiator_socket.h"
#include <utility>
#include <vector>
template<int IN_WIDTH, int OUT_WIDTH>
class b_transport_converter: public sc_core::sc_module
{
enum TLM_IF_TYPE
{
B_TRANSPORT = 0,
NB_TRANSPORT,
TRANSPORT_DBG,
DMI_IF,
INVALID_IF
};
typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
public:
SC_HAS_PROCESS(b_transport_converter);
b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
sc_module(name)
{
target_socket.register_b_transport(
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
initiator_socket.register_nb_transport_bw(
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
}
//simple tlm target/initiator socket...
tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
public:
void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
{
tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
switch(get_tlm_if_type(payload.get_address()))
{
case B_TRANSPORT:
initiator_socket->b_transport(payload, time);
break;
case NB_TRANSPORT:
initiator_socket->nb_transport_fw(payload, phase, time);
wait(resp_complete_event); //! Wait for the response to complete
break;
case TRANSPORT_DBG:
initiator_socket->transport_dbg(payload);
break;
case DMI_IF:
break;
default:
SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
}
}
tlm::tlm_sync_enum
nb_transport_bw(tlm::tlm_generic_payload& payload,
tlm::tlm_phase& phase, sc_core::sc_time& time)
{
if(phase == tlm::BEGIN_RESP) {
resp_complete_event.notify();
phase = tlm::END_RESP;
return tlm::TLM_UPDATED;
}
return tlm::TLM_ACCEPTED;
}
private:
TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
{
//check for b_transport addresses
for(auto& addr_range: m_b_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return B_TRANSPORT;
}
}
//check for nb_transport addresses
for(auto& addr_range: m_nb_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return NB_TRANSPORT;
}
}
//check for dbg_transport addresses
for(auto& addr_range: m_dbg_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return TRANSPORT_DBG;
}
}
//By default return NB_TRANSPORT
return NB_TRANSPORT;
}
//Start and End Address List for each of interfaces...
static addr_range_list m_b_transport_addr_list;
static addr_range_list m_nb_transport_addr_list;
static addr_range_list m_dbg_transport_addr_list;
//event to notify completion of transaction
sc_core::sc_event resp_complete_event;
};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
#endif /* _B_TRANSPORT_CONVERTER_H_ */

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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include"processing_system7_v5_5_tlm.h"
#include<string>
template <int IN_WIDTH, int OUT_WIDTH>
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::rptlm2xtlm_converter(sc_module_name name):sc_module(name)
,target_socket("target_socket")
,wr_socket("init_wr_socket",OUT_WIDTH)
,rd_socket("init_rd_socket",OUT_WIDTH)
,m_btrans_conv("b_transport_converter")
,xtlm_bridge("tlm2xtlmbridge")
{
target_socket.bind(m_btrans_conv.target_socket);
m_btrans_conv.initiator_socket.bind(xtlm_bridge.target_socket);
xtlm_bridge.rd_socket->bind(rd_socket);
xtlm_bridge.wr_socket->bind(wr_socket);
}
template <int IN_WIDTH, int OUT_WIDTH>
void rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*)) {
xtlm_bridge.registerUserExtensionHandlerCallback(callback);
}
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp)
{
if((xtlm_pay == NULL) || (gp == NULL))
return;
if((gp->get_command() == tlm::TLM_WRITE_COMMAND) && (xtlm_pay->get_awuser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_awuser_ptr();
unsigned int size = xtlm_pay->get_awuser_size();
*ptr = (unsigned char)val;
}
else if((gp->get_command() == tlm::TLM_READ_COMMAND) && (xtlm_pay->get_aruser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_aruser_ptr();
unsigned int size = xtlm_pay->get_aruser_size();
*ptr = (unsigned char)val;
}
}
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp)
{
if(gp == NULL)
return;
uint8_t val = 0;
if((gp->get_command() != tlm::TLM_WRITE_COMMAND) && (gp->get_command() != tlm::TLM_READ_COMMAND))
return;
//portion of master ID bits(master_id[5:0]) are derived from the AXI ID(AWID/ARID). (refere Zynq UltraScale+ TRM page.no:414,415)
//val = (*(uint8_t*)(xtlm_pay->get_axi_id())) && 0x3F;
genattr_extension* ext = new genattr_extension;
ext->set_master_id(val);
gp->set_extension(ext);
gp->set_streaming_width(gp->get_data_length());
if(gp->get_command() != tlm::TLM_WRITE_COMMAND)
{
gp->set_byte_enable_length(0);
gp->set_byte_enable_ptr(0);
}
}
processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent
,FCLK_CLK0("FCLK_CLK0")
,FCLK_RESET0_N("FCLK_RESET0_N")
,MIO("MIO")
,DDR_CAS_n("DDR_CAS_n")
,DDR_CKE("DDR_CKE")
,DDR_Clk_n("DDR_Clk_n")
,DDR_Clk("DDR_Clk")
,DDR_CS_n("DDR_CS_n")
,DDR_DRSTB("DDR_DRSTB")
,DDR_ODT("DDR_ODT")
,DDR_RAS_n("DDR_RAS_n")
,DDR_WEB("DDR_WEB")
,DDR_BankAddr("DDR_BankAddr")
,DDR_Addr("DDR_Addr")
,DDR_VRN("DDR_VRN")
,DDR_VRP("DDR_VRP")
,DDR_DM("DDR_DM")
,DDR_DQ("DDR_DQ")
,DDR_DQS_n("DDR_DQS_n")
,DDR_DQS("DDR_DQS")
,PS_SRSTB("PS_SRSTB")
,PS_CLK("PS_CLK")
,PS_PORB("PS_PORB")
,FCLK_CLK0_clk("FCLK_CLK0_clk", sc_time(20000.0,sc_core::SC_PS))//clock period in picoseconds = 1000000/freq(in MZ)
,prop(_prop)
{
//creating instances of xtlm slave sockets
//creating instances of xtlm master sockets
char* unix_path = getenv("COSIM_MACHINE_PATH");
char* tcpip_addr = getenv("COSIM_MACHINE_TCPIP_ADDRESS");
char* dir_path_to_test_machine;
bool unix_socket_en = false;
if (unix_path != nullptr) {
dir_path_to_test_machine = strdup(unix_path);
unix_socket_en = true;
}
if ((unix_socket_en == false) && (tcpip_addr != nullptr)) {
dir_path_to_test_machine = strdup(tcpip_addr);
} else if (unix_socket_en == false) {
printf(
"ERROR: Environment Variables Either COSIM_MACHINE_TCPIP_ADDRESS or COSIM_MACHINE_PATH is not specified.\n 1. Specify COSIM_MACHINE_PATH for Unix Socket Communication.\n 2. Specify COSIM_MACHINE_TCPIP_ADDRESS for TCP Socket Communication.\n");
exit(0);
}
std::string skt_name;
if (unix_socket_en) {
skt_name.append("unix:");
skt_name.append(dir_path_to_test_machine);
skt_name.append("//qemu-rport-_cosim@0");
} else {
skt_name.append(dir_path_to_test_machine);
}
const char* skt = skt_name.c_str();
m_zynq_tlm_model = new xilinx_zynq("xilinx_zynq",skt);
m_zynq_tlm_model->tie_off();
SC_METHOD(trigger_FCLK_CLK0_pin);
sensitive << FCLK_CLK0_clk;
dont_initialize();
m_zynq_tlm_model->rst(qemu_rst);
}
processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() {
//deleteing dynamically created objects
}
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void processing_system7_v5_5_tlm ::trigger_FCLK_CLK0_pin() {
FCLK_CLK0.write(FCLK_CLK0_clk.read());
}
//ps2pl_rst[0] output reset pin
void processing_system7_v5_5_tlm :: FCLK_RESET0_N_trigger() {
FCLK_RESET0_N.write(m_zynq_tlm_model->ps2pl_rst[0].read());
}
void processing_system7_v5_5_tlm ::start_of_simulation()
{
//temporary fix to drive the enabled reset pin
FCLK_RESET0_N.write(true);
qemu_rst.write(false);
}

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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif

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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}

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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/tlm_quantumkeeper.h"
#include "remote-port-tlm.h"
#include "remote-port-tlm-memory-master.h"
#include "remote-port-tlm-memory-slave.h"
#include "remote-port-tlm-wires.h"
class xilinx_zynq
: public remoteport_tlm
{
private:
remoteport_tlm_memory_master rp_m_axi_gp0;
remoteport_tlm_memory_master rp_m_axi_gp1;
remoteport_tlm_memory_slave rp_s_axi_gp0;
remoteport_tlm_memory_slave rp_s_axi_gp1;
remoteport_tlm_memory_slave rp_s_axi_hp0;
remoteport_tlm_memory_slave rp_s_axi_hp1;
remoteport_tlm_memory_slave rp_s_axi_hp2;
remoteport_tlm_memory_slave rp_s_axi_hp3;
remoteport_tlm_memory_slave rp_s_axi_acp;
remoteport_tlm_wires rp_wires_in;
remoteport_tlm_wires rp_wires_out;
remoteport_tlm_wires rp_irq_out;
public:
/*
* M_AXI_GP 0 - 1.
* These sockets represent the High speed PS to PL interfaces.
* These are AXI Slave ports on the PS side and AXI Master ports
* on the PL side.
*
* Used to transfer data from the PS to the PL.
*/
tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
/*
* S_AXI_GP0 - 1.
* These sockets represent the High speed IO Coherent PL to PS
* interfaces.
*
* HP0 - 3.
* These sockets represent the High performance dataflow PL to PS interfaces.
*
* ACP
* Accelerator Coherency Port, used to transfered coherent data to
* the PS via the Cortex-A9 subsystem.
*
* These are AXI Master ports on the PS side and AXI Slave ports
* on the PL side.
*
* Used to transfer data from the PL to the PS.
*/
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
/* PL (fabric) to PS interrupt signals. */
sc_vector<sc_signal<bool> > pl2ps_irq;
/* PS to PL Interrupt signals. */
sc_vector<sc_signal<bool> > ps2pl_irq;
/* FPGA out resets. */
sc_vector<sc_signal<bool> > ps2pl_rst;
xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync = NULL);
};

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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 6
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *)
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\
ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\
_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=0,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TX\
N=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg400"),
.C_GP0_EN_MODIFIABLE_TXN(1),
.C_GP1_EN_MODIFIABLE_TXN(1)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(),
.USB0_VBUS_PWRSELECT(),
.USB0_VBUS_PWRFAULT(1'B0),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule

409
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@ -0,0 +1,409 @@
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire

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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// aw_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_aw_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
output reg cmd_w_valid,
output wire cmd_w_check,
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
input wire cmd_w_ready,
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
input wire cmd_b_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Constants for size.
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
// Constants for length.
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
// Constants for cacheline address.
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Transaction properties.
wire access_is_incr;
wire access_is_wrap;
wire access_is_coherent;
wire access_optimized_size;
wire incr_addr_boundary;
wire incr_is_optimized;
wire wrap_is_optimized;
wire access_is_optimized;
// Command FIFO.
wire cmd_w_push;
reg cmd_full;
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
/////////////////////////////////////////////////////////////////////////////
// Transaction Decode:
//
// Detect if transaction is of correct typ, size and length to qualify as
// an optimized transaction that has to be checked for errors.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
// Transaction has to be Coherent.
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
( S_AXI_AWCACHE[1] == 1'b1 );
// Transaction cacheline boundary address.
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
// Transaction length & size.
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
// Transaction is optimized.
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
/////////////////////////////////////////////////////////////////////////////
// Command FIFO:
//
// Since supported write interleaving is only 1, it is safe to use only a
// simple SRL based FIFO as a command queue.
//
/////////////////////////////////////////////////////////////////////////////
// Determine when transaction infromation is pushed to the FIFO.
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_w_push & ~cmd_w_ready ) begin
addr_ptr <= addr_ptr + 1;
end else if ( ~cmd_w_push & cmd_w_ready ) begin
addr_ptr <= addr_ptr - 1;
end
end
end
// Total number of buffered commands.
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_full <= 1'b0;
cmd_w_valid <= 1'b0;
end else begin
if ( cmd_w_push & ~cmd_w_ready ) begin
cmd_w_valid <= 1'b1;
end else if ( ~cmd_w_push & cmd_w_ready ) begin
cmd_w_valid <= ( addr_ptr != 0 );
end
if ( cmd_w_push & ~cmd_b_ready ) begin
// Going to full.
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
end else if ( ~cmd_w_push & cmd_b_ready ) begin
// Pop in middle of queue doesn't affect full status.
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_w_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
end
end
// Get current transaction info.
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
// Return ready with push back.
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
/////////////////////////////////////////////////////////////////////////////
// Address Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWUSER = S_AXI_AWUSER;
endmodule

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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule

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// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: trace_buffer.v
// Description: Trace port buffer
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7
// |
// --trace_buffer
//-----------------------------------------------------------------------------
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule

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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule

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// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic Functions used by AXI Infrastructure Modules
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Global Parameters:
//
// Functions:
//
// Tasks:
//--------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// BEGIN Global Parameters
///////////////////////////////////////////////////////////////////////////////
localparam G_AXI_AWADDR_INDEX = 0;
localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
localparam G_AXI_AWPROT_WIDTH = 3;
localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
localparam G_AXI_ARADDR_INDEX = 0;
localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
localparam G_AXI_ARPROT_WIDTH = 3;
localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
// Write channel widths
localparam G_AXI_WDATA_INDEX = 0;
localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH;
localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8;
localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
// Write Response channel Widths
localparam G_AXI_BRESP_INDEX = 0;
localparam G_AXI_BRESP_WIDTH = 2;
localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
// Read channel widths
localparam G_AXI_RDATA_INDEX = 0;
localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH;
localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
localparam G_AXI_RRESP_WIDTH = 2;
localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;

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// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_apis.v
*
* Date : 2012-11
*
* Description : Set of Zynq VIP APIs that are used for writing tests.
*
*****************************************************************************/
/* API for setting the STOP_ON_ERROR*/
task automatic set_stop_on_error;
input LEVEL;
begin
$display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
STOP_ON_ERROR = LEVEL;
// M_AXI_GP0.master.set_stop_on_error(LEVEL);
// M_AXI_GP1.master.set_stop_on_error(LEVEL);
// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
M_AXI_GP0.STOP_ON_ERROR = LEVEL;
M_AXI_GP1.STOP_ON_ERROR = LEVEL;
S_AXI_GP0.STOP_ON_ERROR = LEVEL;
S_AXI_GP1.STOP_ON_ERROR = LEVEL;
S_AXI_HP0.STOP_ON_ERROR = LEVEL;
S_AXI_HP1.STOP_ON_ERROR = LEVEL;
S_AXI_HP2.STOP_ON_ERROR = LEVEL;
S_AXI_HP3.STOP_ON_ERROR = LEVEL;
S_AXI_ACP.STOP_ON_ERROR = LEVEL;
end
endtask
/* API for setting the verbosity for channel level info*/
task automatic set_channel_level_info;
input [1023:0] name;
input LEVEL;
begin
$display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
case(name)
// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
"ALL" : begin
// M_AXI_GP0.master.set_channel_level_info(LEVEL);
// M_AXI_GP1.master.set_channel_level_info(LEVEL);
// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
end
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
endcase
end
endtask
/* API for setting the verbosity for function level info*/
task automatic set_function_level_info;
input [1023:0] name;
input LEVEL;
begin
$display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
case(name)
// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
"ALL" : begin
// M_AXI_GP0.master.set_function_level_info(LEVEL);
// M_AXI_GP1.master.set_function_level_info(LEVEL);
// S_AXI_GP0.slave.set_function_level_info(LEVEL);
// S_AXI_GP1.slave.set_function_level_info(LEVEL);
// S_AXI_HP0.slave.set_function_level_info(LEVEL);
// S_AXI_HP1.slave.set_function_level_info(LEVEL);
// S_AXI_HP2.slave.set_function_level_info(LEVEL);
// S_AXI_HP3.slave.set_function_level_info(LEVEL);
// S_AXI_ACP.slave.set_function_level_info(LEVEL);
end
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
endcase
end
endtask
/* API for setting the Message verbosity */
task automatic set_debug_level_info;
input LEVEL;
begin
$display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
DEBUG_INFO = LEVEL;
M_AXI_GP0.DEBUG_INFO = LEVEL;
M_AXI_GP1.DEBUG_INFO = LEVEL;
S_AXI_GP0.DEBUG_INFO = LEVEL;
S_AXI_GP1.DEBUG_INFO = LEVEL;
S_AXI_HP0.DEBUG_INFO = LEVEL;
S_AXI_HP1.DEBUG_INFO = LEVEL;
S_AXI_HP2.DEBUG_INFO = LEVEL;
S_AXI_HP3.DEBUG_INFO = LEVEL;
S_AXI_ACP.DEBUG_INFO = LEVEL;
ddrc.ddr.DEBUG_INFO = LEVEL;
ddrc.ddr_write_ports.DEBUG_INFO = LEVEL;
ddrc.ddr_read_ports.DEBUG_INFO = LEVEL;
ocmc.ocm_write_ports.DEBUG_INFO = LEVEL;
ocmc.ocm_read_ports.DEBUG_INFO = LEVEL;
icm.ssw.ocm_wr_hp.DEBUG_INFO = LEVEL;
icm.ssw.ocm_rd_hp.DEBUG_INFO = LEVEL;
icm.ssw.ddr_hp01.ddr_hp_wr.DEBUG_INFO = LEVEL;
icm.ssw.ddr_hp01.ddr_hp_rd.DEBUG_INFO = LEVEL;
icm.ssw.ddr_hp23.ddr_hp_wr.DEBUG_INFO = LEVEL;
icm.ssw.ddr_hp23.ddr_hp_rd.DEBUG_INFO = LEVEL;
icm.fmsw.ocm_gp_wr.DEBUG_INFO = LEVEL;
icm.fmsw.ddr_gp_wr.DEBUG_INFO = LEVEL;
icm.fmsw.ocm_gp_rd.DEBUG_INFO = LEVEL;
icm.fmsw.ddr_gp_rd.DEBUG_INFO = LEVEL;
icm.fmsw.reg_gp_rd.DEBUG_INFO = LEVEL;
icm.osw_wr.DEBUG_INFO = LEVEL;
icm.osw_rd.DEBUG_INFO = LEVEL;
regc.reg_read_ports.DEBUG_INFO = LEVEL;
end
endtask
/* API for setting ARQos Values */
task automatic set_arqos;
input [1023:0] name;
input [axi_qos_width-1:0] value;
begin
$display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
case(name)
"S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
"S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
"S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
"S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
"S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
"S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
"S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
endcase
end
endtask
/* API for setting AWQos Values */
task automatic set_awqos;
input [1023:0] name;
input [axi_qos_width-1:0] value;
begin
$display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
case(name)
"S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
"S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
"S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
"S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
"S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
"S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
"S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
endcase
end
endtask
/* API for soft reset control */
task automatic fpga_soft_reset;
input[data_width-1:0] reset_ctrl;
begin
if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
gen_rst.fpga_soft_reset(reset_ctrl);
end
endtask
/* API for por and strb reset control */
// task automatic por_srstb_reset;
// input por_reset_ctrl;
// begin
// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
// // gen_rst.por_srstb_reset(por_reset_ctrl);
// gen_rst.por_srstb_reset(por_reset_ctrl);
//
// end
// endtask
/* API for pre-loading memories from (DDR/OCM model) */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
reg [1:0] mem_type;
integer succ;
begin
mem_type = decode_address(start_addr);
succ = $fopen(file_name,"r");
if(succ == 0) begin
$display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
if(STOP_ON_ERROR) $stop;
end
else if(check_addr_aligned(start_addr)) begin
case(mem_type)
OCM_MEM : begin
if (!C_HIGH_OCM_EN)
ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
else
ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
end
DDR_MEM : begin
ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
end
default : begin
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR)
$stop;
end
end
endtask
/* API for pre-loading memories (DDR/OCM) */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
reg [1:0] mem_type;
begin
mem_type = decode_address(start_addr);
if(check_addr_aligned(start_addr)) begin
case(mem_type)
OCM_MEM : begin
if (!C_HIGH_OCM_EN)
ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
else
ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
end
DDR_MEM : begin
ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
end
default : begin
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
end
endtask
/* API for backdoor write to memories (DDR/OCM) */
task automatic write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [1:0] mem_type;
integer succ;
begin
mem_type = decode_address(start_addr);
if(check_addr_aligned(start_addr)) begin
case(mem_type)
OCM_MEM : begin
if (!C_HIGH_OCM_EN)
ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
else
ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
end
DDR_MEM : begin
ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
end
default : begin
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR)
$stop;
end
end
endtask
/* read_memory */
task automatic read_mem;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
output[max_burst_bits-1 :0] data;
reg [1:0] mem_type;
integer succ;
begin
mem_type = decode_address(start_addr);
if(check_addr_aligned(start_addr)) begin
case(mem_type)
OCM_MEM : begin
if (!C_HIGH_OCM_EN)
ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
else
ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
end
DDR_MEM : begin
ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
end
default : begin
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR)
$stop;
end
end
endtask
/* API for backdoor read to memories (DDR/OCM) */
task automatic peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
reg [1:0] mem_type;
integer succ;
begin
mem_type = decode_address(start_addr);
if(check_addr_aligned(start_addr)) begin
case(mem_type)
OCM_MEM : begin
if (!C_HIGH_OCM_EN)
ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
else
ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
end
DDR_MEM : begin
ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
if(DEBUG_INFO)
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
end
default : begin
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR)
$stop;
end
end
endtask
/* API to read interrupt status */
task automatic read_interrupt;
output[irq_width-1:0] irq_status;
begin
irq_status = IRQ_F2P;
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
end
endtask
/* API to wait on interrup */
task automatic wait_interrupt;
input [3:0] irq;
output[irq_width-1:0] irq_status;
begin
if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
case(irq)
0 : wait(IRQ_F2P[0] === 1'b1);
1 : wait(IRQ_F2P[1] === 1'b1);
2 : wait(IRQ_F2P[2] === 1'b1);
3 : wait(IRQ_F2P[3] === 1'b1);
4 : wait(IRQ_F2P[4] === 1'b1);
5 : wait(IRQ_F2P[5] === 1'b1);
6 : wait(IRQ_F2P[6] === 1'b1);
7 : wait(IRQ_F2P[7] === 1'b1);
8 : wait(IRQ_F2P[8] === 1'b1);
9 : wait(IRQ_F2P[9] === 1'b1);
10: wait(IRQ_F2P[10] === 1'b1);
11: wait(IRQ_F2P[11] === 1'b1);
12: wait(IRQ_F2P[12] === 1'b1);
13: wait(IRQ_F2P[13] === 1'b1);
14: wait(IRQ_F2P[14] === 1'b1);
15: wait(IRQ_F2P[15] === 1'b1);
default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
endcase
if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
irq_status = IRQ_F2P;
end
endtask
/* API to wait for a certain match pattern*/
task automatic wait_mem_update;
input[addr_width-1:0] address;
input[data_width-1:0] data_in;
output[data_width-1:0] data_out;
reg[data_width-1:0] datao;
begin
if(mem_update_key) begin
mem_update_key = 0;
if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
if(check_addr_aligned(address)) begin
ddrc.ddr.wait_mem_update(address, datao);
if(datao != data_in)begin
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
$stop;
end else
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
data_out = datao;
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
if(STOP_ON_ERROR) $stop;
end
mem_update_key = 1;
end else
$display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
end
endtask
/* API to initiate a WRITE transaction on one of the AXI-Master ports*/
task automatic write_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] wr_size;
output [axi_rsp_width-1:0] response;
integer succ;
begin
succ = $fopen(file_name,"r");
if(succ == 0) begin
$display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
if(STOP_ON_ERROR) $stop;
end
else if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(check_addr_aligned(start_addr)) begin
$fclose(succ);
// case(start_addr[31:30])
if (start_addr[31:30] === 2'b01) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
end else if(start_addr[31:30] === 2'b10) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
end else begin
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
end
// endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
end
endtask
/* API to initiate a READ transaction on one of the AXI-Master ports*/
task automatic read_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] rd_size;
output [axi_rsp_width-1:0] response;
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
if(STOP_ON_ERROR) $stop;
end else if(check_addr_aligned(start_addr)) begin
// case(start_addr[31:30])
if (start_addr[31:30] === 2'b01) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
end else if(start_addr[31:30] === 2'b10) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
// end
// default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
// endcase
end else begin
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end
end
end
endtask
/* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
task automatic write_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] wr_size;
input [(max_transfer_bytes*8)-1:0] w_data;
output [axi_rsp_width-1:0] response;
reg[511:0] rsp;
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(wr_size > max_transfer_bytes) begin
$display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(start_addr[31:30] === GP_M0) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else if(start_addr[31:30] === GP_M1) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
end
endtask
/* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
task automatic read_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] rd_size;
output[(max_transfer_bytes*8)-1:0] rd_data;
output [axi_rsp_width-1:0] response;
reg[511:0] rsp;
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(rd_size > max_transfer_bytes) begin
$display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(start_addr[31:30] === GP_M0) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else if(start_addr[31:30] === GP_M1) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
end
endtask
/* Hooks to call to VIP APIs */
task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
reg[511:0] rsp;
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(start_addr[31:30] === 2'b01) begin
// end else if(start_addr[31:30] === GP_M0) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else if(start_addr[31:30] === 2'b10) begin
// end else if(start_addr[31:30] === GP_M1) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
end
endtask
task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
reg[511:0] rsp; /// string for response
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(start_addr[31:30] === 2'b01) begin
// end else if(start_addr[31:30] === GP_M0) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else if(start_addr[31:30] === 2'b10) begin
// end else if(start_addr[31:30] === GP_M1) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
end
endtask
task automatic read_burst;
input [addr_width-1:0] start_addr;
input [axi_len_width-1:0] len;
input [axi_size_width-1:0] siz;
input [axi_brst_type_width-1:0] burst;
input [axi_lock_width-1:0] lck;
input [axi_cache_width-1:0] cache;
input [axi_prot_width-1:0] prot;
output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
output [(axi_rsp_width*axi_burst_len)-1:0] response;
reg[511:0] rsp;
begin
if(!check_master_address(start_addr)) begin
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
if(STOP_ON_ERROR) $stop;
end else if(start_addr[31:30] === 2'b01) begin
// end else if(start_addr[31:30] === GP_M0) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else if(start_addr[31:30] === 2'b10) begin
// end else if(start_addr[31:30] === GP_M1) begin
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
rsp = get_resp(response);
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
end
endtask
task automatic wait_reg_update;
input [addr_width-1:0] addr;
input [data_width-1:0] data_i;
input [data_width-1:0] mask_i;
input [int_width-1:0] time_interval;
input [int_width-1:0] time_out;
output [data_width-1:0] data_o;
reg upd_done0;
reg upd_done1;
begin
if(!check_master_address(addr)) begin
$display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
if(STOP_ON_ERROR) $stop;
end else if(addr[31:30] === 2'b01) begin
// end else if(addr[31:30] === GP_M0) begin
if(reg_update_key_0) begin
reg_update_key_0 = 0;
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
if(DEBUG_INFO && upd_done0)
$display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
reg_update_key_0 = 1;
end else
$display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
end else if(addr[31:30] === 2'b10) begin
// end else if(addr[31:30] === GP_M1) begin
if(reg_update_key_1) begin
reg_update_key_1 = 0;
if(DEBUG_INFO)
$display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
if(DEBUG_INFO && upd_done1)
$display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
reg_update_key_1 = 1;
end else
$display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
end else
$display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
end
endtask
/* API to read register map */
task read_register_map;
input [addr_width-1:0] start_addr;
input [max_regs_width:0] no_of_registers;
output[max_burst_bits-1 :0] data;
reg [max_regs_width:0] no_of_regs;
begin
no_of_regs = no_of_registers;
if(no_of_registers > 32) begin
$display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
no_of_regs = 32;
end
if(check_addr_aligned(start_addr)) begin
if(decode_address(start_addr) == REG_MEM) begin
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
end else begin
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
end
end else begin
data = 0;
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
end
end
endtask
/* API to read single register */
task read_register;
input [addr_width-1:0] addr;
output[data_width-1:0] data;
begin
if(check_addr_aligned(addr)) begin
if(decode_address(addr) == REG_MEM) begin
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
regc.regm.get_data(addr >> 2, data);
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
end else begin
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
end
end else begin
data = 0;
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
end
end
endtask
/* API to set the AXI-Slave profile*/
task automatic set_slave_profile;
input[1023:0] name;
input[1:0] latency ;
begin
if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
case(name)
"S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
"S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
"S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
"S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
"S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
"S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
"S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
"ALL" : begin
S_AXI_GP0.set_latency_type(latency);
S_AXI_GP1.set_latency_type(latency);
S_AXI_HP0.set_latency_type(latency);
S_AXI_HP1.set_latency_type(latency);
S_AXI_HP2.set_latency_type(latency);
S_AXI_HP3.set_latency_type(latency);
S_AXI_ACP.set_latency_type(latency);
end
endcase
end
endtask
/*------------------------------ LOCAL APIs ------------------------------------------------ */
/* local API for address decoding*/
function automatic [1:0] decode_address;
input [addr_width-1:0] address;
begin
if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
decode_address = OCM_MEM; /// OCM
else if(address >= ddr_start_addr && address <= ddr_end_addr)
decode_address = DDR_MEM; /// DDR
else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
decode_address = OCM_MEM; /// OCM
else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
decode_address = REG_MEM; /// Register Map
else
decode_address = INVALID_MEM_TYPE; /// ERROR in Address
end
endfunction
/* local API for checking address is 32-bit (4-byte) aligned */
function automatic check_addr_aligned;
input [addr_width-1:0] address;
begin
if((address%4) !=0 ) begin //
check_addr_aligned = 0; ///not_aligned
end else
check_addr_aligned = 1;
end
endfunction
/* local API to check address for GP Masters */
function check_master_address;
input [addr_width-1:0] address;
begin
if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
check_master_address = 1'b1;
else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
check_master_address = 1'b1;
else
check_master_address = 1'b0; /// ERROR in Address
end
endfunction
/* Response decode */
function automatic [511:0] get_resp;
input[axi_rsp_width-1:0] response;
begin
case(response)
2'b00 : get_resp = "OKAY";
2'b01 : get_resp = "EXOKAY";
2'b10 : get_resp = "SLVERR";
2'b11 : get_resp = "DECERR";
endcase
end
endfunction

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_axi_acp.v
*
* Date : 2012-11
*
* Description : Connections for ACP port
*
*****************************************************************************/
/* AXI Slave ACP */
processing_system7_vip_v1_0_15_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
axi_acp_name, // name
axi_acp_data_width, // data width
addr_width, /// address width
axi_acp_id_width, // ID width
C_S_AXI_ACP_BASEADDR, // slave base address
C_S_AXI_ACP_HIGHADDR,// slave size
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
axi_slv_excl_support, // Exclusive access support
axi_acp_wr_outstanding,
axi_acp_rd_outstanding)
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
.S_ACLK (S_AXI_ACP_ACLK),
// Write Address Channel
.S_AWID (S_AXI_ACP_AWID),
.S_AWADDR (S_AXI_ACP_AWADDR),
.S_AWLEN (S_AXI_ACP_AWLEN),
.S_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AWBURST (S_AXI_ACP_AWBURST),
.S_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AWPROT (S_AXI_ACP_AWPROT),
.S_AWVALID (S_AXI_ACP_AWVALID),
.S_AWREADY (S_AXI_ACP_AWREADY),
// Write Data Channel Signals.
.S_WID (S_AXI_ACP_WID),
.S_WDATA (S_AXI_ACP_WDATA),
.S_WSTRB (S_AXI_ACP_WSTRB),
.S_WLAST (S_AXI_ACP_WLAST),
.S_WVALID (S_AXI_ACP_WVALID),
.S_WREADY (S_AXI_ACP_WREADY),
// Write Response Channel Signals.
.S_BID (S_AXI_ACP_BID),
.S_BRESP (S_AXI_ACP_BRESP),
.S_BVALID (S_AXI_ACP_BVALID),
.S_BREADY (S_AXI_ACP_BREADY),
// Read Address Channel Signals.
.S_ARID (S_AXI_ACP_ARID),
.S_ARADDR (S_AXI_ACP_ARADDR),
.S_ARLEN (S_AXI_ACP_ARLEN),
.S_ARSIZE (S_AXI_ACP_ARSIZE),
.S_ARBURST (S_AXI_ACP_ARBURST),
.S_ARLOCK (S_AXI_ACP_ARLOCK),
.S_ARCACHE (S_AXI_ACP_ARCACHE),
.S_ARPROT (S_AXI_ACP_ARPROT),
.S_ARVALID (S_AXI_ACP_ARVALID),
.S_ARREADY (S_AXI_ACP_ARREADY),
// Read Data Channel Signals.
.S_RID (S_AXI_ACP_RID),
.S_RDATA (S_AXI_ACP_RDATA),
.S_RRESP (S_AXI_ACP_RRESP),
.S_RLAST (S_AXI_ACP_RLAST),
.S_RVALID (S_AXI_ACP_RVALID),
.S_RREADY (S_AXI_ACP_RREADY),
// Side band signals
.S_AWQOS (S_AXI_ACP_AWQOS),
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
.SW_CLK (net_sw_clk),
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
.WR_DATA (net_wr_data_acp),
.WR_DATA_STRB (net_wr_strb_acp),
.WR_ADDR (net_wr_addr_acp),
.WR_BYTES (net_wr_bytes_acp),
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
.WR_QOS (net_wr_qos_acp),
.RD_REQ_DDR (ddr_rd_req_port0),
.RD_REQ_OCM (ocm_rd_req_port0),
.RD_REQ_REG (reg_rd_req_port0),
.RD_ADDR (net_rd_addr_acp),
.RD_DATA_DDR (ddr_rd_data_port0),
.RD_DATA_OCM (ocm_rd_data_port0),
.RD_DATA_REG (reg_rd_data_port0),
.RD_BYTES (net_rd_bytes_acp),
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
.RD_DATA_VALID_REG (reg_rd_dv_port0),
.RD_QOS (net_rd_qos_acp)
);

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_axi_gp.v
*
* Date : 2012-11
*
* Description : Connections for AXI GP ports
*
*****************************************************************************/
/* IDs for Masters
// l2m1 (CPU000)
12'b11_000_000_00_00
12'b11_010_000_00_00
12'b11_011_000_00_00
12'b11_100_000_00_00
12'b11_101_000_00_00
12'b11_110_000_00_00
12'b11_111_000_00_00
// l2m1 (CPU001)
12'b11_000_001_00_00
12'b11_010_001_00_00
12'b11_011_001_00_00
12'b11_100_001_00_00
12'b11_101_001_00_00
12'b11_110_001_00_00
12'b11_111_001_00_00
*/
/* AXI -Master GP0 */
processing_system7_vip_v1_0_15_axi_master #(C_USE_M_AXI_GP0, // enable
axi_mgp0_name,// name
axi_mgp_data_width, /// Data Width
addr_width, /// Address width
axi_mgp_id_width, //// ID Width
axi_mgp_outstanding, //// Outstanding transactions
axi_mst_excl_support, // EXCL Access Support
axi_mgp_wr_id, //WR_ID
axi_mgp_rd_id) //RD_ID
M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
.M_ACLK (M_AXI_GP0_ACLK),
// Write Address Channel
.M_AWID (M_AXI_GP0_AWID_FULL),
.M_AWADDR (M_AXI_GP0_AWADDR),
.M_AWLEN (M_AXI_GP0_AWLEN),
.M_AWSIZE (M_AXI_GP0_AWSIZE),
.M_AWBURST (M_AXI_GP0_AWBURST),
.M_AWLOCK (M_AXI_GP0_AWLOCK),
.M_AWCACHE (M_AXI_GP0_AWCACHE),
.M_AWPROT (M_AXI_GP0_AWPROT),
.M_AWVALID (M_AXI_GP0_AWVALID),
.M_AWREADY (M_AXI_GP0_AWREADY),
// Write Data Channel Signals.
.M_WID (M_AXI_GP0_WID_FULL),
.M_WDATA (M_AXI_GP0_WDATA),
.M_WSTRB (M_AXI_GP0_WSTRB),
.M_WLAST (M_AXI_GP0_WLAST),
.M_WVALID (M_AXI_GP0_WVALID),
.M_WREADY (M_AXI_GP0_WREADY),
// Write Response Channel Signals.
.M_BID (M_AXI_GP0_BID_FULL),
.M_BRESP (M_AXI_GP0_BRESP),
.M_BVALID (M_AXI_GP0_BVALID),
.M_BREADY (M_AXI_GP0_BREADY),
// Read Address Channel Signals.
.M_ARID (M_AXI_GP0_ARID_FULL),
.M_ARADDR (M_AXI_GP0_ARADDR),
.M_ARLEN (M_AXI_GP0_ARLEN),
.M_ARSIZE (M_AXI_GP0_ARSIZE),
.M_ARBURST (M_AXI_GP0_ARBURST),
.M_ARLOCK (M_AXI_GP0_ARLOCK),
.M_ARCACHE (M_AXI_GP0_ARCACHE),
.M_ARPROT (M_AXI_GP0_ARPROT),
.M_ARVALID (M_AXI_GP0_ARVALID),
.M_ARREADY (M_AXI_GP0_ARREADY),
// Read Data Channel Signals.
.M_RID (M_AXI_GP0_RID_FULL),
.M_RDATA (M_AXI_GP0_RDATA),
.M_RRESP (M_AXI_GP0_RRESP),
.M_RLAST (M_AXI_GP0_RLAST),
.M_RVALID (M_AXI_GP0_RVALID),
.M_RREADY (M_AXI_GP0_RREADY),
// Side band signals
.M_AWQOS (M_AXI_GP0_AWQOS),
.M_ARQOS (M_AXI_GP0_ARQOS)
);
/* AXI Master GP1 */
processing_system7_vip_v1_0_15_axi_master #(C_USE_M_AXI_GP1, // enable
axi_mgp1_name,// name
axi_mgp_data_width, /// Data Width
addr_width, /// Address width
axi_mgp_id_width, //// ID Width
axi_mgp_outstanding, //// Outstanding transactions
axi_mst_excl_support, // EXCL Access Support
axi_mgp_wr_id, //WR_ID
axi_mgp_rd_id) //RD_ID
M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
.M_ACLK (M_AXI_GP1_ACLK),
// Write Address Channel
.M_AWID (M_AXI_GP1_AWID_FULL),
.M_AWADDR (M_AXI_GP1_AWADDR),
.M_AWLEN (M_AXI_GP1_AWLEN),
.M_AWSIZE (M_AXI_GP1_AWSIZE),
.M_AWBURST (M_AXI_GP1_AWBURST),
.M_AWLOCK (M_AXI_GP1_AWLOCK),
.M_AWCACHE (M_AXI_GP1_AWCACHE),
.M_AWPROT (M_AXI_GP1_AWPROT),
.M_AWVALID (M_AXI_GP1_AWVALID),
.M_AWREADY (M_AXI_GP1_AWREADY),
// Write Data Channel Signals.
.M_WID (M_AXI_GP1_WID_FULL),
.M_WDATA (M_AXI_GP1_WDATA),
.M_WSTRB (M_AXI_GP1_WSTRB),
.M_WLAST (M_AXI_GP1_WLAST),
.M_WVALID (M_AXI_GP1_WVALID),
.M_WREADY (M_AXI_GP1_WREADY),
// Write Response Channel Signals.
.M_BID (M_AXI_GP1_BID_FULL),
.M_BRESP (M_AXI_GP1_BRESP),
.M_BVALID (M_AXI_GP1_BVALID),
.M_BREADY (M_AXI_GP1_BREADY),
// Read Address Channel Signals.
.M_ARID (M_AXI_GP1_ARID_FULL),
.M_ARADDR (M_AXI_GP1_ARADDR),
.M_ARLEN (M_AXI_GP1_ARLEN),
.M_ARSIZE (M_AXI_GP1_ARSIZE),
.M_ARBURST (M_AXI_GP1_ARBURST),
.M_ARLOCK (M_AXI_GP1_ARLOCK),
.M_ARCACHE (M_AXI_GP1_ARCACHE),
.M_ARPROT (M_AXI_GP1_ARPROT),
.M_ARVALID (M_AXI_GP1_ARVALID),
.M_ARREADY (M_AXI_GP1_ARREADY),
// Read Data Channel Signals.
.M_RID (M_AXI_GP1_RID_FULL),
.M_RDATA (M_AXI_GP1_RDATA),
.M_RRESP (M_AXI_GP1_RRESP),
.M_RLAST (M_AXI_GP1_RLAST),
.M_RVALID (M_AXI_GP1_RVALID),
.M_RREADY (M_AXI_GP1_RREADY),
// Side band signals
.M_AWQOS (M_AXI_GP1_AWQOS),
.M_ARQOS (M_AXI_GP1_ARQOS)
);
/* AXI Slave GP0 */
processing_system7_vip_v1_0_15_axi_slave #(C_USE_S_AXI_GP0, /// enable
axi_sgp0_name, //name
axi_sgp_data_width, /// data width
addr_width, /// address width
axi_sgp_id_width, /// ID width
C_S_AXI_GP0_BASEADDR,//// base address
C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
axi_sgp_outstanding, // outstanding transactions
axi_slv_excl_support, // exclusive access not supported
axi_sgp_wr_outstanding,
axi_sgp_rd_outstanding)
S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
.S_ACLK (S_AXI_GP0_ACLK),
// Write Address Channel
.S_AWID (S_AXI_GP0_AWID),
.S_AWADDR (S_AXI_GP0_AWADDR),
.S_AWLEN (S_AXI_GP0_AWLEN),
.S_AWSIZE (S_AXI_GP0_AWSIZE),
.S_AWBURST (S_AXI_GP0_AWBURST),
.S_AWLOCK (S_AXI_GP0_AWLOCK),
.S_AWCACHE (S_AXI_GP0_AWCACHE),
.S_AWPROT (S_AXI_GP0_AWPROT),
.S_AWVALID (S_AXI_GP0_AWVALID),
.S_AWREADY (S_AXI_GP0_AWREADY),
// Write Data Channel Signals.
.S_WID (S_AXI_GP0_WID),
.S_WDATA (S_AXI_GP0_WDATA),
.S_WSTRB (S_AXI_GP0_WSTRB),
.S_WLAST (S_AXI_GP0_WLAST),
.S_WVALID (S_AXI_GP0_WVALID),
.S_WREADY (S_AXI_GP0_WREADY),
// Write Response Channel Signals.
.S_BID (S_AXI_GP0_BID),
.S_BRESP (S_AXI_GP0_BRESP),
.S_BVALID (S_AXI_GP0_BVALID),
.S_BREADY (S_AXI_GP0_BREADY),
// Read Address Channel Signals.
.S_ARID (S_AXI_GP0_ARID),
.S_ARADDR (S_AXI_GP0_ARADDR),
.S_ARLEN (S_AXI_GP0_ARLEN),
.S_ARSIZE (S_AXI_GP0_ARSIZE),
.S_ARBURST (S_AXI_GP0_ARBURST),
.S_ARLOCK (S_AXI_GP0_ARLOCK),
.S_ARCACHE (S_AXI_GP0_ARCACHE),
.S_ARPROT (S_AXI_GP0_ARPROT),
.S_ARVALID (S_AXI_GP0_ARVALID),
.S_ARREADY (S_AXI_GP0_ARREADY),
// Read Data Channel Signals.
.S_RID (S_AXI_GP0_RID),
.S_RDATA (S_AXI_GP0_RDATA),
.S_RRESP (S_AXI_GP0_RRESP),
.S_RLAST (S_AXI_GP0_RLAST),
.S_RVALID (S_AXI_GP0_RVALID),
.S_RREADY (S_AXI_GP0_RREADY),
// Side band signals
.S_AWQOS (S_AXI_GP0_AWQOS),
.S_ARQOS (S_AXI_GP0_ARQOS),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
.WR_DATA (net_wr_data_gp0),
.WR_DATA_STRB (net_wr_strb_gp0),
.WR_ADDR (net_wr_addr_gp0),
.WR_BYTES (net_wr_bytes_gp0),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
.WR_QOS (net_wr_qos_gp0),
.RD_REQ_DDR (net_rd_req_ddr_gp0),
.RD_REQ_OCM (net_rd_req_ocm_gp0),
.RD_REQ_REG (net_rd_req_reg_gp0),
.RD_ADDR (net_rd_addr_gp0),
.RD_DATA_DDR (net_rd_data_ddr_gp0),
.RD_DATA_OCM (net_rd_data_ocm_gp0),
.RD_DATA_REG (net_rd_data_reg_gp0),
.RD_BYTES (net_rd_bytes_gp0),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
.RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
.RD_QOS (net_rd_qos_gp0)
);
/* AXI Slave GP1 */
processing_system7_vip_v1_0_15_axi_slave #(C_USE_S_AXI_GP1, /// enable
axi_sgp1_name, //name
axi_sgp_data_width, /// data width
addr_width, /// address width
axi_sgp_id_width, /// ID width
C_S_AXI_GP1_BASEADDR,//// base address
C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
axi_sgp_outstanding, // outstanding transactions
axi_slv_excl_support, // exclusive access
axi_sgp_wr_outstanding,
axi_sgp_rd_outstanding)
S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
.S_ACLK (S_AXI_GP1_ACLK),
// Write Address Channel
.S_AWID (S_AXI_GP1_AWID),
.S_AWADDR (S_AXI_GP1_AWADDR),
.S_AWLEN (S_AXI_GP1_AWLEN),
.S_AWSIZE (S_AXI_GP1_AWSIZE),
.S_AWBURST (S_AXI_GP1_AWBURST),
.S_AWLOCK (S_AXI_GP1_AWLOCK),
.S_AWCACHE (S_AXI_GP1_AWCACHE),
.S_AWPROT (S_AXI_GP1_AWPROT),
.S_AWVALID (S_AXI_GP1_AWVALID),
.S_AWREADY (S_AXI_GP1_AWREADY),
// Write Data Channel Signals.
.S_WID (S_AXI_GP1_WID),
.S_WDATA (S_AXI_GP1_WDATA),
.S_WSTRB (S_AXI_GP1_WSTRB),
.S_WLAST (S_AXI_GP1_WLAST),
.S_WVALID (S_AXI_GP1_WVALID),
.S_WREADY (S_AXI_GP1_WREADY),
// Write Response Channel Signals.
.S_BID (S_AXI_GP1_BID),
.S_BRESP (S_AXI_GP1_BRESP),
.S_BVALID (S_AXI_GP1_BVALID),
.S_BREADY (S_AXI_GP1_BREADY),
// Read Address Channel Signals.
.S_ARID (S_AXI_GP1_ARID),
.S_ARADDR (S_AXI_GP1_ARADDR),
.S_ARLEN (S_AXI_GP1_ARLEN),
.S_ARSIZE (S_AXI_GP1_ARSIZE),
.S_ARBURST (S_AXI_GP1_ARBURST),
.S_ARLOCK (S_AXI_GP1_ARLOCK),
.S_ARCACHE (S_AXI_GP1_ARCACHE),
.S_ARPROT (S_AXI_GP1_ARPROT),
.S_ARVALID (S_AXI_GP1_ARVALID),
.S_ARREADY (S_AXI_GP1_ARREADY),
// Read Data Channel Signals.
.S_RID (S_AXI_GP1_RID),
.S_RDATA (S_AXI_GP1_RDATA),
.S_RRESP (S_AXI_GP1_RRESP),
.S_RLAST (S_AXI_GP1_RLAST),
.S_RVALID (S_AXI_GP1_RVALID),
.S_RREADY (S_AXI_GP1_RREADY),
// Side band signals
.S_AWQOS (S_AXI_GP1_AWQOS),
.S_ARQOS (S_AXI_GP1_ARQOS),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
.WR_DATA (net_wr_data_gp1),
.WR_DATA_STRB (net_wr_strb_gp1),
.WR_ADDR (net_wr_addr_gp1),
.WR_BYTES (net_wr_bytes_gp1),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
.WR_QOS (net_wr_qos_gp1),
.RD_REQ_OCM (net_rd_req_ocm_gp1),
.RD_REQ_DDR (net_rd_req_ddr_gp1),
.RD_REQ_REG (net_rd_req_reg_gp1),
.RD_ADDR (net_rd_addr_gp1),
.RD_DATA_DDR (net_rd_data_ddr_gp1),
.RD_DATA_OCM (net_rd_data_ocm_gp1),
.RD_DATA_REG (net_rd_data_reg_gp1),
.RD_BYTES (net_rd_bytes_gp1),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
.RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
.RD_QOS (net_rd_qos_gp1)
);

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_axi_hp.v
*
* Date : 2012-11
*
* Description : Connections for AXI HP ports
*
*****************************************************************************/
/* AXI Slave HP0 */
processing_system7_vip_v1_0_15_afi_slave #( C_USE_S_AXI_HP0, // enable
axi_hp0_name, // name
C_S_AXI_HP0_DATA_WIDTH, // data width
addr_width, /// address width
axi_hp_id_width, // ID width
C_S_AXI_HP0_BASEADDR, // slave base address
C_S_AXI_HP0_HIGHADDR, // slave size
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
axi_slv_excl_support) // Exclusive access support
S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
.S_ACLK (S_AXI_HP0_ACLK),
// Write Address channel
.S_AWID (S_AXI_HP0_AWID),
.S_AWADDR (S_AXI_HP0_AWADDR),
.S_AWLEN (S_AXI_HP0_AWLEN),
.S_AWSIZE (S_AXI_HP0_AWSIZE),
.S_AWBURST (S_AXI_HP0_AWBURST),
.S_AWLOCK (S_AXI_HP0_AWLOCK),
.S_AWCACHE (S_AXI_HP0_AWCACHE),
.S_AWPROT (S_AXI_HP0_AWPROT),
.S_AWVALID (S_AXI_HP0_AWVALID),
.S_AWREADY (S_AXI_HP0_AWREADY),
// Write Data channel signals.
.S_WID (S_AXI_HP0_WID),
.S_WDATA (S_AXI_HP0_WDATA),
.S_WSTRB (S_AXI_HP0_WSTRB),
.S_WLAST (S_AXI_HP0_WLAST),
.S_WVALID (S_AXI_HP0_WVALID),
.S_WREADY (S_AXI_HP0_WREADY),
// Write Response channel signals.
.S_BID (S_AXI_HP0_BID),
.S_BRESP (S_AXI_HP0_BRESP),
.S_BVALID (S_AXI_HP0_BVALID),
.S_BREADY (S_AXI_HP0_BREADY),
// Read Address channel signals.
.S_ARID (S_AXI_HP0_ARID),
.S_ARADDR (S_AXI_HP0_ARADDR),
.S_ARLEN (S_AXI_HP0_ARLEN),
.S_ARSIZE (S_AXI_HP0_ARSIZE),
.S_ARBURST (S_AXI_HP0_ARBURST),
.S_ARLOCK (S_AXI_HP0_ARLOCK),
.S_ARCACHE (S_AXI_HP0_ARCACHE),
.S_ARPROT (S_AXI_HP0_ARPROT),
.S_ARVALID (S_AXI_HP0_ARVALID),
.S_ARREADY (S_AXI_HP0_ARREADY),
// Read Data channel signals.
.S_RID (S_AXI_HP0_RID),
.S_RDATA (S_AXI_HP0_RDATA),
.S_RRESP (S_AXI_HP0_RRESP),
.S_RLAST (S_AXI_HP0_RLAST),
.S_RVALID (S_AXI_HP0_RVALID),
.S_RREADY (S_AXI_HP0_RREADY),
// Side band signals
.S_AWQOS (S_AXI_HP0_AWQOS),
.S_ARQOS (S_AXI_HP0_ARQOS),
// these are needed only for HP ports
.S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
.S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
.S_RCOUNT (S_AXI_HP0_RCOUNT),
.S_WCOUNT (S_AXI_HP0_WCOUNT),
.S_RACOUNT (S_AXI_HP0_RACOUNT),
.S_WACOUNT (S_AXI_HP0_WACOUNT),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
.WR_DATA (net_wr_data_hp0),
.WR_DATA_STRB (net_wr_strb_hp0),
.WR_ADDR (net_wr_addr_hp0),
.WR_BYTES (net_wr_bytes_hp0),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
.WR_QOS (net_wr_qos_hp0),
.RD_REQ_DDR (net_rd_req_ddr_hp0),
.RD_REQ_OCM (net_rd_req_ocm_hp0),
.RD_ADDR (net_rd_addr_hp0),
.RD_DATA_DDR (net_rd_data_ddr_hp0),
.RD_DATA_OCM (net_rd_data_ocm_hp0),
.RD_BYTES (net_rd_bytes_hp0),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
.RD_QOS (net_rd_qos_hp0)
);
/* AXI Slave HP1 */
processing_system7_vip_v1_0_15_afi_slave #( C_USE_S_AXI_HP1, // enable
axi_hp1_name, // name
C_S_AXI_HP1_DATA_WIDTH, // data width
addr_width, /// address width
axi_hp_id_width, // ID width
C_S_AXI_HP1_BASEADDR, // slave base address
C_S_AXI_HP1_HIGHADDR, // Slave size
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
axi_slv_excl_support) // Exclusive access support
S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
.S_ACLK (S_AXI_HP1_ACLK),
// Write Address channel
.S_AWID (S_AXI_HP1_AWID),
.S_AWADDR (S_AXI_HP1_AWADDR),
.S_AWLEN (S_AXI_HP1_AWLEN),
.S_AWSIZE (S_AXI_HP1_AWSIZE),
.S_AWBURST (S_AXI_HP1_AWBURST),
.S_AWLOCK (S_AXI_HP1_AWLOCK),
.S_AWCACHE (S_AXI_HP1_AWCACHE),
.S_AWPROT (S_AXI_HP1_AWPROT),
.S_AWVALID (S_AXI_HP1_AWVALID),
.S_AWREADY (S_AXI_HP1_AWREADY),
// Write Data channel signals.
.S_WID (S_AXI_HP1_WID),
.S_WDATA (S_AXI_HP1_WDATA),
.S_WSTRB (S_AXI_HP1_WSTRB),
.S_WLAST (S_AXI_HP1_WLAST),
.S_WVALID (S_AXI_HP1_WVALID),
.S_WREADY (S_AXI_HP1_WREADY),
// Write Response channel signals.
.S_BID (S_AXI_HP1_BID),
.S_BRESP (S_AXI_HP1_BRESP),
.S_BVALID (S_AXI_HP1_BVALID),
.S_BREADY (S_AXI_HP1_BREADY),
// Read Address channel signals.
.S_ARID (S_AXI_HP1_ARID),
.S_ARADDR (S_AXI_HP1_ARADDR),
.S_ARLEN (S_AXI_HP1_ARLEN),
.S_ARSIZE (S_AXI_HP1_ARSIZE),
.S_ARBURST (S_AXI_HP1_ARBURST),
.S_ARLOCK (S_AXI_HP1_ARLOCK),
.S_ARCACHE (S_AXI_HP1_ARCACHE),
.S_ARPROT (S_AXI_HP1_ARPROT),
.S_ARVALID (S_AXI_HP1_ARVALID),
.S_ARREADY (S_AXI_HP1_ARREADY),
// Read Data channel signals.
.S_RID (S_AXI_HP1_RID),
.S_RDATA (S_AXI_HP1_RDATA),
.S_RRESP (S_AXI_HP1_RRESP),
.S_RLAST (S_AXI_HP1_RLAST),
.S_RVALID (S_AXI_HP1_RVALID),
.S_RREADY (S_AXI_HP1_RREADY),
// Side band signals
.S_AWQOS (S_AXI_HP1_AWQOS),
.S_ARQOS (S_AXI_HP1_ARQOS),
// these are needed only for HP ports
.S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
.S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
.S_RCOUNT (S_AXI_HP1_RCOUNT),
.S_WCOUNT (S_AXI_HP1_WCOUNT),
.S_RACOUNT (S_AXI_HP1_RACOUNT),
.S_WACOUNT (S_AXI_HP1_WACOUNT),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
.WR_DATA (net_wr_data_hp1),
.WR_DATA_STRB (net_wr_strb_hp1),
.WR_ADDR (net_wr_addr_hp1),
.WR_BYTES (net_wr_bytes_hp1),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
.WR_QOS (net_wr_qos_hp1),
.RD_REQ_DDR (net_rd_req_ddr_hp1),
.RD_REQ_OCM (net_rd_req_ocm_hp1),
.RD_ADDR (net_rd_addr_hp1),
.RD_DATA_DDR (net_rd_data_ddr_hp1),
.RD_DATA_OCM (net_rd_data_ocm_hp1),
.RD_BYTES (net_rd_bytes_hp1),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
.RD_QOS (net_rd_qos_hp1)
);
/* AXI Slave HP2 */
processing_system7_vip_v1_0_15_afi_slave #( C_USE_S_AXI_HP2, // enable
axi_hp2_name, // name
C_S_AXI_HP2_DATA_WIDTH, // data width
addr_width, /// address width
axi_hp_id_width, // ID width
C_S_AXI_HP2_BASEADDR, // slave base address
C_S_AXI_HP2_HIGHADDR, // SLave size
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
axi_slv_excl_support) // Exclusive access support
S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
.S_ACLK (S_AXI_HP2_ACLK),
// Write Address channel
.S_AWID (S_AXI_HP2_AWID),
.S_AWADDR (S_AXI_HP2_AWADDR),
.S_AWLEN (S_AXI_HP2_AWLEN),
.S_AWSIZE (S_AXI_HP2_AWSIZE),
.S_AWBURST (S_AXI_HP2_AWBURST),
.S_AWLOCK (S_AXI_HP2_AWLOCK),
.S_AWCACHE (S_AXI_HP2_AWCACHE),
.S_AWPROT (S_AXI_HP2_AWPROT),
.S_AWVALID (S_AXI_HP2_AWVALID),
.S_AWREADY (S_AXI_HP2_AWREADY),
// Write Data channel signals.
.S_WID (S_AXI_HP2_WID),
.S_WDATA (S_AXI_HP2_WDATA),
.S_WSTRB (S_AXI_HP2_WSTRB),
.S_WLAST (S_AXI_HP2_WLAST),
.S_WVALID (S_AXI_HP2_WVALID),
.S_WREADY (S_AXI_HP2_WREADY),
// Write Response channel signals.
.S_BID (S_AXI_HP2_BID),
.S_BRESP (S_AXI_HP2_BRESP),
.S_BVALID (S_AXI_HP2_BVALID),
.S_BREADY (S_AXI_HP2_BREADY),
// Read Address channel signals.
.S_ARID (S_AXI_HP2_ARID),
.S_ARADDR (S_AXI_HP2_ARADDR),
.S_ARLEN (S_AXI_HP2_ARLEN),
.S_ARSIZE (S_AXI_HP2_ARSIZE),
.S_ARBURST (S_AXI_HP2_ARBURST),
.S_ARLOCK (S_AXI_HP2_ARLOCK),
.S_ARCACHE (S_AXI_HP2_ARCACHE),
.S_ARPROT (S_AXI_HP2_ARPROT),
.S_ARVALID (S_AXI_HP2_ARVALID),
.S_ARREADY (S_AXI_HP2_ARREADY),
// Read Data channel signals.
.S_RID (S_AXI_HP2_RID),
.S_RDATA (S_AXI_HP2_RDATA),
.S_RRESP (S_AXI_HP2_RRESP),
.S_RLAST (S_AXI_HP2_RLAST),
.S_RVALID (S_AXI_HP2_RVALID),
.S_RREADY (S_AXI_HP2_RREADY),
// Side band signals
.S_AWQOS (S_AXI_HP2_AWQOS),
.S_ARQOS (S_AXI_HP2_ARQOS),
// these are needed only for HP ports
.S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
.S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
.S_RCOUNT (S_AXI_HP2_RCOUNT),
.S_WCOUNT (S_AXI_HP2_WCOUNT),
.S_RACOUNT (S_AXI_HP2_RACOUNT),
.S_WACOUNT (S_AXI_HP2_WACOUNT),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
.WR_DATA (net_wr_data_hp2),
.WR_DATA_STRB (net_wr_strb_hp2),
.WR_ADDR (net_wr_addr_hp2),
.WR_BYTES (net_wr_bytes_hp2),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
.WR_QOS (net_wr_qos_hp2),
.RD_REQ_DDR (net_rd_req_ddr_hp2),
.RD_REQ_OCM (net_rd_req_ocm_hp2),
.RD_ADDR (net_rd_addr_hp2),
.RD_DATA_DDR (net_rd_data_ddr_hp2),
.RD_DATA_OCM (net_rd_data_ocm_hp2),
.RD_BYTES (net_rd_bytes_hp2),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
.RD_QOS (net_rd_qos_hp2)
);
/* AXI Slave HP3 */
processing_system7_vip_v1_0_15_afi_slave #( C_USE_S_AXI_HP3, // enable
axi_hp3_name, // name
C_S_AXI_HP3_DATA_WIDTH, // data width
addr_width, /// address width
axi_hp_id_width, // ID width
C_S_AXI_HP3_BASEADDR, // slave base address
C_S_AXI_HP3_HIGHADDR, // SLave size
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
axi_slv_excl_support) // Exclusive access support
S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
.S_ACLK (S_AXI_HP3_ACLK),
// Write ADDRESS CHANNEL
.S_AWID (S_AXI_HP3_AWID),
.S_AWADDR (S_AXI_HP3_AWADDR),
.S_AWLEN (S_AXI_HP3_AWLEN),
.S_AWSIZE (S_AXI_HP3_AWSIZE),
.S_AWBURST (S_AXI_HP3_AWBURST),
.S_AWLOCK (S_AXI_HP3_AWLOCK),
.S_AWCACHE (S_AXI_HP3_AWCACHE),
.S_AWPROT (S_AXI_HP3_AWPROT),
.S_AWVALID (S_AXI_HP3_AWVALID),
.S_AWREADY (S_AXI_HP3_AWREADY),
// Write Data channel signals.
.S_WID (S_AXI_HP3_WID),
.S_WDATA (S_AXI_HP3_WDATA),
.S_WSTRB (S_AXI_HP3_WSTRB),
.S_WLAST (S_AXI_HP3_WLAST),
.S_WVALID (S_AXI_HP3_WVALID),
.S_WREADY (S_AXI_HP3_WREADY),
// Write Response channel signals.
.S_BID (S_AXI_HP3_BID),
.S_BRESP (S_AXI_HP3_BRESP),
.S_BVALID (S_AXI_HP3_BVALID),
.S_BREADY (S_AXI_HP3_BREADY),
// Read Address channel signals.
.S_ARID (S_AXI_HP3_ARID),
.S_ARADDR (S_AXI_HP3_ARADDR),
.S_ARLEN (S_AXI_HP3_ARLEN),
.S_ARSIZE (S_AXI_HP3_ARSIZE),
.S_ARBURST (S_AXI_HP3_ARBURST),
.S_ARLOCK (S_AXI_HP3_ARLOCK),
.S_ARCACHE (S_AXI_HP3_ARCACHE),
.S_ARPROT (S_AXI_HP3_ARPROT),
.S_ARVALID (S_AXI_HP3_ARVALID),
.S_ARREADY (S_AXI_HP3_ARREADY),
// Read Data channel signals.
.S_RID (S_AXI_HP3_RID),
.S_RDATA (S_AXI_HP3_RDATA),
.S_RRESP (S_AXI_HP3_RRESP),
.S_RLAST (S_AXI_HP3_RLAST),
.S_RVALID (S_AXI_HP3_RVALID),
.S_RREADY (S_AXI_HP3_RREADY),
// Side band signals
.S_AWQOS (S_AXI_HP3_AWQOS),
.S_ARQOS (S_AXI_HP3_ARQOS),
// these are needed only for HP ports
.S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
.S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
.S_RCOUNT (S_AXI_HP3_RCOUNT),
.S_WCOUNT (S_AXI_HP3_WCOUNT),
.S_RACOUNT (S_AXI_HP3_RACOUNT),
.S_WACOUNT (S_AXI_HP3_WACOUNT),
.SW_CLK (net_sw_clk),
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
.WR_DATA (net_wr_data_hp3),
.WR_DATA_STRB (net_wr_strb_hp3),
.WR_ADDR (net_wr_addr_hp3),
.WR_BYTES (net_wr_bytes_hp3),
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
.WR_QOS (net_wr_qos_hp3),
.RD_REQ_DDR (net_rd_req_ddr_hp3),
.RD_REQ_OCM (net_rd_req_ocm_hp3),
.RD_ADDR (net_rd_addr_hp3),
.RD_DATA_DDR (net_rd_data_ddr_hp3),
.RD_DATA_OCM (net_rd_data_ocm_hp3),
.RD_BYTES (net_rd_bytes_hp3),
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
.RD_QOS (net_rd_qos_hp3)
);

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_local_params.v
*
* Date : 2012-11
*
* Description : Parameters used in Zynq VIP
*
*****************************************************************************/
/* local */
parameter m_axi_gp0_baseaddr = 32'h4000_0000;
parameter m_axi_gp1_baseaddr = 32'h8000_0000;
parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
parameter addr_width = 32; // maximum address width
parameter data_width = 32; // maximum data width.
parameter max_chars = 128; // max characters for file name
parameter mem_width = data_width/8; /// memory width in bytes
parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
parameter int_width = 32; //integre width
/* for internal read/write APIs used for data transfers */
parameter max_burst_len = 16; /// maximum brst length on axi
parameter max_data_width = 64; // maximum data width for internal AXI bursts
parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
parameter max_registers = 32;
parameter max_regs_width = clogb2(max_registers);
parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
/* Interrupt bits supported */
parameter irq_width = 16;
/* GP Master0 & Master1 address decode */
parameter GP_M0 = 2'b01;
parameter GP_M1 = 2'b10;
parameter ALL_RANDOM= 2'b00;
parameter ALL_ZEROS = 2'b01;
parameter ALL_ONES = 2'b10;
parameter ddr_start_addr = 32'h0008_0000;
parameter ddr_end_addr = 32'h7FFF_FFFF;
parameter ocm_start_addr = 32'h0000_0000;
parameter ocm_end_addr = 32'h0003_FFFF;
parameter high_ocm_start_addr = 32'hFFFC_0000;
parameter high_ocm_end_addr = 32'hFFFF_FFFF;
parameter ocm_low_addr = 32'hFFFF_0000;
parameter reg_start_addr = 32'hE000_0000;
parameter reg_end_addr = 32'hF8F0_2F80;
/* for Master port APIs and AXI protocol related signal widths*/
parameter axi_burst_len = 16;
parameter axi_len_width = clogb2(axi_burst_len);
parameter axi_size_width = 3;
parameter axi_brst_type_width = 2;
parameter axi_lock_width = 2;
parameter axi_cache_width = 4;
parameter axi_prot_width = 3;
parameter axi_rsp_width = 2;
parameter axi_mgp_data_width = 32;
parameter axi_mgp_id_width = 12;
parameter axi_mgp_outstanding = 8;
parameter axi_mgp_wr_id = 12'hC00;
parameter axi_mgp_rd_id = 12'hC0C;
parameter axi_mgp0_name = "M_AXI_GP0";
parameter axi_mgp1_name = "M_AXI_GP1";
parameter axi_qos_width = 4;
parameter max_transfer_bytes = 256; // For Master APIs.
parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
/* for GP slave ports*/
parameter axi_sgp_data_width = 32;
parameter axi_sgp_id_width = 6;
parameter axi_sgp_rd_outstanding = 8;
parameter axi_sgp_wr_outstanding = 8;
parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
parameter axi_sgp0_name = "S_AXI_GP0";
parameter axi_sgp1_name = "S_AXI_GP1";
/* for ACP slave ports*/
parameter axi_acp_data_width = 64;
parameter axi_acp_id_width = 3;
parameter axi_acp_rd_outstanding = 7;
parameter axi_acp_wr_outstanding = 3;
parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
parameter axi_acp_name = "S_AXI_ACP";
/* for HP slave ports*/
parameter axi_hp_id_width = 6;
parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
parameter axi_hp0_name = "S_AXI_HP0";
parameter axi_hp1_name = "S_AXI_HP1";
parameter axi_hp2_name = "S_AXI_HP2";
parameter axi_hp3_name = "S_AXI_HP3";
parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
/* AXI transfer types */
parameter AXI_FIXED = 2'b00;
parameter AXI_INCR = 2'b01;
parameter AXI_WRAP = 2'b10;
/* Exclusive Access */
parameter AXI_NRML = 2'b00;
parameter AXI_EXCL = 2'b01;
parameter AXI_LOCK = 2'b10;
/* AXI Response types */
parameter AXI_OK = 2'b00;
parameter AXI_EXCL_OK = 2'b01;
parameter AXI_SLV_ERR = 2'b10;
parameter AXI_DEC_ERR = 2'b11;
function automatic integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
/* WR FIFO data */
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
// parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
// parameter wr_bytes_lsb = 0;
// parameter wr_bytes_msb = max_burst_bytes_width;
// parameter wr_addr_lsb = wr_bytes_msb + 1;
// parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
// parameter wr_data_lsb = wr_addr_msb + 1;
// parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
// parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
// parameter wr_qos_lsb = wr_data_msb + 1;
// `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
/* WR AFI FIFO data */
/* ID - 1071:1066
Resp - 1065:1064
data - 1063:40
address - 39:8
valid_bytes - 7:0
*/
// parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
// parameter wr_afi_bytes_lsb = 0;
// parameter wr_afi_bytes_msb = max_burst_bytes_width;
// parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
// parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
// parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
// parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
// parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
// parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
// parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
// parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
// parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
// parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
/* for interconnect fifo models */
parameter intr_max_outstanding = 8;
parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
parameter rd_afi_bytes_lsb = 0;
parameter rd_afi_bytes_msb = max_burst_bytes_width;
parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
/* Latency types */
parameter BEST_CASE = 0;
parameter AVG_CASE = 1;
parameter WORST_CASE = 2;
parameter RANDOM_CASE = 3;
/* Latency Parameters ACP */
parameter acp_wr_min = 21;
parameter acp_wr_avg = 16;
parameter acp_wr_max = 27;
parameter acp_rd_min = 34;
parameter acp_rd_avg = 125;
parameter acp_rd_max = 130;
/* Latency Parameters GP */
parameter gp_wr_min = 21;
parameter gp_wr_avg = 16;
parameter gp_wr_max = 46;
parameter gp_rd_min = 38;
parameter gp_rd_avg = 125;
parameter gp_rd_max = 130;
/* Latency Parameters HP */
parameter afi_wr_min = 37;
parameter afi_wr_avg = 41;
parameter afi_wr_max = 42;
parameter afi_rd_min = 41;
parameter afi_rd_avg = 221;
parameter afi_rd_max = 229;
/* ID VALID and INVALID */
parameter secure_access_enabled = 0;
parameter id_invalid = 0;
parameter id_valid = 1;
/* Display */
parameter DISP_INFO = "*ZYNQ_VIP_INFO";
parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

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/*****************************************************************************
* File : processing_system7_vip_v1_0_15_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
// if(GPIO_I !== 0)
// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
// if(MIO !== 0)
// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
// if(DDR_ARB !== 0)
// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;

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// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI VIP wrapper
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_vip
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_vip_v1_1_13_top #
(
parameter C_AXI_PROTOCOL = 0,
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_WDATA_WIDTH = 32,
parameter integer C_AXI_RDATA_WIDTH = 32,
parameter integer C_AXI_WID_WIDTH = 0,
parameter integer C_AXI_RID_WIDTH = 0,
parameter integer C_AXI_AWUSER_WIDTH = 0,
parameter integer C_AXI_ARUSER_WIDTH = 0,
parameter integer C_AXI_WUSER_WIDTH = 0,
parameter integer C_AXI_RUSER_WIDTH = 0,
parameter integer C_AXI_BUSER_WIDTH = 0,
parameter integer C_AXI_SUPPORTS_NARROW = 1,
parameter integer C_AXI_HAS_BURST = 1,
parameter integer C_AXI_HAS_LOCK = 1,
parameter integer C_AXI_HAS_CACHE = 1,
parameter integer C_AXI_HAS_REGION = 1,
parameter integer C_AXI_HAS_PROT = 1,
parameter integer C_AXI_HAS_QOS = 1,
parameter integer C_AXI_HAS_WSTRB = 1,
parameter integer C_AXI_HAS_BRESP = 1,
parameter integer C_AXI_HAS_RRESP = 1,
parameter integer C_AXI_HAS_ARESETN = 1
)
(
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
//Please refer xgui tcl and coreinfo.yml
// System Signals
input wire aclk,
input wire aclken,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
/**********************************************************************************************
* NOTE:
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
* Please refer xgui tcl and coreinfo.yml
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
* the simulation
*********************************************************************************************/
/**********************************************************************************************
* Master_mode means that either the dut is statically being configured to be in master mode
* or it statically being configured to be pass-through mode and switched to be in master mode
* in run time.
* Slave mode means that either the dut is statically being configured to be in slave mode
* or it statically being configured to be pass-through mode and switched to be in slave mode
* in run time.
* Pass-through mode means that either the dut is statically being configured to be in
* pass-through mode or it statically being configured to be pass-through mode and switched
* to be in master/slave mode and then switch back to be in pass-through mode in run time
*********************************************************************************************/
logic runtime_master =0;
logic runtime_slave =0;
wire run_slave_mode;
wire run_master_mode;
wire run_passth_mode;
wire compile_master_mode;
wire compile_slave_mode;
wire master_mode;
wire slave_mode;
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
assign master_mode = compile_master_mode || run_master_mode;
assign slave_mode = compile_slave_mode || run_slave_mode;
// Slave Interface Write Address Ports Internal
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
// Slave Interface Write Data Ports
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
// Slave Interface Write Response Ports
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
// Slave Interface Read Address Ports
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
//Slave Interface Read Data Ports
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
// Master Interface Write Address Port
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
// Master Interface Write Data Ports Internal
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
// Master Interface Write Response Ports Internal
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
// Master Interface Read Address Port Internal
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
// Master Interface Read Data Ports Internal
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
axi_vip_if #(
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
) IF (
.ACLK(aclk),
.ARESET_N(aresetn),
.ACLKEN(aclken)
);
//synthesis translate_off
initial begin
$display("XilinxAXIVIP: Found at Path: %m");
end
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
generate
initial begin
if(C_AXI_INTERFACE_MODE ==0) begin
IF.set_intf_master;
end else if(C_AXI_INTERFACE_MODE ==2) begin
IF.set_intf_slave;
end else if(C_AXI_INTERFACE_MODE ==1) begin
$display("This AXI VIP is in passthrough mode");
end else begin
$fatal(0,"This AXI VIP's mode is out of range");
end
end
endgenerate
/*
Function: set_passthrough_mode
Sets AXI VIP passthrough into run time passthrough mode
*/
function void set_passthrough_mode();
if (C_AXI_INTERFACE_MODE == 1) begin
runtime_master = 0;
runtime_slave = 0;
IF.set_intf_monitor();
end else begin
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
end
endfunction: set_passthrough_mode
/*
Function: set_master_mode
Sets AXI VIP passthrough into run time master mode
*/
function void set_master_mode();
if (C_AXI_INTERFACE_MODE == 1) begin
runtime_master = 1;
runtime_slave = 0;
IF.set_intf_master();
end else begin
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
end
endfunction : set_master_mode
/*
Function: set_slave_mode
Sets AXI VIP passthrough into run time slave mode
*/
function void set_slave_mode();
if (C_AXI_INTERFACE_MODE == 1) begin
runtime_master = 0;
runtime_slave = 1;
IF.set_intf_slave();
end else begin
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
end
endfunction : set_slave_mode
/*
Function: set_xilinx_slave_ready_check
Sets xilinx_slave_ready_check_enable of IF to be 1
*/
function void set_xilinx_slave_ready_check();
IF.xilinx_slave_ready_check_enable = 1;
endfunction
/*
Function: clr_xilinx_slave_ready_check
Sets xilinx_slave_ready_check_enable of IF to be 0
*/
function void clr_xilinx_slave_ready_check();
IF.xilinx_slave_ready_check_enable = 0;
endfunction
/*
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_aw_wait_cycles(input integer unsigned new_num);
IF.PC.max_aw_wait_cycles = new_num;
endfunction : set_max_aw_wait_cycles
/*
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_ar_wait_cycles(input integer unsigned new_num);
IF.PC.max_ar_wait_cycles = new_num;
endfunction : set_max_ar_wait_cycles
/*
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_r_wait_cycles(input integer unsigned new_num);
IF.PC.max_r_wait_cycles = new_num;
endfunction : set_max_r_wait_cycles
/*
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_b_wait_cycles(input integer unsigned new_num);
IF.PC.max_b_wait_cycles = new_num;
endfunction : set_max_b_wait_cycles
/*
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_w_wait_cycles(input integer unsigned new_num);
IF.PC.max_w_wait_cycles = new_num;
endfunction : set_max_w_wait_cycles
/*
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
endfunction : set_max_wlast_wait_cycles
/*
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
IF.PC.max_rtransfers_wait_cycles = new_num;
endfunction : set_max_rtransfers_wait_cycles
/*
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
IF.PC.max_wtransfers_wait_cycles = new_num;
endfunction : set_max_wtransfers_wait_cycles
/*
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
*/
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
IF.PC.max_wlcmd_wait_cycles = new_num;
endfunction : set_max_wlcmd_wait_cycles
/*
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_aw_wait_cycles();
return(IF.PC.max_aw_wait_cycles);
endfunction : get_max_aw_wait_cycles
/*
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_ar_wait_cycles();
return(IF.PC.max_ar_wait_cycles);
endfunction : get_max_ar_wait_cycles
/*
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_r_wait_cycles();
return(IF.PC.max_r_wait_cycles);
endfunction : get_max_r_wait_cycles
/*
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_b_wait_cycles();
return(IF.PC.max_b_wait_cycles);
endfunction : get_max_b_wait_cycles
/*
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_w_wait_cycles();
return(IF.PC.max_w_wait_cycles);
endfunction :get_max_w_wait_cycles
/*
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_wlast_wait_cycles();
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
endfunction :get_max_wlast_wait_cycles
/*
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_rtransfers_wait_cycles();
return(IF.PC.max_rtransfers_wait_cycles);
endfunction :get_max_rtransfers_wait_cycles
/*
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_wtransfers_wait_cycles();
return(IF.PC.max_wtransfers_wait_cycles);
endfunction :get_max_wtransfers_wait_cycles
/*
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
*/
function integer unsigned get_max_wlcmd_wait_cycles();
return(IF.PC.max_wlcmd_wait_cycles);
endfunction :get_max_wlcmd_wait_cycles
/*
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
*/
function void set_fatal_to_warnings();
IF.PC.fatal_to_warnings = 1;
endfunction : set_fatal_to_warnings
/*
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
*/
function void clr_fatal_to_warnings();
IF.PC.fatal_to_warnings = 0;
endfunction : clr_fatal_to_warnings
//synthesis translate_on
endmodule // axi_vip_v1_1_13_top

9
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{
"version": "1.0",
"modules": {
"design_1": {
"proto_instances": {
}
}
}
}

101
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024
//Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *)
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
endmodule

BIN
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project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v Normal file
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024
//Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *)
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
endmodule

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2022.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>

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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

500
project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v Normal file
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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_vip_v1_0_15 #(
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(50.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule

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{
"version": "1.0",
"modules": {
"design_1": {
"proto_instances": {
}
}
}
}

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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024
//Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *)
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
endmodule

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<?xml version="1.0" encoding="utf-8"?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">design_1</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0"/>
<edge id="e1" source="n0" target="n1"/>
</graph>
</graphml>

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}

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/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}

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################################################################################
# Vivado (TM) v2022.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./design_1.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './design_1.sh' script.
./design_1.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./design_1.sh -noclean_files
For more information on the script, please type './design_1.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.

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vlib work
vlib activehdl
vlib activehdl/xilinx_vip
vlib activehdl/axi_infrastructure_v1_1_0
vlib activehdl/axi_vip_v1_1_13
vlib activehdl/processing_system7_vip_v1_0_15
vlib activehdl/xil_defaultlib
vmap xilinx_vip activehdl/xilinx_vip
vmap axi_infrastructure_v1_1_0 activehdl/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_13 activehdl/axi_vip_v1_1_13
vmap processing_system7_vip_v1_0_15 activehdl/processing_system7_vip_v1_0_15
vmap xil_defaultlib activehdl/xil_defaultlib
vlog -work xilinx_vip -sv2k12 "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work axi_infrastructure_v1_1_0 -v2k5 "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_13 -sv2k12 "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_15 -sv2k12 "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v" \
"../../../bd/design_1/sim/design_1.v" \
vlog -work xil_defaultlib \
"glbl.v"

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<?xml version="1.0" encoding="utf-8"?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">design_1</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0"/>
<edge id="e1" source="n0" target="n1"/>
</graph>
</graphml>

151
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@ -0,0 +1,151 @@
#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2022.2 (64-bit)
#
# Filename : design_1.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
#
# Tool Version Limit: 2022.10
#
# usage: design_1.sh [-help]
# usage: design_1.sh [-lib_map_path]
# usage: design_1.sh [-noclean_files]
# usage: design_1.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'design_1.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "design_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n"
exit 1
fi
map_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
map_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Map library.cfg file
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: design_1.sh [-help]\n\
Usage: design_1.sh [-lib_map_path]\n\
Usage: design_1.sh [-reset_run]\n\
Usage: design_1.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2

0
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.udo Normal file
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15
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt Normal file
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axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../project_1.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_15,../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
design_1_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v

84
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@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif

47
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@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

47
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@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

47
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/libremoteport.dll Normal file
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@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

47
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/libremoteport.so Normal file
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@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000800
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000800
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000220
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000000
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000000
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}

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/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 10000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 10000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 10000000
#define UART_FREQ 100000000
#define SPI_FREQ 166666672
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif

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onbreak {quit -force}
onerror {quit -force}
asim +access +r +m+design_1 -L xilinx_vip -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do {wave.do}
view wave
view structure
do {design_1.udo}
run 1000ns
endsim
quit -force

2
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/wave.do Normal file
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add wave *
add wave /glbl/GSR

106
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/xilinx-zynq.cc Normal file
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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}

49
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt Normal file
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################################################################################
# Vivado (TM) v2022.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./design_1.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './design_1.sh' script.
./design_1.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./design_1.sh -noclean_files
For more information on the script, please type './design_1.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.

42
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/compile.do Normal file
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vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xilinx_vip
vlib modelsim_lib/msim/axi_infrastructure_v1_1_0
vlib modelsim_lib/msim/axi_vip_v1_1_13
vlib modelsim_lib/msim/processing_system7_vip_v1_0_15
vlib modelsim_lib/msim/xil_defaultlib
vmap xilinx_vip modelsim_lib/msim/xilinx_vip
vmap axi_infrastructure_v1_1_0 modelsim_lib/msim/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_13 modelsim_lib/msim/axi_vip_v1_1_13
vmap processing_system7_vip_v1_0_15 modelsim_lib/msim/processing_system7_vip_v1_0_15
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"C:/Xilinx/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work axi_infrastructure_v1_1_0 -incr -mfcu "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_13 -incr -mfcu -sv -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_15 -incr -mfcu -sv -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../project_1.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+C:/Xilinx/Vivado/2022.2/data/xilinx_vip/include" \
"../../../bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v" \
"../../../bd/design_1/sim/design_1.v" \
vlog -work xil_defaultlib \
"glbl.v"

42
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda Normal file
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<?xml version="1.0" encoding="utf-8"?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">design_1</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0"/>
<edge id="e1" source="n0" target="n1"/>
</graph>
</graphml>

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