diff --git a/Packages/.repos.xml b/Packages/.repos.xml new file mode 100644 index 0000000..55f8c8c --- /dev/null +++ b/Packages/.repos.xml @@ -0,0 +1,13 @@ + + + + CMSIS Pack + Keil + http://www.keil.com/pack/index.idx + + + XCDL/CMSIS Pack + GNU ARM Eclipse + http://gnuarmeclipse.sourceforge.net/packages/content.xml + + diff --git a/project_1/design_1_wrapper.xsa b/project_1/design_1_wrapper.xsa index ebc5348..a818322 100644 Binary files a/project_1/design_1_wrapper.xsa and b/project_1/design_1_wrapper.xsa differ diff --git a/project_1/project_1.cache/wt/project.wpc b/project_1/project_1.cache/wt/project.wpc index 3c63dc5..7a5a66e 100644 --- a/project_1/project_1.cache/wt/project.wpc +++ b/project_1/project_1.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 -57656254616c6b5472616e736d697373696f6e417474656d70746564:1 -6d6f64655f636f756e7465727c4755494d6f6465:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:8 +6d6f64655f636f756e7465727c4755494d6f6465:4 eof: diff --git a/project_1/project_1.cache/wt/synthesis.wdf b/project_1/project_1.cache/wt/synthesis.wdf index b1be6aa..2a460ec 100644 --- a/project_1/project_1.cache/wt/synthesis.wdf +++ b/project_1/project_1.cache/wt/synthesis.wdf @@ -41,7 +41,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333573:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313332302e3636304d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3930362e3531364d42:00:00 -eof:2809958735 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333773:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313330342e3436314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3838342e3331324d42:00:00 +eof:2933133820 diff --git a/project_1/project_1.cache/wt/webtalk_pa.xml b/project_1/project_1.cache/wt/webtalk_pa.xml index bf28112..2d03aa6 100644 --- a/project_1/project_1.cache/wt/webtalk_pa.xml +++ b/project_1/project_1.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
diff --git a/project_1/project_1.gen/sources_1/bd/design_1/design_1.bda b/project_1/project_1.gen/sources_1/bd/design_1/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/design_1.bda +++ b/project_1/project_1.gen/sources_1/bd/design_1/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.gen/sources_1/bd/design_1/design_1.bxml b/project_1/project_1.gen/sources_1/bd/design_1/design_1.bxml index 697c884..2d3857a 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/design_1.bxml +++ b/project_1/project_1.gen/sources_1/bd/design_1/design_1.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc b/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc index 46d92ca..7fac2b2 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc +++ b/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc @@ -6,6 +6,5 @@ # This constraints file is not used in normal top-down synthesis (default flow # of Vivado) ################################################################################ -create_clock -name processing_system7_0_FCLK_CLK0 -period 20 [get_pins processing_system7_0/FCLK_CLK0] ################################################################################ \ No newline at end of file diff --git a/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v index c89c718..2ed0977 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -1,7 +1,7 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -//Date : Sun Oct 20 21:34:05 2024 +//Date : Fri Oct 25 01:46:36 2024 //Host : destop1 running 64-bit major release (build 9200) //Command : generate_target design_1_wrapper.bd //Design : design_1_wrapper diff --git a/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh b/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh index f3bd433..7b770a2 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh +++ b/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh @@ -1,5 +1,5 @@  - + @@ -14,12 +14,12 @@ - + - + @@ -29,7 +29,7 @@ - + @@ -213,7 +213,7 @@ - + @@ -256,11 +256,11 @@ - + - + @@ -326,7 +326,7 @@ - + @@ -353,9 +353,9 @@ - - - + + + @@ -369,27 +369,27 @@ - + - + - - - - - - - + + + + + + + - - + + @@ -397,11 +397,11 @@ - + - + @@ -410,8 +410,8 @@ - - + + @@ -420,12 +420,12 @@ - + - - + + - + @@ -546,7 +546,7 @@ - + @@ -568,11 +568,11 @@ - + - + @@ -726,10 +726,10 @@ - - - - + + + + @@ -792,8 +792,8 @@ - - + + @@ -828,54 +828,54 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -884,14 +884,14 @@ - - - - - - - - + + + + + + + + @@ -904,152 +904,152 @@ - - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - + @@ -1101,8 +1101,6 @@ - - diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp index 8d6a2fa..b44361e 100644 Binary files a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp and b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp differ diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc index 9943577..7811620 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc @@ -17,15 +17,236 @@ ############################################################################ # Clock constraints # ############################################################################ -create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"] -set_input_jitter clk_fpga_0 0.6 -#The clocks are asynchronous, user should constrain them appropriately.# ############################################################################ # I/O STANDARDS and Location Constraints # ############################################################################ +# GPIO / gpio[53] / MIO[53] +set_property iostandard "LVCMOS33" [get_ports "MIO[53]"] +set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"] +set_property slew "slow" [get_ports "MIO[53]"] +set_property drive "8" [get_ports "MIO[53]"] +set_property pullup "TRUE" [get_ports "MIO[53]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"] +# GPIO / gpio[52] / MIO[52] +set_property iostandard "LVCMOS33" [get_ports "MIO[52]"] +set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"] +set_property slew "slow" [get_ports "MIO[52]"] +set_property drive "8" [get_ports "MIO[52]"] +set_property pullup "TRUE" [get_ports "MIO[52]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[52]"] +# GPIO / gpio[51] / MIO[51] +set_property iostandard "LVCMOS33" [get_ports "MIO[51]"] +set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"] +set_property slew "slow" [get_ports "MIO[51]"] +set_property drive "8" [get_ports "MIO[51]"] +set_property pullup "TRUE" [get_ports "MIO[51]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"] +# GPIO / gpio[50] / MIO[50] +set_property iostandard "LVCMOS33" [get_ports "MIO[50]"] +set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"] +set_property slew "slow" [get_ports "MIO[50]"] +set_property drive "8" [get_ports "MIO[50]"] +set_property pullup "TRUE" [get_ports "MIO[50]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"] +# GPIO / gpio[49] / MIO[49] +set_property iostandard "LVCMOS33" [get_ports "MIO[49]"] +set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"] +set_property slew "slow" [get_ports "MIO[49]"] +set_property drive "8" [get_ports "MIO[49]"] +set_property pullup "TRUE" [get_ports "MIO[49]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[49]"] +# GPIO / gpio[48] / MIO[48] +set_property iostandard "LVCMOS33" [get_ports "MIO[48]"] +set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"] +set_property slew "slow" [get_ports "MIO[48]"] +set_property drive "8" [get_ports "MIO[48]"] +set_property pullup "TRUE" [get_ports "MIO[48]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[48]"] +# GPIO / gpio[47] / MIO[47] +set_property iostandard "LVCMOS33" [get_ports "MIO[47]"] +set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"] +set_property slew "slow" [get_ports "MIO[47]"] +set_property drive "8" [get_ports "MIO[47]"] +set_property pullup "TRUE" [get_ports "MIO[47]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"] +# GPIO / gpio[46] / MIO[46] +set_property iostandard "LVCMOS33" [get_ports "MIO[46]"] +set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"] +set_property slew "slow" [get_ports "MIO[46]"] +set_property drive "8" [get_ports "MIO[46]"] +set_property pullup "TRUE" [get_ports "MIO[46]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"] +# GPIO / gpio[45] / MIO[45] +set_property iostandard "LVCMOS33" [get_ports "MIO[45]"] +set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"] +set_property slew "slow" [get_ports "MIO[45]"] +set_property drive "8" [get_ports "MIO[45]"] +set_property pullup "TRUE" [get_ports "MIO[45]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"] +# GPIO / gpio[44] / MIO[44] +set_property iostandard "LVCMOS33" [get_ports "MIO[44]"] +set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"] +set_property slew "slow" [get_ports "MIO[44]"] +set_property drive "8" [get_ports "MIO[44]"] +set_property pullup "TRUE" [get_ports "MIO[44]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"] +# GPIO / gpio[43] / MIO[43] +set_property iostandard "LVCMOS33" [get_ports "MIO[43]"] +set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"] +set_property slew "slow" [get_ports "MIO[43]"] +set_property drive "8" [get_ports "MIO[43]"] +set_property pullup "TRUE" [get_ports "MIO[43]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"] +# GPIO / gpio[42] / MIO[42] +set_property iostandard "LVCMOS33" [get_ports "MIO[42]"] +set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"] +set_property slew "slow" [get_ports "MIO[42]"] +set_property drive "8" [get_ports "MIO[42]"] +set_property pullup "TRUE" [get_ports "MIO[42]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"] +# GPIO / gpio[41] / MIO[41] +set_property iostandard "LVCMOS33" [get_ports "MIO[41]"] +set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"] +set_property slew "slow" [get_ports "MIO[41]"] +set_property drive "8" [get_ports "MIO[41]"] +set_property pullup "TRUE" [get_ports "MIO[41]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"] +# GPIO / gpio[40] / MIO[40] +set_property iostandard "LVCMOS33" [get_ports "MIO[40]"] +set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"] +set_property slew "slow" [get_ports "MIO[40]"] +set_property drive "8" [get_ports "MIO[40]"] +set_property pullup "TRUE" [get_ports "MIO[40]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"] +# GPIO / gpio[39] / MIO[39] +set_property iostandard "LVCMOS33" [get_ports "MIO[39]"] +set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"] +set_property slew "slow" [get_ports "MIO[39]"] +set_property drive "8" [get_ports "MIO[39]"] +set_property pullup "TRUE" [get_ports "MIO[39]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"] +# GPIO / gpio[38] / MIO[38] +set_property iostandard "LVCMOS33" [get_ports "MIO[38]"] +set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"] +set_property slew "slow" [get_ports "MIO[38]"] +set_property drive "8" [get_ports "MIO[38]"] +set_property pullup "TRUE" [get_ports "MIO[38]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"] +# GPIO / gpio[37] / MIO[37] +set_property iostandard "LVCMOS33" [get_ports "MIO[37]"] +set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"] +set_property slew "slow" [get_ports "MIO[37]"] +set_property drive "8" [get_ports "MIO[37]"] +set_property pullup "TRUE" [get_ports "MIO[37]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"] +# GPIO / gpio[36] / MIO[36] +set_property iostandard "LVCMOS33" [get_ports "MIO[36]"] +set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"] +set_property slew "slow" [get_ports "MIO[36]"] +set_property drive "8" [get_ports "MIO[36]"] +set_property pullup "TRUE" [get_ports "MIO[36]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"] +# GPIO / gpio[35] / MIO[35] +set_property iostandard "LVCMOS33" [get_ports "MIO[35]"] +set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"] +set_property slew "slow" [get_ports "MIO[35]"] +set_property drive "8" [get_ports "MIO[35]"] +set_property pullup "TRUE" [get_ports "MIO[35]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"] +# GPIO / gpio[34] / MIO[34] +set_property iostandard "LVCMOS33" [get_ports "MIO[34]"] +set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"] +set_property slew "slow" [get_ports "MIO[34]"] +set_property drive "8" [get_ports "MIO[34]"] +set_property pullup "TRUE" [get_ports "MIO[34]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"] +# GPIO / gpio[33] / MIO[33] +set_property iostandard "LVCMOS33" [get_ports "MIO[33]"] +set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"] +set_property slew "slow" [get_ports "MIO[33]"] +set_property drive "8" [get_ports "MIO[33]"] +set_property pullup "TRUE" [get_ports "MIO[33]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"] +# GPIO / gpio[32] / MIO[32] +set_property iostandard "LVCMOS33" [get_ports "MIO[32]"] +set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"] +set_property slew "slow" [get_ports "MIO[32]"] +set_property drive "8" [get_ports "MIO[32]"] +set_property pullup "TRUE" [get_ports "MIO[32]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"] +# GPIO / gpio[31] / MIO[31] +set_property iostandard "LVCMOS33" [get_ports "MIO[31]"] +set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"] +set_property slew "slow" [get_ports "MIO[31]"] +set_property drive "8" [get_ports "MIO[31]"] +set_property pullup "TRUE" [get_ports "MIO[31]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"] +# GPIO / gpio[30] / MIO[30] +set_property iostandard "LVCMOS33" [get_ports "MIO[30]"] +set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"] +set_property slew "slow" [get_ports "MIO[30]"] +set_property drive "8" [get_ports "MIO[30]"] +set_property pullup "TRUE" [get_ports "MIO[30]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"] +# GPIO / gpio[29] / MIO[29] +set_property iostandard "LVCMOS33" [get_ports "MIO[29]"] +set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"] +set_property slew "slow" [get_ports "MIO[29]"] +set_property drive "8" [get_ports "MIO[29]"] +set_property pullup "TRUE" [get_ports "MIO[29]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"] +# GPIO / gpio[28] / MIO[28] +set_property iostandard "LVCMOS33" [get_ports "MIO[28]"] +set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"] +set_property slew "slow" [get_ports "MIO[28]"] +set_property drive "8" [get_ports "MIO[28]"] +set_property pullup "TRUE" [get_ports "MIO[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"] +# GPIO / gpio[27] / MIO[27] +set_property iostandard "LVCMOS33" [get_ports "MIO[27]"] +set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"] +set_property slew "slow" [get_ports "MIO[27]"] +set_property drive "8" [get_ports "MIO[27]"] +set_property pullup "TRUE" [get_ports "MIO[27]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"] +# GPIO / gpio[26] / MIO[26] +set_property iostandard "LVCMOS33" [get_ports "MIO[26]"] +set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"] +set_property slew "slow" [get_ports "MIO[26]"] +set_property drive "8" [get_ports "MIO[26]"] +set_property pullup "TRUE" [get_ports "MIO[26]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"] +# GPIO / gpio[25] / MIO[25] +set_property iostandard "LVCMOS33" [get_ports "MIO[25]"] +set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"] +set_property slew "slow" [get_ports "MIO[25]"] +set_property drive "8" [get_ports "MIO[25]"] +set_property pullup "TRUE" [get_ports "MIO[25]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[25]"] +# GPIO / gpio[24] / MIO[24] +set_property iostandard "LVCMOS33" [get_ports "MIO[24]"] +set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"] +set_property slew "slow" [get_ports "MIO[24]"] +set_property drive "8" [get_ports "MIO[24]"] +set_property pullup "TRUE" [get_ports "MIO[24]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[24]"] +# GPIO / gpio[23] / MIO[23] +set_property iostandard "LVCMOS33" [get_ports "MIO[23]"] +set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"] +set_property slew "slow" [get_ports "MIO[23]"] +set_property drive "8" [get_ports "MIO[23]"] +set_property pullup "TRUE" [get_ports "MIO[23]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"] +# GPIO / gpio[22] / MIO[22] +set_property iostandard "LVCMOS33" [get_ports "MIO[22]"] +set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"] +set_property slew "slow" [get_ports "MIO[22]"] +set_property drive "8" [get_ports "MIO[22]"] +set_property pullup "TRUE" [get_ports "MIO[22]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"] # SPI 0 / mosi / MIO[21] set_property iostandard "LVCMOS33" [get_ports "MIO[21]"] set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] @@ -33,6 +254,20 @@ set_property slew "slow" [get_ports "MIO[21]"] set_property drive "8" [get_ports "MIO[21]"] set_property pullup "TRUE" [get_ports "MIO[21]"] set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"] +# SPI 0 / ss[2] / MIO[20] +set_property iostandard "LVCMOS33" [get_ports "MIO[20]"] +set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"] +set_property slew "slow" [get_ports "MIO[20]"] +set_property drive "8" [get_ports "MIO[20]"] +set_property pullup "TRUE" [get_ports "MIO[20]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"] +# SPI 0 / ss[1] / MIO[19] +set_property iostandard "LVCMOS33" [get_ports "MIO[19]"] +set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"] +set_property slew "slow" [get_ports "MIO[19]"] +set_property drive "8" [get_ports "MIO[19]"] +set_property pullup "TRUE" [get_ports "MIO[19]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"] # SPI 0 / ss[0] / MIO[18] set_property iostandard "LVCMOS33" [get_ports "MIO[18]"] set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] @@ -54,6 +289,20 @@ set_property slew "slow" [get_ports "MIO[16]"] set_property drive "8" [get_ports "MIO[16]"] set_property pullup "TRUE" [get_ports "MIO[16]"] set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"] +# GPIO / gpio[15] / MIO[15] +set_property iostandard "LVCMOS33" [get_ports "MIO[15]"] +set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"] +set_property slew "slow" [get_ports "MIO[15]"] +set_property drive "8" [get_ports "MIO[15]"] +set_property pullup "TRUE" [get_ports "MIO[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"] +# GPIO / gpio[14] / MIO[14] +set_property iostandard "LVCMOS33" [get_ports "MIO[14]"] +set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"] +set_property slew "slow" [get_ports "MIO[14]"] +set_property drive "8" [get_ports "MIO[14]"] +set_property pullup "TRUE" [get_ports "MIO[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"] # UART 1 / rx / MIO[13] set_property iostandard "LVCMOS33" [get_ports "MIO[13]"] set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] @@ -68,6 +317,83 @@ set_property slew "slow" [get_ports "MIO[12]"] set_property drive "8" [get_ports "MIO[12]"] set_property pullup "TRUE" [get_ports "MIO[12]"] set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[12]"] +# GPIO / gpio[11] / MIO[11] +set_property iostandard "LVCMOS33" [get_ports "MIO[11]"] +set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"] +set_property slew "slow" [get_ports "MIO[11]"] +set_property drive "8" [get_ports "MIO[11]"] +set_property pullup "TRUE" [get_ports "MIO[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"] +# GPIO / gpio[10] / MIO[10] +set_property iostandard "LVCMOS33" [get_ports "MIO[10]"] +set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"] +set_property slew "slow" [get_ports "MIO[10]"] +set_property drive "8" [get_ports "MIO[10]"] +set_property pullup "TRUE" [get_ports "MIO[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"] +# GPIO / gpio[9] / MIO[9] +set_property iostandard "LVCMOS33" [get_ports "MIO[9]"] +set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"] +set_property slew "slow" [get_ports "MIO[9]"] +set_property drive "8" [get_ports "MIO[9]"] +set_property pullup "TRUE" [get_ports "MIO[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"] +# GPIO / gpio[8] / MIO[8] +set_property iostandard "LVCMOS33" [get_ports "MIO[8]"] +set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"] +set_property slew "slow" [get_ports "MIO[8]"] +set_property drive "8" [get_ports "MIO[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"] +# GPIO / gpio[7] / MIO[7] +set_property iostandard "LVCMOS33" [get_ports "MIO[7]"] +set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"] +set_property slew "slow" [get_ports "MIO[7]"] +set_property drive "8" [get_ports "MIO[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"] +# GPIO / gpio[6] / MIO[6] +set_property iostandard "LVCMOS33" [get_ports "MIO[6]"] +set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"] +set_property slew "slow" [get_ports "MIO[6]"] +set_property drive "8" [get_ports "MIO[6]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[6]"] +# GPIO / gpio[5] / MIO[5] +set_property iostandard "LVCMOS33" [get_ports "MIO[5]"] +set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"] +set_property slew "slow" [get_ports "MIO[5]"] +set_property drive "8" [get_ports "MIO[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"] +# GPIO / gpio[4] / MIO[4] +set_property iostandard "LVCMOS33" [get_ports "MIO[4]"] +set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"] +set_property slew "slow" [get_ports "MIO[4]"] +set_property drive "8" [get_ports "MIO[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"] +# GPIO / gpio[3] / MIO[3] +set_property iostandard "LVCMOS33" [get_ports "MIO[3]"] +set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"] +set_property slew "slow" [get_ports "MIO[3]"] +set_property drive "8" [get_ports "MIO[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"] +# GPIO / gpio[2] / MIO[2] +set_property iostandard "LVCMOS33" [get_ports "MIO[2]"] +set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"] +set_property slew "slow" [get_ports "MIO[2]"] +set_property drive "8" [get_ports "MIO[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"] +# GPIO / gpio[1] / MIO[1] +set_property iostandard "LVCMOS33" [get_ports "MIO[1]"] +set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"] +set_property slew "slow" [get_ports "MIO[1]"] +set_property drive "8" [get_ports "MIO[1]"] +set_property pullup "TRUE" [get_ports "MIO[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[1]"] +# GPIO / gpio[0] / MIO[0] +set_property iostandard "LVCMOS33" [get_ports "MIO[0]"] +set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"] +set_property slew "slow" [get_ports "MIO[0]"] +set_property drive "8" [get_ports "MIO[0]"] +set_property pullup "TRUE" [get_ports "MIO[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"] set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"] set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] set_property slew "FAST" [get_ports "DDR_VRP"] diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml index 6b1d2ca..d7549ed 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml @@ -9107,7 +9107,7 @@ FREQ_HZ - 50000000 + 1e+07 FREQ_TOLERANCE_HZ @@ -9176,7 +9176,7 @@ - true + false @@ -9199,7 +9199,7 @@ FREQ_HZ - 10000000 + 1e+07 FREQ_TOLERANCE_HZ @@ -9291,7 +9291,7 @@ FREQ_HZ - 10000000 + 1e+07 FREQ_TOLERANCE_HZ @@ -9383,7 +9383,7 @@ FREQ_HZ - 10000000 + 1e+07 FREQ_TOLERANCE_HZ @@ -9495,7 +9495,7 @@ - true + false @@ -15197,11 +15197,11 @@ GENtimestamp - Sun Oct 20 13:34:22 UTC 2024 + Thu Oct 24 17:46:56 UTC 2024 outputProductCRC - 9:6da19851 + 9:5a5e7e00 @@ -15212,7 +15212,7 @@ outputProductCRC - 9:6da19851 + 9:5a5e7e00 @@ -15228,11 +15228,11 @@ GENtimestamp - Sun Oct 20 13:34:22 UTC 2024 + Thu Oct 24 17:46:56 UTC 2024 outputProductCRC - 9:6da19851 + 9:5a5e7e00 @@ -15253,7 +15253,7 @@ outputProductCRC - 9:9d08a276 + 9:44e5a984 @@ -15269,11 +15269,11 @@ GENtimestamp - Sun Oct 20 13:34:23 UTC 2024 + Thu Oct 24 17:46:56 UTC 2024 outputProductCRC - 9:d40e219b + 9:44e5a984 sim_type @@ -15292,11 +15292,11 @@ GENtimestamp - Sun Oct 20 13:34:23 UTC 2024 + Thu Oct 24 17:46:56 UTC 2024 outputProductCRC - 9:9d08a276 + 9:44e5a984 sim_type @@ -15315,11 +15315,11 @@ GENtimestamp - Sun Oct 20 13:34:23 UTC 2024 + Thu Oct 24 17:46:57 UTC 2024 outputProductCRC - 9:9d08a276 + 9:44e5a984 @@ -15335,11 +15335,11 @@ GENtimestamp - Sun Oct 20 13:34:23 UTC 2024 + Thu Oct 24 17:46:57 UTC 2024 outputProductCRC - 9:d40e219b + 9:44e5a984 sim_type @@ -15358,11 +15358,11 @@ GENtimestamp - Sun Oct 20 13:34:24 UTC 2024 + Thu Oct 24 17:46:58 UTC 2024 outputProductCRC - 9:9d08a276 + 9:44e5a984 sim_type @@ -15380,11 +15380,11 @@ GENtimestamp - Sun Oct 20 13:35:16 UTC 2024 + Thu Oct 24 17:47:57 UTC 2024 outputProductCRC - 9:6da19851 + 9:5a5e7e00 @@ -29711,7 +29711,7 @@ - true + false @@ -29883,7 +29883,7 @@ - true + false @@ -32143,7 +32143,7 @@ C_FCLK_CLK0_BUF - TRUE + FALSE C_FCLK_CLK1_BUF @@ -32188,6 +32188,10 @@ 7 8 + + choice_list_0d5ddc26 + MIO 20 + choice_list_0d7de060 ARM PLL @@ -32228,11 +32232,6 @@ MIO 30 .. 31 MIO 42 .. 43 - - choice_list_1e4fa2cf - <Select> - MIO - choice_list_2091a159 <Select> @@ -32349,11 +32348,6 @@ MIO 50 MIO 52 - - choice_list_3e08ea62 - <Select> - MIO 19 - choice_list_3f5f808e LVCMOS 3.3V @@ -32361,12 +32355,6 @@ HSTL 1.8V LVCMOS 1.8V - - choice_list_422ff54b - <Select> - fast - slow - choice_list_45a0fd9c <Select> @@ -32384,11 +32372,6 @@ 0x00100000 0x00040000 - - choice_list_4a3b26eb - <Select> - MIO 20 - choice_list_4d36a164 <Select> @@ -32396,13 +32379,6 @@ Medium High - - choice_list_56c426e3 - <Select> - in - out - inout - choice_list_56e9f994 <Select> @@ -32564,6 +32540,10 @@ MIO 52 MIO 53 + + choice_list_6a48f1e0 + MIO + choice_list_6bc4d474 LVCMOS 3.3V @@ -32573,11 +32553,6 @@ Active High Active Low - - choice_list_7275faaa - <Select> - LVCMOS 3.3V - choice_list_72f3e128 LVCMOS 1.8V @@ -32589,6 +32564,10 @@ choice_list_767f870c External + + choice_list_796e10af + MIO 19 + choice_list_7abc2131 16 Bit @@ -33033,12 +33012,6 @@ 16 32 - - choice_list_ce8c471b - <Select> - disabled - enabled - choice_list_d0304fb3 0xE0009000 @@ -33859,7 +33832,7 @@ - false + true @@ -33871,7 +33844,7 @@ - false + true @@ -34071,11 +34044,11 @@ PCW_FCLK_CLK0_BUF PCW FCLK CLK0 BUF - TRUE + FALSE - true + false @@ -34119,7 +34092,7 @@ PCW_UIPARAM_DDR_FREQ_MHZ PCW UIPARAM DDR FREQ MHZ - 533.333333 + 350 PCW_UIPARAM_DDR_BANK_ADDR_COUNT @@ -34519,7 +34492,7 @@ PCW_APU_PERIPHERAL_FREQMHZ PCW APU PERIPHERAL FREQMHZ - 666.666666 + 400 PCW_DCI_PERIPHERAL_FREQMHZ @@ -34780,17 +34753,17 @@ PCW_ACT_APU_PERIPHERAL_FREQMHZ PCW ACT APU PERIPHERAL FREQMHZ - 666.666687 + 400.000000 PCW_UIPARAM_ACT_DDR_FREQ_MHZ PCW UIPARAM ACT DDR FREQ MHZ - 533.333374 + 350.000000 PCW_ACT_DCI_PERIPHERAL_FREQMHZ PCW ACT DCI PERIPHERAL FREQMHZ - 10.158730 + 10.144927 PCW_ACT_QSPI_PERIPHERAL_FREQMHZ @@ -34860,7 +34833,7 @@ PCW_ACT_WDT_PERIPHERAL_FREQMHZ PCW ACT WDT PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC_PERIPHERAL_FREQMHZ @@ -34880,7 +34853,7 @@ PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ PCW ACT FPGA0 PERIPHERAL FREQMHZ - 50.000000 + 10.000000 PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ @@ -34900,37 +34873,37 @@ PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ - 111.111115 + 66.666672 PCW_CLK0_FREQ PCW CLK0 FREQ - 50000000 + 10000000 PCW_CLK1_FREQ @@ -34955,7 +34928,7 @@ PCW_CPU_PERIPHERAL_DIVISOR0 CLKPARAM - 2 + 4 @@ -34967,7 +34940,7 @@ PCW_DDR_PERIPHERAL_DIVISOR0 CLKPARAM - 2 + 4 @@ -35063,7 +35036,7 @@ PCW_FCLK0_PERIPHERAL_DIVISOR0 CLKPARAM - 5 + 1 @@ -35111,7 +35084,7 @@ PCW_FCLK0_PERIPHERAL_DIVISOR1 CLKPARAM - 4 + 1 @@ -35219,7 +35192,7 @@ PCW_DCI_PERIPHERAL_DIVISOR0 CLKPARAM - 15 + 46 @@ -35231,7 +35204,7 @@ PCW_DCI_PERIPHERAL_DIVISOR1 CLKPARAM - 7 + 3 @@ -35290,7 +35263,7 @@ PCW_ARMPLL_CTRL_FBDIV CLKPARAM - 40 + 48 @@ -35314,7 +35287,7 @@ PCW_DDRPLL_CTRL_FBDIV CLKPARAM - 32 + 42 @@ -35326,7 +35299,7 @@ PCW_CPU_CPU_PLL_FREQMHZ CLKPARAM - 1333.333 + 1600.000 @@ -35350,7 +35323,7 @@ PCW_DDR_DDR_PLL_FREQMHZ CLKPARAM - 1066.667 + 1400.000 @@ -36302,7 +36275,7 @@ PCW_EN_GPIO PCW EN GPIO - 0 + 1 PCW_EN_I2C0 @@ -36412,7 +36385,7 @@ PCW_EN_CLK0_PORT PCW EN CLK0 PORT - 1 + 0 @@ -36461,7 +36434,7 @@ PCW_EN_RST0_PORT PCW EN RST0 PORT Enables general purpose reset signal 0 for PL logic - 1 + 0 @@ -38049,12 +38022,12 @@ PCW_SPI0_GRP_SS1_ENABLE - 0 + 1 PCW_SPI0_GRP_SS1_IO PCW SPI0 GRP SS1 IO - <Select> + MIO 19 @@ -38065,12 +38038,12 @@ PCW_SPI0_GRP_SS2_ENABLE - 0 + 1 PCW_SPI0_GRP_SS2_IO PCW SPI0 GRP SS2 IO - <Select> + MIO 20 @@ -38470,13 +38443,6 @@ PCW_USB_RESET_ENABLE 0 - - - - false - - - PCW_USB_RESET_SELECT @@ -38655,13 +38621,6 @@ PCW_I2C_RESET_ENABLE 0 - - - - false - - - PCW_I2C_RESET_SELECT @@ -38703,19 +38662,12 @@ PCW_GPIO_MIO_GPIO_ENABLE - 0 + 1 PCW_GPIO_MIO_GPIO_IO PCW GPIO MIO GPIO IO - <Select> - - - - false - - - + MIO PCW_GPIO_EMIO_GPIO_ENABLE @@ -38911,31 +38863,17 @@ PCW_MIO_0_PULLUP PCW MIO 0 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_0_IOTYPE PCW MIO 0 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_0_DIRECTION PCW MIO 0 DIRECTION - <Select> + inout @@ -38947,43 +38885,22 @@ PCW_MIO_0_SLEW PCW MIO 0 SLEW - <Select> - - - - false - - - + slow PCW_MIO_1_PULLUP PCW MIO 1 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_1_IOTYPE PCW MIO 1 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_1_DIRECTION PCW MIO 1 DIRECTION - <Select> + inout @@ -38995,19 +38912,12 @@ PCW_MIO_1_SLEW PCW MIO 1 SLEW - <Select> - - - - false - - - + slow PCW_MIO_2_PULLUP PCW MIO 2 PULLUP - <Select> + disabled @@ -39019,19 +38929,12 @@ PCW_MIO_2_IOTYPE PCW MIO 2 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_2_DIRECTION PCW MIO 2 DIRECTION - <Select> + inout @@ -39043,19 +38946,12 @@ PCW_MIO_2_SLEW PCW MIO 2 SLEW - <Select> - - - - false - - - + slow PCW_MIO_3_PULLUP PCW MIO 3 PULLUP - <Select> + disabled @@ -39067,19 +38963,12 @@ PCW_MIO_3_IOTYPE PCW MIO 3 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_3_DIRECTION PCW MIO 3 DIRECTION - <Select> + inout @@ -39091,19 +38980,12 @@ PCW_MIO_3_SLEW PCW MIO 3 SLEW - <Select> - - - - false - - - + slow PCW_MIO_4_PULLUP PCW MIO 4 PULLUP - <Select> + disabled @@ -39115,19 +38997,12 @@ PCW_MIO_4_IOTYPE PCW MIO 4 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_4_DIRECTION PCW MIO 4 DIRECTION - <Select> + inout @@ -39139,19 +39014,12 @@ PCW_MIO_4_SLEW PCW MIO 4 SLEW - <Select> - - - - false - - - + slow PCW_MIO_5_PULLUP PCW MIO 5 PULLUP - <Select> + disabled @@ -39163,19 +39031,12 @@ PCW_MIO_5_IOTYPE PCW MIO 5 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_5_DIRECTION PCW MIO 5 DIRECTION - <Select> + inout @@ -39187,19 +39048,12 @@ PCW_MIO_5_SLEW PCW MIO 5 SLEW - <Select> - - - - false - - - + slow PCW_MIO_6_PULLUP PCW MIO 6 PULLUP - <Select> + disabled @@ -39211,19 +39065,12 @@ PCW_MIO_6_IOTYPE PCW MIO 6 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_6_DIRECTION PCW MIO 6 DIRECTION - <Select> + inout @@ -39235,19 +39082,12 @@ PCW_MIO_6_SLEW PCW MIO 6 SLEW - <Select> - - - - false - - - + slow PCW_MIO_7_PULLUP PCW MIO 7 PULLUP - <Select> + disabled @@ -39259,19 +39099,12 @@ PCW_MIO_7_IOTYPE PCW MIO 7 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_7_DIRECTION PCW MIO 7 DIRECTION - <Select> + out @@ -39283,19 +39116,12 @@ PCW_MIO_7_SLEW PCW MIO 7 SLEW - <Select> - - - - false - - - + slow PCW_MIO_8_PULLUP PCW MIO 8 PULLUP - <Select> + disabled @@ -39307,19 +39133,12 @@ PCW_MIO_8_IOTYPE PCW MIO 8 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_8_DIRECTION PCW MIO 8 DIRECTION - <Select> + out @@ -39331,43 +39150,22 @@ PCW_MIO_8_SLEW PCW MIO 8 SLEW - <Select> - - - - false - - - + slow PCW_MIO_9_PULLUP PCW MIO 9 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_9_IOTYPE PCW MIO 9 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_9_DIRECTION PCW MIO 9 DIRECTION - <Select> + inout @@ -39379,43 +39177,22 @@ PCW_MIO_9_SLEW PCW MIO 9 SLEW - <Select> - - - - false - - - + slow PCW_MIO_10_PULLUP PCW MIO 10 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_10_IOTYPE PCW MIO 10 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_10_DIRECTION PCW MIO 10 DIRECTION - <Select> + inout @@ -39427,43 +39204,22 @@ PCW_MIO_10_SLEW PCW MIO 10 SLEW - <Select> - - - - false - - - + slow PCW_MIO_11_PULLUP PCW MIO 11 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_11_IOTYPE PCW MIO 11 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_11_DIRECTION PCW MIO 11 DIRECTION - <Select> + inout @@ -39475,14 +39231,7 @@ PCW_MIO_11_SLEW PCW MIO 11 SLEW - <Select> - - - - false - - - + slow PCW_MIO_12_PULLUP @@ -39541,31 +39290,17 @@ PCW_MIO_14_PULLUP PCW MIO 14 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_14_IOTYPE PCW MIO 14 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_14_DIRECTION PCW MIO 14 DIRECTION - <Select> + inout @@ -39577,43 +39312,22 @@ PCW_MIO_14_SLEW PCW MIO 14 SLEW - <Select> - - - - false - - - + slow PCW_MIO_15_PULLUP PCW MIO 15 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_15_IOTYPE PCW MIO 15 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_15_DIRECTION PCW MIO 15 DIRECTION - <Select> + inout @@ -39625,14 +39339,7 @@ PCW_MIO_15_SLEW PCW MIO 15 SLEW - <Select> - - - - false - - - + slow PCW_MIO_16_PULLUP @@ -39718,31 +39425,17 @@ PCW_MIO_19_PULLUP PCW MIO 19 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_19_IOTYPE PCW MIO 19 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_19_DIRECTION PCW MIO 19 DIRECTION - <Select> + out @@ -39754,43 +39447,22 @@ PCW_MIO_19_SLEW PCW MIO 19 SLEW - <Select> - - - - false - - - + slow PCW_MIO_20_PULLUP PCW MIO 20 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_20_IOTYPE PCW MIO 20 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_20_DIRECTION PCW MIO 20 DIRECTION - <Select> + out @@ -39802,14 +39474,7 @@ PCW_MIO_20_SLEW PCW MIO 20 SLEW - <Select> - - - - false - - - + slow PCW_MIO_21_PULLUP @@ -39841,31 +39506,17 @@ PCW_MIO_22_PULLUP PCW MIO 22 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_22_IOTYPE PCW MIO 22 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_22_DIRECTION PCW MIO 22 DIRECTION - <Select> + inout @@ -39877,43 +39528,22 @@ PCW_MIO_22_SLEW PCW MIO 22 SLEW - <Select> - - - - false - - - + slow PCW_MIO_23_PULLUP PCW MIO 23 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_23_IOTYPE PCW MIO 23 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_23_DIRECTION PCW MIO 23 DIRECTION - <Select> + inout @@ -39925,43 +39555,22 @@ PCW_MIO_23_SLEW PCW MIO 23 SLEW - <Select> - - - - false - - - + slow PCW_MIO_24_PULLUP PCW MIO 24 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_24_IOTYPE PCW MIO 24 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_24_DIRECTION PCW MIO 24 DIRECTION - <Select> + inout @@ -39973,43 +39582,22 @@ PCW_MIO_24_SLEW PCW MIO 24 SLEW - <Select> - - - - false - - - + slow PCW_MIO_25_PULLUP PCW MIO 25 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_25_IOTYPE PCW MIO 25 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_25_DIRECTION PCW MIO 25 DIRECTION - <Select> + inout @@ -40021,43 +39609,22 @@ PCW_MIO_25_SLEW PCW MIO 25 SLEW - <Select> - - - - false - - - + slow PCW_MIO_26_PULLUP PCW MIO 26 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_26_IOTYPE PCW MIO 26 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_26_DIRECTION PCW MIO 26 DIRECTION - <Select> + inout @@ -40069,43 +39636,22 @@ PCW_MIO_26_SLEW PCW MIO 26 SLEW - <Select> - - - - false - - - + slow PCW_MIO_27_PULLUP PCW MIO 27 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_27_IOTYPE PCW MIO 27 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_27_DIRECTION PCW MIO 27 DIRECTION - <Select> + inout @@ -40117,43 +39663,22 @@ PCW_MIO_27_SLEW PCW MIO 27 SLEW - <Select> - - - - false - - - + slow PCW_MIO_28_PULLUP PCW MIO 28 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_28_IOTYPE PCW MIO 28 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_28_DIRECTION PCW MIO 28 DIRECTION - <Select> + inout @@ -40165,43 +39690,22 @@ PCW_MIO_28_SLEW PCW MIO 28 SLEW - <Select> - - - - false - - - + slow PCW_MIO_29_PULLUP PCW MIO 29 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_29_IOTYPE PCW MIO 29 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_29_DIRECTION PCW MIO 29 DIRECTION - <Select> + inout @@ -40213,43 +39717,22 @@ PCW_MIO_29_SLEW PCW MIO 29 SLEW - <Select> - - - - false - - - + slow PCW_MIO_30_PULLUP PCW MIO 30 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_30_IOTYPE PCW MIO 30 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_30_DIRECTION PCW MIO 30 DIRECTION - <Select> + inout @@ -40261,43 +39744,22 @@ PCW_MIO_30_SLEW PCW MIO 30 SLEW - <Select> - - - - false - - - + slow PCW_MIO_31_PULLUP PCW MIO 31 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_31_IOTYPE PCW MIO 31 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_31_DIRECTION PCW MIO 31 DIRECTION - <Select> + inout @@ -40309,43 +39771,22 @@ PCW_MIO_31_SLEW PCW MIO 31 SLEW - <Select> - - - - false - - - + slow PCW_MIO_32_PULLUP PCW MIO 32 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_32_IOTYPE PCW MIO 32 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_32_DIRECTION PCW MIO 32 DIRECTION - <Select> + inout @@ -40357,43 +39798,22 @@ PCW_MIO_32_SLEW PCW MIO 32 SLEW - <Select> - - - - false - - - + slow PCW_MIO_33_PULLUP PCW MIO 33 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_33_IOTYPE PCW MIO 33 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_33_DIRECTION PCW MIO 33 DIRECTION - <Select> + inout @@ -40405,43 +39825,22 @@ PCW_MIO_33_SLEW PCW MIO 33 SLEW - <Select> - - - - false - - - + slow PCW_MIO_34_PULLUP PCW MIO 34 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_34_IOTYPE PCW MIO 34 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_34_DIRECTION PCW MIO 34 DIRECTION - <Select> + inout @@ -40453,43 +39852,22 @@ PCW_MIO_34_SLEW PCW MIO 34 SLEW - <Select> - - - - false - - - + slow PCW_MIO_35_PULLUP PCW MIO 35 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_35_IOTYPE PCW MIO 35 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_35_DIRECTION PCW MIO 35 DIRECTION - <Select> + inout @@ -40501,43 +39879,22 @@ PCW_MIO_35_SLEW PCW MIO 35 SLEW - <Select> - - - - false - - - + slow PCW_MIO_36_PULLUP PCW MIO 36 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_36_IOTYPE PCW MIO 36 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_36_DIRECTION PCW MIO 36 DIRECTION - <Select> + inout @@ -40549,43 +39906,22 @@ PCW_MIO_36_SLEW PCW MIO 36 SLEW - <Select> - - - - false - - - + slow PCW_MIO_37_PULLUP PCW MIO 37 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_37_IOTYPE PCW MIO 37 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_37_DIRECTION PCW MIO 37 DIRECTION - <Select> + inout @@ -40597,43 +39933,22 @@ PCW_MIO_37_SLEW PCW MIO 37 SLEW - <Select> - - - - false - - - + slow PCW_MIO_38_PULLUP PCW MIO 38 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_38_IOTYPE PCW MIO 38 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_38_DIRECTION PCW MIO 38 DIRECTION - <Select> + inout @@ -40645,43 +39960,22 @@ PCW_MIO_38_SLEW PCW MIO 38 SLEW - <Select> - - - - false - - - + slow PCW_MIO_39_PULLUP PCW MIO 39 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_39_IOTYPE PCW MIO 39 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_39_DIRECTION PCW MIO 39 DIRECTION - <Select> + inout @@ -40693,43 +39987,22 @@ PCW_MIO_39_SLEW PCW MIO 39 SLEW - <Select> - - - - false - - - + slow PCW_MIO_40_PULLUP PCW MIO 40 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_40_IOTYPE PCW MIO 40 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_40_DIRECTION PCW MIO 40 DIRECTION - <Select> + inout @@ -40741,43 +40014,22 @@ PCW_MIO_40_SLEW PCW MIO 40 SLEW - <Select> - - - - false - - - + slow PCW_MIO_41_PULLUP PCW MIO 41 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_41_IOTYPE PCW MIO 41 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_41_DIRECTION PCW MIO 41 DIRECTION - <Select> + inout @@ -40789,43 +40041,22 @@ PCW_MIO_41_SLEW PCW MIO 41 SLEW - <Select> - - - - false - - - + slow PCW_MIO_42_PULLUP PCW MIO 42 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_42_IOTYPE PCW MIO 42 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_42_DIRECTION PCW MIO 42 DIRECTION - <Select> + inout @@ -40837,43 +40068,22 @@ PCW_MIO_42_SLEW PCW MIO 42 SLEW - <Select> - - - - false - - - + slow PCW_MIO_43_PULLUP PCW MIO 43 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_43_IOTYPE PCW MIO 43 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_43_DIRECTION PCW MIO 43 DIRECTION - <Select> + inout @@ -40885,43 +40095,22 @@ PCW_MIO_43_SLEW PCW MIO 43 SLEW - <Select> - - - - false - - - + slow PCW_MIO_44_PULLUP PCW MIO 44 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_44_IOTYPE PCW MIO 44 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_44_DIRECTION PCW MIO 44 DIRECTION - <Select> + inout @@ -40933,43 +40122,22 @@ PCW_MIO_44_SLEW PCW MIO 44 SLEW - <Select> - - - - false - - - + slow PCW_MIO_45_PULLUP PCW MIO 45 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_45_IOTYPE PCW MIO 45 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_45_DIRECTION PCW MIO 45 DIRECTION - <Select> + inout @@ -40981,43 +40149,22 @@ PCW_MIO_45_SLEW PCW MIO 45 SLEW - <Select> - - - - false - - - + slow PCW_MIO_46_PULLUP PCW MIO 46 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_46_IOTYPE PCW MIO 46 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_46_DIRECTION PCW MIO 46 DIRECTION - <Select> + inout @@ -41029,43 +40176,22 @@ PCW_MIO_46_SLEW PCW MIO 46 SLEW - <Select> - - - - false - - - + slow PCW_MIO_47_PULLUP PCW MIO 47 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_47_IOTYPE PCW MIO 47 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_47_DIRECTION PCW MIO 47 DIRECTION - <Select> + inout @@ -41077,43 +40203,22 @@ PCW_MIO_47_SLEW PCW MIO 47 SLEW - <Select> - - - - false - - - + slow PCW_MIO_48_PULLUP PCW MIO 48 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_48_IOTYPE PCW MIO 48 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_48_DIRECTION PCW MIO 48 DIRECTION - <Select> + inout @@ -41125,43 +40230,22 @@ PCW_MIO_48_SLEW PCW MIO 48 SLEW - <Select> - - - - false - - - + slow PCW_MIO_49_PULLUP PCW MIO 49 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_49_IOTYPE PCW MIO 49 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_49_DIRECTION PCW MIO 49 DIRECTION - <Select> + inout @@ -41173,43 +40257,22 @@ PCW_MIO_49_SLEW PCW MIO 49 SLEW - <Select> - - - - false - - - + slow PCW_MIO_50_PULLUP PCW MIO 50 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_50_IOTYPE PCW MIO 50 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_50_DIRECTION PCW MIO 50 DIRECTION - <Select> + inout @@ -41221,43 +40284,22 @@ PCW_MIO_50_SLEW PCW MIO 50 SLEW - <Select> - - - - false - - - + slow PCW_MIO_51_PULLUP PCW MIO 51 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_51_IOTYPE PCW MIO 51 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_51_DIRECTION PCW MIO 51 DIRECTION - <Select> + inout @@ -41269,43 +40311,22 @@ PCW_MIO_51_SLEW PCW MIO 51 SLEW - <Select> - - - - false - - - + slow PCW_MIO_52_PULLUP PCW MIO 52 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_52_IOTYPE PCW MIO 52 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_52_DIRECTION PCW MIO 52 DIRECTION - <Select> + inout @@ -41317,43 +40338,22 @@ PCW_MIO_52_SLEW PCW MIO 52 SLEW - <Select> - - - - false - - - + slow PCW_MIO_53_PULLUP PCW MIO 53 PULLUP - <Select> - - - - false - - - + enabled PCW_MIO_53_IOTYPE PCW MIO 53 IOTYPE - <Select> - - - - false - - - + LVCMOS 3.3V PCW_MIO_53_DIRECTION PCW MIO 53 DIRECTION - <Select> + inout @@ -41365,14 +40365,7 @@ PCW_MIO_53_SLEW PCW MIO 53 SLEW - <Select> - - - - false - - - + slow preset @@ -41387,14 +40380,12 @@ PCW_MIO_TREE_PERIPHERALS PCW MIO TREE PERIPHERALS - unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#SPI 0#SPI 0#SPI 0#unassigned#unassigned#SPI 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned# -unassigned#unassigned#unassigned#unassigned#unassigned#unassigned + GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO PCW_MIO_TREE_SIGNALS PCW MIO TREE SIGNALS - unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#sclk#miso#ss[0]#unassigned#unassigned#mosi#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned# -unassigned#unassigned#unassigned#unassigned#unassigned + gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#tx#rx#gpio[14]#gpio[15]#sclk#miso#ss[0]#ss[1]#ss[2]#mosi#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53] PCW_PS7_SI_REV @@ -41404,11 +40395,11 @@ unassigned#unassigned#unassigned#unassigned#unassigned PCW_FPGA_FCLK0_ENABLE PCW FPGA FCLK0 ENABLE - 1 + 0 - true + false @@ -41768,6 +40759,7 @@ unassigned#unassigned#unassigned#unassigned#unassigned + @@ -41785,10 +40777,17 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + + + + + + @@ -41800,13 +40799,34 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + + + + + + + + + + + + + + + + + + + + @@ -41815,6 +40835,14 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + + + + + + + @@ -41827,10 +40855,182 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -41843,7 +41043,9 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + @@ -41874,6 +41076,7 @@ unassigned#unassigned#unassigned#unassigned#unassigned + @@ -41882,6 +41085,9 @@ unassigned#unassigned#unassigned#unassigned#unassigned + + + diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v index fa2289e..7d88859 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -// Date : Sun Oct 20 21:35:16 2024 +// Date : Fri Oct 25 01:47:57 2024 // Host : destop1 running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim // d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v @@ -15,9 +15,7 @@ (* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *) (* NotValidForBitStream *) module design_1_processing_system7_0_0 - (FCLK_CLK0, - FCLK_RESET0_N, - MIO, + (MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, @@ -38,8 +36,6 @@ module design_1_processing_system7_0_0 PS_SRSTB, PS_CLK, PS_PORB); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; @@ -79,8 +75,6 @@ module design_1_processing_system7_0_0 wire DDR_VRN; wire DDR_VRP; wire DDR_WEB; - wire FCLK_CLK0; - wire FCLK_RESET0_N; wire [53:0]MIO; wire PS_CLK; wire PS_PORB; @@ -130,9 +124,11 @@ module design_1_processing_system7_0_0 wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; wire NLW_inst_EVENT_EVENTO_UNCONNECTED; + wire NLW_inst_FCLK_CLK0_UNCONNECTED; wire NLW_inst_FCLK_CLK1_UNCONNECTED; wire NLW_inst_FCLK_CLK2_UNCONNECTED; wire NLW_inst_FCLK_CLK3_UNCONNECTED; + wire NLW_inst_FCLK_RESET0_N_UNCONNECTED; wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; @@ -414,7 +410,7 @@ module design_1_processing_system7_0_0 (* C_EN_EMIO_ENET1 = "0" *) (* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) - (* C_FCLK_CLK0_BUF = "TRUE" *) + (* C_FCLK_CLK0_BUF = "FALSE" *) (* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) @@ -462,7 +458,7 @@ module design_1_processing_system7_0_0 (* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) - (* POWER = "/>" *) + (* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst (.CAN0_PHY_RX(1'b0), @@ -581,7 +577,7 @@ module design_1_processing_system7_0_0 .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), - .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK0(NLW_inst_FCLK_CLK0_UNCONNECTED), .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED), .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED), .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED), @@ -589,7 +585,7 @@ module design_1_processing_system7_0_0 .FCLK_CLKTRIG1_N(1'b0), .FCLK_CLKTRIG2_N(1'b0), .FCLK_CLKTRIG3_N(1'b0), - .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET0_N(NLW_inst_FCLK_RESET0_N_UNCONNECTED), .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), @@ -1154,7 +1150,7 @@ endmodule (* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *) (* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) -(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) +(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "FALSE" *) (* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) (* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) (* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *) @@ -1171,7 +1167,7 @@ endmodule (* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) (* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *) -(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 (CAN0_PHY_TX, CAN0_PHY_RX, @@ -2564,9 +2560,6 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system wire DDR_WEB; wire ENET0_MDIO_T_n; wire ENET1_MDIO_T_n; - wire FCLK_CLK0; - wire [0:0]FCLK_CLK_unbuffered; - wire FCLK_RESET0_N; wire I2C0_SCL_T_n; wire I2C0_SDA_T_n; wire I2C1_SCL_T_n; @@ -3575,10 +3568,12 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system wire PS7_i_n_705; wire PS7_i_n_706; wire PS7_i_n_707; + wire PS7_i_n_708; wire PS7_i_n_709; wire PS7_i_n_71; wire PS7_i_n_710; wire PS7_i_n_711; + wire PS7_i_n_712; wire PS7_i_n_713; wire PS7_i_n_714; wire PS7_i_n_715; @@ -3965,9 +3960,11 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system assign EVENT_STANDBYWFE[0] = \ ; assign EVENT_STANDBYWFI[1] = \ ; assign EVENT_STANDBYWFI[0] = \ ; + assign FCLK_CLK0 = \ ; assign FCLK_CLK1 = \ ; assign FCLK_CLK2 = \ ; assign FCLK_CLK3 = \ ; + assign FCLK_RESET0_N = \ ; assign FCLK_RESET1_N = \ ; assign FCLK_RESET2_N = \ ; assign FCLK_RESET3_N = \ ; @@ -5526,9 +5523,9 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system .EVENTEVENTO(PS7_i_n_88), .EVENTSTANDBYWFE({PS7_i_n_236,PS7_i_n_237}), .EVENTSTANDBYWFI({PS7_i_n_238,PS7_i_n_239}), - .FCLKCLK({PS7_i_n_705,PS7_i_n_706,PS7_i_n_707,FCLK_CLK_unbuffered}), + .FCLKCLK({PS7_i_n_705,PS7_i_n_706,PS7_i_n_707,PS7_i_n_708}), .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), - .FCLKRESETN({PS7_i_n_709,PS7_i_n_710,PS7_i_n_711,FCLK_RESET0_N}), + .FCLKRESETN({PS7_i_n_709,PS7_i_n_710,PS7_i_n_711,PS7_i_n_712}), .FPGAIDLEN(1'b0), .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), .FTMDTRACEINCLOCK(1'b0), @@ -5945,10 +5942,6 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system (.IO(buffered_PS_SRSTB), .PAD(PS_SRSTB)); (* BOX_TYPE = "PRIMITIVE" *) - BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG - (.I(FCLK_CLK_unbuffered), - .O(FCLK_CLK0)); - (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[0].MIO_BIBUF (.IO(buffered_MIO[0]), .PAD(MIO[0])); diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl index 023f8ec..e3be0c1 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 --- Date : Sun Oct 20 21:35:16 2024 +-- Date : Fri Oct 25 01:47:57 2024 -- Host : destop1 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl @@ -719,7 +719,7 @@ entity design_1_processing_system7_0_0_processing_system7_v5_5_processing_system attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; - attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; @@ -817,7 +817,7 @@ entity design_1_processing_system7_0_0_processing_system7_v5_5_processing_system attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7"; attribute POWER : string; - attribute POWER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "/>"; + attribute POWER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; end design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7; @@ -826,7 +826,6 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_ signal \\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; - signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; @@ -1834,10 +1833,12 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_ signal PS7_i_n_705 : STD_LOGIC; signal PS7_i_n_706 : STD_LOGIC; signal PS7_i_n_707 : STD_LOGIC; + signal PS7_i_n_708 : STD_LOGIC; signal PS7_i_n_709 : STD_LOGIC; signal PS7_i_n_71 : STD_LOGIC; signal PS7_i_n_710 : STD_LOGIC; signal PS7_i_n_711 : STD_LOGIC; + signal PS7_i_n_712 : STD_LOGIC; signal PS7_i_n_713 : STD_LOGIC; signal PS7_i_n_714 : STD_LOGIC; signal PS7_i_n_715 : STD_LOGIC; @@ -2180,7 +2181,6 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_ attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; - attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; @@ -2371,9 +2371,11 @@ begin EVENT_STANDBYWFE(0) <= \\; EVENT_STANDBYWFI(1) <= \\; EVENT_STANDBYWFI(0) <= \\; + FCLK_CLK0 <= \\; FCLK_CLK1 <= \\; FCLK_CLK2 <= \\; FCLK_CLK3 <= \\; + FCLK_RESET0_N <= \\; FCLK_RESET1_N <= \\; FCLK_RESET2_N <= \\; FCLK_RESET3_N <= \\; @@ -4037,12 +4039,12 @@ PS7_i: unisim.vcomponents.PS7 FCLKCLK(3) => PS7_i_n_705, FCLKCLK(2) => PS7_i_n_706, FCLKCLK(1) => PS7_i_n_707, - FCLKCLK(0) => FCLK_CLK_unbuffered(0), + FCLKCLK(0) => PS7_i_n_708, FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => PS7_i_n_709, FCLKRESETN(2) => PS7_i_n_710, FCLKRESETN(1) => PS7_i_n_711, - FCLKRESETN(0) => FCLK_RESET0_N, + FCLKRESETN(0) => PS7_i_n_712, FPGAIDLEN => '0', FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => '0', @@ -5380,11 +5382,6 @@ PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); -\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG - port map ( - I => FCLK_CLK_unbuffered(0), - O => FCLK_CLK0 - ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), @@ -6164,8 +6161,6 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_processing_system7_0_0 is port ( - FCLK_CLK0 : out STD_LOGIC; - FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; @@ -6244,9 +6239,11 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_CLK0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET0_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; @@ -6536,7 +6533,7 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; - attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; + attribute C_FCLK_CLK0_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; @@ -6632,7 +6629,7 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef"; attribute POWER : string; - attribute POWER of inst : label is "/>"; + attribute POWER of inst : label is "/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; @@ -6647,13 +6644,9 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; - attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; - attribute X_INTERFACE_PARAMETER : string; - attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; - attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; @@ -6783,7 +6776,7 @@ inst: entity work.design_1_processing_system7_0_0_processing_system7_v5_5_proces EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), - FCLK_CLK0 => FCLK_CLK0, + FCLK_CLK0 => NLW_inst_FCLK_CLK0_UNCONNECTED, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, @@ -6791,7 +6784,7 @@ inst: entity work.design_1_processing_system7_0_0_processing_system7_v5_5_proces FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', - FCLK_RESET0_N => FCLK_RESET0_N, + FCLK_RESET0_N => NLW_inst_FCLK_RESET0_N_UNCONNECTED, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v index f99ae07..a316aa4 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -// Date : Sun Oct 20 21:35:16 2024 +// Date : Fri Oct 25 01:47:57 2024 // Host : destop1 running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub // d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v @@ -14,12 +14,10 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *) -module design_1_processing_system7_0_0(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, - DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, - DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) -/* synthesis syn_black_box black_box_pad_pin="FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; - output FCLK_CLK0; - output FCLK_RESET0_N; +module design_1_processing_system7_0_0(MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, + DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, + DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) +/* synthesis syn_black_box black_box_pad_pin="MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; inout [53:0]MIO; inout DDR_CAS_n; inout DDR_CKE; diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl index 6d98fdd..03d8857 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 --- Date : Sun Oct 20 21:35:16 2024 +-- Date : Fri Oct 25 01:47:57 2024 -- Host : destop1 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl @@ -14,8 +14,6 @@ use IEEE.STD_LOGIC_1164.ALL; entity design_1_processing_system7_0_0 is Port ( - FCLK_CLK0 : out STD_LOGIC; - FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; @@ -45,7 +43,7 @@ architecture stub of design_1_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; +attribute black_box_pad_pin of stub : architecture is "MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2022.2"; begin diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/design_1_processing_system7_0_0.hwdef b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/design_1_processing_system7_0_0.hwdef index b298e6a..44be097 100644 Binary files a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/design_1_processing_system7_0_0.hwdef and b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/design_1_processing_system7_0_0.hwdef differ diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v index e131e9a..d5535b3 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v @@ -149,13 +149,13 @@ // CR #682573 // Added BIBUF to fixed IO ports and IBUF to fixed input ports //------------------------------------------------------------------------------ -(*POWER= "/>" *) -(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ -, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\ +(*POWER= "/>" *) +(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=350, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ +, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=400, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=48, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=42, PCW_CPU_CPU_PLL_FREQMHZ=1600.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1400.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\ , PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 3.3V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\ -, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=0, PCW_QSPI_GRP_SINGLE_SS_ENABLE=0, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 12 .. 13, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=MIO 16 .. 21, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=MIO 18, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0\ -, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL\ -, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) +, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=0, PCW_QSPI_GRP_SINGLE_SS_ENABLE=0, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 12 .. 13, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=MIO 16 .. 21, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=MIO 18, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=MIO 19, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=MIO 20, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0\ +, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X\ +, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=0, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) module processing_system7_v5_5_processing_system7 diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c index d358599..d8c4994 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c @@ -25,9 +25,9 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -35,13 +35,13 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -81,9 +81,9 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -100,26 +100,26 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -162,14 +162,14 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -254,14 +254,14 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -306,14 +306,14 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -423,9 +423,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reserved_reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -433,7 +433,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006004[18:14] = 0x00000000U // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -467,66 +467,66 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -552,7 +552,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006020[30:30] = 0x00000000U // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -598,20 +598,20 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -619,7 +619,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -821,17 +821,17 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 // .. .. ==> 0XF8006078[11:8] = 0x00000001U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_cksre = 0x5 + // .. .. ==> 0XF8006078[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_t_cksrx = 0x5 + // .. .. ==> 0XF8006078[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U // .. .. reg_ddrc_t_ckesr = 0x4 // .. .. ==> 0XF8006078[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U), // .. .. reg_ddrc_t_ckpde = 0x2 // .. .. ==> 0XF800607C[3:0] = 0x00000002U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U @@ -866,22 +866,22 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -1061,35 +1061,35 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -1178,9 +1178,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1188,10 +1188,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1199,10 +1199,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1210,10 +1210,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1221,7 +1221,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -1478,22 +1478,22 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -1944,6 +1944,354 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2002,6 +2350,64 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2089,6 +2495,64 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2117,6 +2581,934 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B @@ -2458,9 +3850,9 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -2468,13 +3860,13 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -2514,9 +3906,9 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -2533,26 +3925,26 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -2595,14 +3987,14 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -2687,14 +4079,14 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -2739,14 +4131,14 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -2856,9 +4248,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -2881,7 +4273,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006004[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -2915,66 +4307,66 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -3006,7 +4398,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006020[31:31] = 0x00000000U // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3055,20 +4447,20 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -3076,7 +4468,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3314,17 +4706,17 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 // .. .. ==> 0XF8006078[11:8] = 0x00000001U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_cksre = 0x5 + // .. .. ==> 0XF8006078[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_t_cksrx = 0x5 + // .. .. ==> 0XF8006078[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U // .. .. reg_ddrc_t_ckesr = 0x4 // .. .. ==> 0XF8006078[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U), // .. .. reg_ddrc_t_ckpde = 0x2 // .. .. ==> 0XF800607C[3:0] = 0x00000002U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U @@ -3367,22 +4759,22 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -3619,35 +5011,35 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -3736,9 +5128,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3746,10 +5138,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3757,10 +5149,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3768,10 +5160,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3779,7 +5171,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -4063,22 +5455,22 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -4532,6 +5924,354 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4590,6 +6330,64 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4677,6 +6475,64 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4705,6 +6561,934 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B @@ -5044,9 +7828,9 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -5054,13 +7838,13 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -5100,9 +7884,9 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -5119,26 +7903,26 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -5181,14 +7965,14 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -5273,14 +8057,14 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5325,14 +8109,14 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -5442,9 +8226,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -5467,7 +8251,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006004[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -5501,66 +8285,66 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -5592,7 +8376,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006020[31:31] = 0x00000000U // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5641,20 +8425,20 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -5662,7 +8446,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5916,22 +8700,22 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -6141,35 +8925,35 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -6258,9 +9042,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6268,10 +9052,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6279,10 +9063,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6290,10 +9074,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6301,7 +9085,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -6585,22 +9369,22 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -7051,6 +9835,354 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7109,6 +10241,64 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7196,6 +10386,64 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7224,6 +10472,934 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.html b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.html +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 - +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -176,22 +176,22 @@ Xilinx MIO 1 - +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -199,22 +199,22 @@ Xilinx MIO 2 - +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout @@ -222,22 +222,22 @@ Xilinx MIO 3 - +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout @@ -245,22 +245,22 @@ Xilinx MIO 4 - +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout @@ -268,22 +268,22 @@ Xilinx MIO 5 - +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout @@ -291,22 +291,22 @@ Xilinx MIO 6 - +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout @@ -314,22 +314,22 @@ Xilinx MIO 7 - +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out @@ -337,22 +337,22 @@ Xilinx MIO 8 - +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out @@ -360,22 +360,22 @@ Xilinx MIO 9 - +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -383,22 +383,22 @@ Xilinx MIO 10 - +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -406,22 +406,22 @@ Xilinx MIO 11 - +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -475,22 +475,22 @@ in MIO 14 - +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -498,22 +498,22 @@ in MIO 15 - +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -590,22 +590,22 @@ inout MIO 19 - +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out @@ -613,22 +613,22 @@ inout MIO 20 - +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out @@ -659,22 +659,22 @@ inout MIO 22 - +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -682,22 +682,22 @@ inout MIO 23 - +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -705,22 +705,22 @@ inout MIO 24 - +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -728,22 +728,22 @@ inout MIO 25 - +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -751,22 +751,22 @@ inout MIO 26 - +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -774,22 +774,22 @@ inout MIO 27 - +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -797,22 +797,22 @@ inout MIO 28 - +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -820,22 +820,22 @@ inout MIO 29 - +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -843,22 +843,22 @@ inout MIO 30 - +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -866,22 +866,22 @@ inout MIO 31 - +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -889,22 +889,22 @@ inout MIO 32 - +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -912,22 +912,22 @@ inout MIO 33 - +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -935,22 +935,22 @@ inout MIO 34 - +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -958,22 +958,22 @@ inout MIO 35 - +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -981,22 +981,22 @@ inout MIO 36 - +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1004,22 +1004,22 @@ inout MIO 37 - +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1027,22 +1027,22 @@ inout MIO 38 - +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1050,22 +1050,22 @@ inout MIO 39 - +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1073,22 +1073,22 @@ inout MIO 40 - +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1096,22 +1096,22 @@ inout MIO 41 - +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1119,22 +1119,22 @@ inout MIO 42 - +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1142,22 +1142,22 @@ inout MIO 43 - +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1165,22 +1165,22 @@ inout MIO 44 - +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1188,22 +1188,22 @@ inout MIO 45 - +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1211,22 +1211,22 @@ inout MIO 46 - +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1234,22 +1234,22 @@ inout MIO 47 - +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1257,22 +1257,22 @@ inout MIO 48 - +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1280,22 +1280,22 @@ inout MIO 49 - +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1303,22 +1303,22 @@ inout MIO 50 - +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1326,22 +1326,22 @@ inout MIO 51 - +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1349,22 +1349,22 @@ inout MIO 52 - +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1372,22 +1372,22 @@ inout MIO 53 - +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout @@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c index cafd145..aa0abdc 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c @@ -38,9 +38,9 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -48,13 +48,13 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -94,9 +94,9 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -113,26 +113,26 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -175,14 +175,14 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -267,14 +267,14 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -319,14 +319,14 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -436,9 +436,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reserved_reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -446,7 +446,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006004[18:14] = 0x00000000U // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -480,66 +480,66 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -565,7 +565,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006020[30:30] = 0x00000000U // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -611,20 +611,20 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -632,7 +632,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -834,17 +834,17 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 // .. .. ==> 0XF8006078[11:8] = 0x00000001U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_cksre = 0x5 + // .. .. ==> 0XF8006078[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_t_cksrx = 0x5 + // .. .. ==> 0XF8006078[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U // .. .. reg_ddrc_t_ckesr = 0x4 // .. .. ==> 0XF8006078[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U), // .. .. reg_ddrc_t_ckpde = 0x2 // .. .. ==> 0XF800607C[3:0] = 0x00000002U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U @@ -879,22 +879,22 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -1074,35 +1074,35 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -1191,9 +1191,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1201,10 +1201,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1212,10 +1212,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1223,10 +1223,10 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -1234,7 +1234,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -1491,22 +1491,22 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -1957,6 +1957,354 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2015,6 +2363,64 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2102,6 +2508,64 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -2130,6 +2594,934 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B @@ -2471,9 +3863,9 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -2481,13 +3873,13 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -2527,9 +3919,9 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -2546,26 +3938,26 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -2608,14 +4000,14 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -2700,14 +4092,14 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -2752,14 +4144,14 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -2869,9 +4261,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -2894,7 +4286,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006004[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -2928,66 +4320,66 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -3019,7 +4411,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006020[31:31] = 0x00000000U // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3068,20 +4460,20 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -3089,7 +4481,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3327,17 +4719,17 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 // .. .. ==> 0XF8006078[11:8] = 0x00000001U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_cksre = 0x5 + // .. .. ==> 0XF8006078[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_t_cksrx = 0x5 + // .. .. ==> 0XF8006078[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U // .. .. reg_ddrc_t_ckesr = 0x4 // .. .. ==> 0XF8006078[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U), // .. .. reg_ddrc_t_ckpde = 0x2 // .. .. ==> 0XF800607C[3:0] = 0x00000002U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U @@ -3380,22 +4772,22 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -3632,35 +5024,35 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -3749,9 +5141,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3759,10 +5151,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3770,10 +5162,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3781,10 +5173,10 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -3792,7 +5184,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -4076,22 +5468,22 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -4545,6 +5937,354 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4603,6 +6343,64 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4690,6 +6488,64 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -4718,6 +6574,934 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B @@ -5057,9 +7841,9 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -5067,13 +7851,13 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. PLL_FDIV = 0x30 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -5113,9 +7897,9 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. DIVISOR = 0x4 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000004U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U @@ -5132,26 +7916,26 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000400U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000114[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000114[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000114[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x000FA3C0U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. PLL_FDIV = 0x2a + // .. .. .. ==> 0XF8000104[18:12] = 0x0000002AU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002A000U // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x0002A000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -5194,14 +7978,14 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. DDR_3XCLK_DIVISOR = 0x4 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000004U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x6 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000006U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x18000000U // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x18400003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0xc @@ -5286,14 +8070,14 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0xf - // .. ==> 0XF8000128[13:8] = 0x0000000FU - // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U - // .. DIVISOR1 = 0x7 - // .. ==> 0XF8000128[25:20] = 0x00000007U - // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. DIVISOR0 = 0x2e + // .. ==> 0XF8000128[13:8] = 0x0000002EU + // .. ==> MASK : 0x00003F00U VAL : 0x00002E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302E01U), // .. CLKACT0 = 0x0 // .. ==> 0XF8000154[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5338,14 +8122,14 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x5 - // .. .. ==> 0XF8000170[13:8] = 0x00000005U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR0 = 0x8 + // .. .. ==> 0XF8000170[13:8] = 0x00000008U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -5455,9 +8239,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 - // .. .. ==> 0XF8006004[11:0] = 0x00000082U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x55 + // .. .. ==> 0XF8006004[11:0] = 0x00000055U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000055U // .. .. reg_ddrc_active_ranks = 0x1 // .. .. ==> 0XF8006004[13:12] = 0x00000001U // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U @@ -5480,7 +8264,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006004[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081055U), // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf // .. .. ==> 0XF8006008[10:0] = 0x0000000FU // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU @@ -5514,66 +8298,66 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U // .. .. EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0xa1 - // .. .. ==> 0XF8006014[13:6] = 0x000000A1U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_t_rc = 0x12 + // .. .. ==> 0XF8006014[5:0] = 0x00000012U + // .. .. ==> MASK : 0x0000003FU VAL : 0x00000012U + // .. .. reg_ddrc_t_rfc_min = 0x69 + // .. .. ==> 0XF8006014[13:6] = 0x00000069U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001A40U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0XF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), - // .. .. reg_ddrc_wr2pre = 0x13 - // .. .. ==> 0XF8006018[4:0] = 0x00000013U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041A52U), + // .. .. reg_ddrc_wr2pre = 0x10 + // .. .. ==> 0XF8006018[4:0] = 0x00000010U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000010U // .. .. reg_ddrc_powerdown_to_x32 = 0x6 // .. .. ==> 0XF8006018[9:5] = 0x00000006U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_faw = 0xe + // .. .. ==> 0XF8006018[15:10] = 0x0000000EU + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00003800U + // .. .. reg_ddrc_t_ras_max = 0x17 + // .. .. ==> 0XF8006018[21:16] = 0x00000017U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00170000U + // .. .. reg_ddrc_t_ras_min = 0xd + // .. .. ==> 0XF8006018[26:22] = 0x0000000DU + // .. .. ==> MASK : 0x07C00000U VAL : 0x03400000U // .. .. reg_ddrc_t_cke = 0x4 // .. .. ==> 0XF8006018[31:28] = 0x00000004U // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x435738D0U), // .. .. reg_ddrc_write_latency = 0x5 // .. .. ==> 0XF800601C[4:0] = 0x00000005U // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U // .. .. reg_ddrc_rd2wr = 0x7 // .. .. ==> 0XF800601C[9:5] = 0x00000007U // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xf - // .. .. ==> 0XF800601C[14:10] = 0x0000000FU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U - // .. .. reg_ddrc_t_xp = 0x5 - // .. .. ==> 0XF800601C[19:15] = 0x00000005U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x3 + // .. .. ==> 0XF800601C[19:15] = 0x00000003U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00018000U // .. .. reg_ddrc_pad_pd = 0x0 // .. .. ==> 0XF800601C[22:20] = 0x00000000U // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x5 - // .. .. ==> 0XF800601C[27:23] = 0x00000005U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U // .. .. reg_ddrc_t_rcd = 0x7 // .. .. ==> 0XF800601C[31:28] = 0x00000007U // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7201B8E5U), // .. .. reg_ddrc_t_ccd = 0x4 // .. .. ==> 0XF8006020[4:2] = 0x00000004U // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. .. reg_ddrc_refresh_margin = 0x2 // .. .. ==> 0XF8006020[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U @@ -5605,7 +8389,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006020[31:31] = 0x00000000U // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), // .. .. reg_ddrc_en_2t_timing_mode = 0x0 // .. .. ==> 0XF8006024[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5654,20 +8438,20 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0xb30 - // .. .. ==> 0XF8006030[15:0] = 0x00000B30U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_mr = 0x530 + // .. .. ==> 0XF8006030[15:0] = 0x00000530U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000530U // .. .. reg_ddrc_emr = 0x4 // .. .. ==> 0XF8006030[31:16] = 0x00000004U // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040530U), // .. .. reg_ddrc_burst_rdwr = 0x4 // .. .. ==> 0XF8006034[3:0] = 0x00000004U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x16d - // .. .. ==> 0XF8006034[13:4] = 0x0000016DU - // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_pre_cke_x1024 = 0xf0 + // .. .. ==> 0XF8006034[13:4] = 0x000000F0U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00000F00U // .. .. reg_ddrc_post_cke_x1024 = 0x1 // .. .. ==> 0XF8006034[25:16] = 0x00000001U // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U @@ -5675,7 +8459,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006034[28:28] = 0x00000000U // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00010F04U), // .. .. reg_ddrc_force_low_pri_n = 0x0 // .. .. ==> 0XF8006038[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -5929,22 +8713,22 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U // .. .. EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. t_zq_short_interval_x1024 = 0x8583 + // .. .. ==> 0XF80060A8[19:0] = 0x00008583U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x00008583U + // .. .. dram_rstn_x1024 = 0x45 + // .. .. ==> 0XF80060A8[27:20] = 0x00000045U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x04500000U // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x04508583U), // .. .. deeppowerdown_en = 0x0 // .. .. ==> 0XF80060AC[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. deeppowerdown_to_x1024 = 0xab + // .. .. ==> 0XF80060AC[8:1] = 0x000000ABU + // .. .. ==> MASK : 0x000001FEU VAL : 0x00000156U // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x00000156U), // .. .. dfi_wrlvl_max_x1024 = 0xfff // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU @@ -6154,35 +8938,35 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF800612C[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF800612C[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF800612C[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006130[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006130[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006130[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006134[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006134[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006134[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_wrlvl_init_ratio = 0x0 // .. .. ==> 0XF8006138[9:0] = 0x00000000U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa4 - // .. .. ==> 0XF8006138[19:10] = 0x000000A4U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. reg_phy_gatelvl_init_ratio = 0x8c + // .. .. ==> 0XF8006138[19:10] = 0x0000008CU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023000U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00023000U), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -6271,9 +9055,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U // .. .. EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006168[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006168[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006168[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6281,10 +9065,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006168[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF800616C[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF800616C[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF800616C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6292,10 +9076,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF800616C[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006170[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006170[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006170[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6303,10 +9087,10 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006170[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 - // .. .. ==> 0XF8006174[10:0] = 0x000000F9U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xe1 + // .. .. ==> 0XF8006174[10:0] = 0x000000E1U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E1U // .. .. reg_phy_fifo_we_in_force = 0x0 // .. .. ==> 0XF8006174[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U @@ -6314,7 +9098,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006174[20:12] = 0x00000000U // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E1U), // .. .. reg_phy_wr_data_slave_ratio = 0xc0 // .. .. ==> 0XF800617C[9:0] = 0x000000C0U // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U @@ -6598,22 +9382,22 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 // .. .. ==> 0XF80062B0[3:0] = 0x00000005U // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_idle_after_reset_x32 = 0xc + // .. .. ==> 0XF80062B0[11:4] = 0x0000000CU + // .. .. ==> MASK : 0x00000FF0U VAL : 0x000000C0U // .. .. reg_ddrc_t_mrw = 0x5 // .. .. ==> 0XF80062B0[21:12] = 0x00000005U // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x000050C5U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0x6f + // .. .. ==> 0XF80062B4[7:0] = 0x0000006FU + // .. .. ==> MASK : 0x000000FFU VAL : 0x0000006FU + // .. .. reg_ddrc_dev_zqinit_x32 = 0xc + // .. .. ==> 0XF80062B4[17:8] = 0x0000000CU + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00000C00U // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x00000C6FU), // .. .. START: POLL ON DCI STATUS // .. .. DONE = 1 // .. .. ==> 0XF8000B74[13:13] = 0x00000001U @@ -7064,6 +9848,354 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. FINISH: DDRIOB SETTINGS // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000730[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7122,6 +10254,64 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x000016E1U), // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7209,6 +10399,64 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x000016A0U), // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800074C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF800074C[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800074C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000750[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 5 + // .. ==> 0XF8000750[7:5] = 0x00000005U + // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000750[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 @@ -7237,6 +10485,934 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x000016A0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000758[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000758[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000758[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800075C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800075C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800075C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000760[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000760[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000760[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000764[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000764[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000764[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000768[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000768[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000768[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800076C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800076C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800076C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000770[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000774[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000774[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000778[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800077C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800077C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000780[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000784[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000788[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800078C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000790[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000790[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000794[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000798[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800079C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007A8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007AC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007B8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007BC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C8[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007CC[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml index cd0efb9..09f1648 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml @@ -4,8 +4,8 @@ - - + + @@ -22,21 +22,21 @@ - + - + - - + + - - + + - + @@ -76,13 +76,13 @@ - + - - + + @@ -92,7 +92,7 @@ - + @@ -110,8 +110,8 @@ - - + + @@ -125,24 +125,24 @@ - + - - - - - - - - - - - - + + + + + + + + + + + + @@ -151,14 +151,14 @@ - - - - - - - - + + + + + + + + @@ -171,182 +171,182 @@ - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -448,10 +448,10 @@ - - - - + + + + @@ -578,7 +578,7 @@ - + @@ -603,7 +603,7 @@ - + @@ -634,7 +634,7 @@ - + diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.cpp b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.cpp index 26da6f2..b4e68b8 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.cpp +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.cpp @@ -61,12 +61,10 @@ #ifdef XILINX_SIMULATOR -design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") +design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") { // initialize pins - mp_impl->FCLK_CLK0(FCLK_CLK0); - mp_impl->FCLK_RESET0_N(FCLK_RESET0_N); mp_impl->MIO(MIO); mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CKE(DDR_CKE); @@ -101,12 +99,10 @@ void design_1_processing_system7_0_0::before_end_of_elaboration() #ifdef XM_SYSTEMC -design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") +design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") { // initialize pins - mp_impl->FCLK_CLK0(FCLK_CLK0); - mp_impl->FCLK_RESET0_N(FCLK_RESET0_N); mp_impl->MIO(MIO); mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CKE(DDR_CKE); @@ -141,12 +137,10 @@ void design_1_processing_system7_0_0::before_end_of_elaboration() #ifdef RIVIERA -design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") +design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") { // initialize pins - mp_impl->FCLK_CLK0(FCLK_CLK0); - mp_impl->FCLK_RESET0_N(FCLK_RESET0_N); mp_impl->MIO(MIO); mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CKE(DDR_CKE); @@ -181,11 +175,9 @@ void design_1_processing_system7_0_0::before_end_of_elaboration() #ifdef VCSSYSTEMC -design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") +design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") { // initialize pins - mp_impl->FCLK_CLK0(FCLK_CLK0); - mp_impl->FCLK_RESET0_N(FCLK_RESET0_N); mp_impl->MIO(MIO); mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CKE(DDR_CKE); @@ -223,11 +215,9 @@ void design_1_processing_system7_0_0::before_end_of_elaboration() #ifdef MTI_SYSTEMC -design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") +design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") { // initialize pins - mp_impl->FCLK_CLK0(FCLK_CLK0); - mp_impl->FCLK_RESET0_N(FCLK_RESET0_N); mp_impl->MIO(MIO); mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CKE(DDR_CKE); diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h index 8ae4899..0e71ccc 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h @@ -80,8 +80,6 @@ public: // module pin-to-pin RTL interface - sc_core::sc_out< bool > FCLK_CLK0; - sc_core::sc_out< bool > FCLK_RESET0_N; sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CKE; @@ -130,8 +128,6 @@ public: // module pin-to-pin RTL interface - sc_core::sc_out< bool > FCLK_CLK0; - sc_core::sc_out< bool > FCLK_RESET0_N; sc_core::sc_inout< sc_dt::sc_bv<54> > MIO; sc_core::sc_inout< bool > DDR_CAS_n; sc_core::sc_inout< bool > DDR_CKE; @@ -180,8 +176,6 @@ public: // module pin-to-pin RTL interface - sc_core::sc_out< bool > FCLK_CLK0; - sc_core::sc_out< bool > FCLK_RESET0_N; sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CKE; @@ -230,8 +224,6 @@ public: // module pin-to-pin RTL interface - sc_core::sc_out< bool > FCLK_CLK0; - sc_core::sc_out< bool > FCLK_RESET0_N; sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CKE; @@ -284,8 +276,6 @@ public: // module pin-to-pin RTL interface - sc_core::sc_out< bool > FCLK_CLK0; - sc_core::sc_out< bool > FCLK_RESET0_N; sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CKE; diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.sv b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.sv index 8396f0c..8ce4e8c 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.sv +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.sv @@ -677,8 +677,6 @@ //MODULE DECLARATION module design_1_processing_system7_0_0 ( - FCLK_CLK0, - FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, @@ -753,7 +751,7 @@ parameter C_USE_S_AXI_HP3 = 0; parameter C_USE_S_AXI_ACP = 0; parameter C_PS7_SI_REV = "PRODUCTION"; - parameter C_FCLK_CLK0_BUF = "TRUE"; + parameter C_FCLK_CLK0_BUF = "FALSE"; parameter C_FCLK_CLK1_BUF = "FALSE"; parameter C_FCLK_CLK2_BUF = "FALSE"; parameter C_FCLK_CLK3_BUF = "FALSE"; @@ -763,8 +761,6 @@ //INPUT AND OUTPUT PORTS - output FCLK_CLK0; - output FCLK_RESET0_N; inout [53 : 0] MIO; inout DDR_CAS_n; inout DDR_CKE; @@ -789,8 +785,6 @@ //REG DECLARATIONS - reg FCLK_CLK0; - reg FCLK_RESET0_N; string ip_name; reg disable_port; @@ -799,7 +793,6 @@ import "DPI-C" function void ps7_set_ip_context(input string ip_name); import "DPI-C" function void ps7_set_str_param(input string name,input string val); import "DPI-C" function void ps7_set_int_param(input string name,input longint val); import "DPI-C" function void ps7_init_c_model(); -import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0(); export "DPI-C" function ps7_stop_sim; function void ps7_stop_sim(); $display("End of simulation"); @@ -895,18 +888,5 @@ import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0(); ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN ); ps7_init_c_model(); end - initial - begin - FCLK_CLK0 = 1'b0; - end - - always #(10.0) FCLK_CLK0 <= ~FCLK_CLK0; - - always@(posedge FCLK_CLK0) - begin - ps7_set_ip_context(ip_name); - ps7_simulate_single_cycle_FCLK_CLK0(); - end - endmodule diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v index 51a4df7..4129b26 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v @@ -56,8 +56,6 @@ `timescale 1ns/1ps module design_1_processing_system7_0_0 ( -FCLK_CLK0, -FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, @@ -80,8 +78,6 @@ PS_SRSTB, PS_CLK, PS_PORB ); -output FCLK_CLK0; -output FCLK_RESET0_N; input [53 : 0] MIO; input DDR_CAS_n; input DDR_CKE; @@ -119,7 +115,7 @@ input PS_PORB; .C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP3_DATA_WIDTH(64), .C_HIGH_OCM_EN(0), - .C_FCLK_CLK0_FREQ(50.0), + .C_FCLK_CLK0_FREQ(10.0), .C_FCLK_CLK1_FREQ(10.0), .C_FCLK_CLK2_FREQ(10.0), .C_FCLK_CLK3_FREQ(10.0), @@ -481,14 +477,14 @@ input PS_PORB; .S_AXI_HP3_WID(6'B0), .S_AXI_HP3_WDATA(64'B0), .S_AXI_HP3_WSTRB(8'B0), - .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK0(), .FCLK_CLK1(), .FCLK_CLK2(), .FCLK_CLK3(), - .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET0_N(), .FCLK_RESET1_N(), .FCLK_RESET2_N(), .FCLK_RESET3_N(), diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.cpp b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.cpp index a3eb6ba..96afcf6 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.cpp +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.cpp @@ -112,7 +112,7 @@ design_1_processing_system7_0_0_sc::design_1_processing_system7_0_0_sc(const sc_ model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1"); model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT"); model_param_props.addString("C_PS7_SI_REV", "PRODUCTION"); - model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE"); + model_param_props.addString("C_FCLK_CLK0_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE"); diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv index 492af2b..0ec74e3 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv @@ -66,8 +66,6 @@ typedef bit bit_as_bool; (* SC_MODULE_EXPORT *) module design_1_processing_system7_0_0 ( - output bit_as_bool FCLK_CLK0, - output bit_as_bool FCLK_RESET0_N, output bit [53 : 0] MIO, output bit_as_bool DDR_CAS_n, output bit_as_bool DDR_CKE, @@ -95,11 +93,9 @@ endmodule `ifdef XCELIUM (* XMSC_MODULE_EXPORT *) -module design_1_processing_system7_0_0 (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB) +module design_1_processing_system7_0_0 (MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB) (* integer foreign = "SystemC"; *); - output wire FCLK_CLK0; - output wire FCLK_RESET0_N; inout wire [53 : 0] MIO; inout wire DDR_CAS_n; inout wire DDR_CKE; diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.cpp b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.cpp index 685bf10..a64292b 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.cpp +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.cpp @@ -144,8 +144,6 @@ void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name, xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent - ,FCLK_CLK0("FCLK_CLK0") - ,FCLK_RESET0_N("FCLK_RESET0_N") ,MIO("MIO") ,DDR_CAS_n("DDR_CAS_n") ,DDR_CKE("DDR_CKE") @@ -167,7 +165,6 @@ processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_n ,PS_SRSTB("PS_SRSTB") ,PS_CLK("PS_CLK") ,PS_PORB("PS_PORB") - ,FCLK_CLK0_clk("FCLK_CLK0_clk", sc_time(20000.0,sc_core::SC_PS))//clock period in picoseconds = 1000000/freq(in MZ) ,prop(_prop) { //creating instances of xtlm slave sockets @@ -202,27 +199,14 @@ processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_n m_zynq_tlm_model->tie_off(); - SC_METHOD(trigger_FCLK_CLK0_pin); - sensitive << FCLK_CLK0_clk; - dont_initialize(); m_zynq_tlm_model->rst(qemu_rst); } processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() { //deleteing dynamically created objects } - //Method which is sentive to FCLK_CLK0_clk sc_clock object - //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value - void processing_system7_v5_5_tlm ::trigger_FCLK_CLK0_pin() { - FCLK_CLK0.write(FCLK_CLK0_clk.read()); - } - //ps2pl_rst[0] output reset pin - void processing_system7_v5_5_tlm :: FCLK_RESET0_N_trigger() { - FCLK_RESET0_N.write(m_zynq_tlm_model->ps2pl_rst[0].read()); - } void processing_system7_v5_5_tlm ::start_of_simulation() { //temporary fix to drive the enabled reset pin - FCLK_RESET0_N.write(true); qemu_rst.write(false); } diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h index 876b69c..62c9ab7 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h @@ -134,8 +134,6 @@ class processing_system7_v5_5_tlm : public sc_core::sc_module { public: // Non-AXI ports are declared here - sc_core::sc_out FCLK_CLK0; - sc_core::sc_out FCLK_RESET0_N; sc_core::sc_inout > MIO; sc_core::sc_inout DDR_CAS_n; sc_core::sc_inout DDR_CKE; @@ -192,16 +190,9 @@ processing_system7_v5_5_tlm(sc_core::sc_module_name name, // sc_clocks for generating pl clocks // output pins FCLK_CLK0..3 are drived by these clocks - sc_core::sc_clock FCLK_CLK0_clk; - //Method which is sentive to FCLK_CLK0_clk sc_clock object - //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value - void trigger_FCLK_CLK0_pin(); - //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled - //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761) - void FCLK_RESET0_N_trigger(); sc_signal qemu_rst; void start_of_simulation(); diff --git a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v index 1154daa..8e65006 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v @@ -54,12 +54,10 @@ (* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\ ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\ -_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=0,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TX\ -N=1,C_GP1_EN_MODIFIABLE_TXN=1}" *) +_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=0,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=FALSE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_T\ +XN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module design_1_processing_system7_0_0 ( - FCLK_CLK0, - FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, @@ -83,12 +81,6 @@ module design_1_processing_system7_0_0 ( PS_PORB ); -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) -output wire FCLK_CLK0; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) -output wire FCLK_RESET0_N; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout wire [53 : 0] MIO; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) @@ -184,7 +176,7 @@ inout wire PS_PORB; .C_USE_S_AXI_HP3(0), .C_USE_S_AXI_ACP(0), .C_PS7_SI_REV("PRODUCTION"), - .C_FCLK_CLK0_BUF("TRUE"), + .C_FCLK_CLK0_BUF("FALSE"), .C_FCLK_CLK1_BUF("FALSE"), .C_FCLK_CLK2_BUF("FALSE"), .C_FCLK_CLK3_BUF("FALSE"), @@ -803,7 +795,7 @@ inout wire PS_PORB; .DMA1_DRTYPE(2'B0), .DMA2_DRTYPE(2'B0), .DMA3_DRTYPE(2'B0), - .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK0(), .FCLK_CLK1(), .FCLK_CLK2(), .FCLK_CLK3(), @@ -811,7 +803,7 @@ inout wire PS_PORB; .FCLK_CLKTRIG1_N(1'B0), .FCLK_CLKTRIG2_N(1'B0), .FCLK_CLKTRIG3_N(1'B0), - .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET0_N(), .FCLK_RESET1_N(), .FCLK_RESET2_N(), .FCLK_RESET3_N(), diff --git a/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v b/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v index 9499956..b27478a 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v @@ -1,7 +1,7 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -//Date : Sun Oct 20 21:34:05 2024 +//Date : Fri Oct 25 01:46:36 2024 //Host : destop1 running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 diff --git a/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef b/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef index 1028a0c..7967d91 100644 Binary files a/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef and b/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef differ diff --git a/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v b/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v index 9499956..b27478a 100644 --- a/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v +++ b/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v @@ -1,7 +1,7 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -//Date : Sun Oct 20 21:34:05 2024 +//Date : Fri Oct 25 01:46:36 2024 //Host : destop1 running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 diff --git a/project_1/project_1.hw/hw_1/hw.xml b/project_1/project_1.hw/hw_1/hw.xml new file mode 100644 index 0000000..f65e3d5 --- /dev/null +++ b/project_1/project_1.hw/hw_1/hw.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/project_1/project_1.hw/project_1.lpr b/project_1/project_1.hw/project_1.lpr index 7c60ccc..d56332c 100644 --- a/project_1/project_1.hw/project_1.lpr +++ b/project_1/project_1.hw/project_1.lpr @@ -3,4 +3,6 @@ - + + + diff --git a/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v b/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v index 51a4df7..4129b26 100644 --- a/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v +++ b/project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v @@ -56,8 +56,6 @@ `timescale 1ns/1ps module design_1_processing_system7_0_0 ( -FCLK_CLK0, -FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, @@ -80,8 +78,6 @@ PS_SRSTB, PS_CLK, PS_PORB ); -output FCLK_CLK0; -output FCLK_RESET0_N; input [53 : 0] MIO; input DDR_CAS_n; input DDR_CKE; @@ -119,7 +115,7 @@ input PS_PORB; .C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP3_DATA_WIDTH(64), .C_HIGH_OCM_EN(0), - .C_FCLK_CLK0_FREQ(50.0), + .C_FCLK_CLK0_FREQ(10.0), .C_FCLK_CLK1_FREQ(10.0), .C_FCLK_CLK2_FREQ(10.0), .C_FCLK_CLK3_FREQ(10.0), @@ -481,14 +477,14 @@ input PS_PORB; .S_AXI_HP3_WID(6'B0), .S_AXI_HP3_WDATA(64'B0), .S_AXI_HP3_WSTRB(8'B0), - .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK0(), .FCLK_CLK1(), .FCLK_CLK2(), .FCLK_CLK3(), - .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET0_N(), .FCLK_RESET1_N(), .FCLK_RESET2_N(), .FCLK_RESET3_N(), diff --git a/project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v b/project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v index 9499956..b27478a 100644 --- a/project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v +++ b/project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v @@ -1,7 +1,7 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -//Date : Sun Oct 20 21:34:05 2024 +//Date : Fri Oct 25 01:46:36 2024 //Host : destop1 running 64-bit major release (build 9200) //Command : generate_target design_1.bd //Design : design_1 diff --git a/project_1/project_1.ip_user_files/mem_init_files/design_1.bda b/project_1/project_1.ip_user_files/mem_init_files/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/mem_init_files/design_1.bda +++ b/project_1/project_1.ip_user_files/mem_init_files/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.h b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.h +++ b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.html b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.html +++ b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.tcl b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/mem_init_files/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/mem_init_files/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/mem_init_files/ps7_init_gpl.h b/project_1/project_1.ip_user_files/mem_init_files/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/mem_init_files/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/mem_init_files/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh index 7b29fc4..eeba258 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 @@ -90,11 +90,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/activehdl" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh index c0ac916..be0b961 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 @@ -92,11 +92,10 @@ setup() copy_setup_file() { file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/modelsim" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.sh index 8ed6d44..80b08d7 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 @@ -99,11 +99,10 @@ setup() copy_setup_file() { file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.sh index 143d37e..d6d0081 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 @@ -90,11 +90,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.sh index 9444564..2e9c3ec 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/README.txt index 36ce5e8..2d2c88d 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh index 8c023fd..3b6026c 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/README.txt b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/README.txt index 46ab106..1b4f069 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/README.txt +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 +# Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024 # ################################################################################ diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.bda b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.bda +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.sh b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.sh index 711a0dc..98a8e3b 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.sh +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 +# Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # # Tool Version Limit: 2022.10 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.h index 67a0831..1362a8a 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.h @@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html index 8356427..40ba227 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html @@ -153,22 +153,22 @@ Xilinx MIO 0 @@ -176,22 +176,22 @@ Xilinx MIO 1 @@ -199,22 +199,22 @@ Xilinx MIO 2 @@ -222,22 +222,22 @@ Xilinx MIO 3 @@ -245,22 +245,22 @@ Xilinx MIO 4 @@ -268,22 +268,22 @@ Xilinx MIO 5 @@ -291,22 +291,22 @@ Xilinx MIO 6 @@ -314,22 +314,22 @@ Xilinx MIO 7 @@ -337,22 +337,22 @@ Xilinx MIO 8 @@ -360,22 +360,22 @@ Xilinx MIO 9 @@ -383,22 +383,22 @@ Xilinx MIO 10 @@ -406,22 +406,22 @@ Xilinx MIO 11 @@ -475,22 +475,22 @@ in MIO 14 @@ -498,22 +498,22 @@ in MIO 15 @@ -590,22 +590,22 @@ inout MIO 19 @@ -613,22 +613,22 @@ inout MIO 20 @@ -659,22 +659,22 @@ inout MIO 22 @@ -682,22 +682,22 @@ inout MIO 23 @@ -705,22 +705,22 @@ inout MIO 24 @@ -728,22 +728,22 @@ inout MIO 25 @@ -751,22 +751,22 @@ inout MIO 26 @@ -774,22 +774,22 @@ inout MIO 27 @@ -797,22 +797,22 @@ inout MIO 28 @@ -820,22 +820,22 @@ inout MIO 29 @@ -843,22 +843,22 @@ inout MIO 30 @@ -866,22 +866,22 @@ inout MIO 31 @@ -889,22 +889,22 @@ inout MIO 32 @@ -912,22 +912,22 @@ inout MIO 33 @@ -935,22 +935,22 @@ inout MIO 34 @@ -958,22 +958,22 @@ inout MIO 35 @@ -981,22 +981,22 @@ inout MIO 36 @@ -1004,22 +1004,22 @@ inout MIO 37 @@ -1027,22 +1027,22 @@ inout MIO 38 @@ -1050,22 +1050,22 @@ inout MIO 39 @@ -1073,22 +1073,22 @@ inout MIO 40 @@ -1096,22 +1096,22 @@ inout MIO 41 @@ -1119,22 +1119,22 @@ inout MIO 42 @@ -1142,22 +1142,22 @@ inout MIO 43 @@ -1165,22 +1165,22 @@ inout MIO 44 @@ -1188,22 +1188,22 @@ inout MIO 45 @@ -1211,22 +1211,22 @@ inout MIO 46 @@ -1234,22 +1234,22 @@ inout MIO 47 @@ -1257,22 +1257,22 @@ inout MIO 48 @@ -1280,22 +1280,22 @@ inout MIO 49 @@ -1303,22 +1303,22 @@ inout MIO 50 @@ -1326,22 +1326,22 @@ inout MIO 51 @@ -1349,22 +1349,22 @@ inout MIO 52 @@ -1372,22 +1372,22 @@ inout MIO 53
- +GPIO - +gpio[0] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[1] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[2] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[3] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[4] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[5] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[6] - +LVCMOS 3.3V - +slow - +disabled - +inout
- +GPIO - +gpio[7] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[8] - +LVCMOS 3.3V - +slow - +disabled - +out
- +GPIO - +gpio[9] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[10] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[11] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[14] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[15] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +SPI 0 - +ss[1] - +LVCMOS 3.3V - +slow - +enabled - +out
- +SPI 0 - +ss[2] - +LVCMOS 3.3V - +slow - +enabled - +out
- +GPIO - +gpio[22] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[23] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[24] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[25] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[26] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[27] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[28] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[29] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[30] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[31] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[32] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[33] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[34] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[35] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[36] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[37] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[38] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[39] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[40] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[41] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[42] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[43] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[44] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[45] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[46] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[47] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[48] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[49] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[50] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[51] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[52] - +LVCMOS 3.3V - +slow - +enabled - +inout
- +GPIO - +gpio[53] - +LVCMOS 3.3V - +slow - +enabled - +inout
@@ -1475,7 +1475,7 @@ Select the burst Length. It refers to the amount of data read/written after a re Operating Frequency (MHz) -533.333333 +350 Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade @@ -1790,7 +1790,7 @@ The average of the data midpoint delay, of the data delays associated with a byt ARM PLL -666.666687 +400.000000 @@ -1823,7 +1823,7 @@ IO PLL IO PLL -50.000000 +10.000000 @@ -2576,10 +2576,10 @@ SLCR_LOCK f0 -2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -2639,7 +2639,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -2724,10 +2724,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -2747,7 +2747,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -3391,10 +3391,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -3514,7 +3514,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -3599,10 +3599,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -3619,10 +3619,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -3639,10 +3639,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. @@ -3662,7 +3662,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -3747,10 +3747,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. @@ -3770,7 +3770,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -4434,10 +4434,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -4454,10 +4454,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -4477,7 +4477,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -5840,10 +5840,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -5860,10 +5860,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -5883,7 +5883,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -6469,10 +6469,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -6512,7 +6512,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -9316,10 +9316,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -9379,7 +9379,7 @@ ddrc_ctrl -1082 +1055 Two Rank Configuration @@ -9904,10 +9904,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -9924,10 +9924,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -9967,7 +9967,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -10051,10 +10051,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -10091,10 +10091,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -10111,10 +10111,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -10131,10 +10131,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -10174,7 +10174,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -10298,10 +10298,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -10318,10 +10318,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -10358,10 +10358,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -10401,7 +10401,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -10505,10 +10505,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -10688,7 +10688,7 @@ ddrc_ctrl -270872d0 +27087290 DRAM Parameters 3 @@ -11293,10 +11293,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register @@ -11336,7 +11336,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -11440,10 +11440,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -11503,7 +11503,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -13811,10 +13811,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -13831,10 +13831,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -13874,7 +13874,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -14332,10 +14332,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -14352,10 +14352,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -14375,7 +14375,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -14479,10 +14479,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -14502,7 +14502,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -16737,10 +16737,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16760,7 +16760,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16864,10 +16864,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -16887,7 +16887,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -16991,10 +16991,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17014,7 +17014,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -17118,10 +17118,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -17141,7 +17141,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -18401,10 +18401,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18464,7 +18464,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18548,10 +18548,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18611,7 +18611,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18695,10 +18695,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18758,7 +18758,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -18842,10 +18842,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. @@ -18905,7 +18905,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -21948,10 +21948,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -21991,7 +21991,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -22075,10 +22075,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -22095,10 +22095,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -22118,7 +22118,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -22968,6 +22968,270 @@ DDRIOB_DCI_CTRL + +MIO_PIN_00 + + + +0XF8000700 + + +32 + + +RW + + +0x000000 + + +MIO Pin 0 Control + + + + + +MIO_PIN_01 + + + +0XF8000704 + + +32 + + +RW + + +0x000000 + + +MIO Pin 1 Control + + + + + +MIO_PIN_02 + + + +0XF8000708 + + +32 + + +RW + + +0x000000 + + +MIO Pin 2 Control + + + + + +MIO_PIN_03 + + + +0XF800070C + + +32 + + +RW + + +0x000000 + + +MIO Pin 3 Control + + + + + +MIO_PIN_04 + + + +0XF8000710 + + +32 + + +RW + + +0x000000 + + +MIO Pin 4 Control + + + + + +MIO_PIN_05 + + + +0XF8000714 + + +32 + + +RW + + +0x000000 + + +MIO Pin 5 Control + + + + + +MIO_PIN_06 + + + +0XF8000718 + + +32 + + +RW + + +0x000000 + + +MIO Pin 6 Control + + + + + +MIO_PIN_07 + + + +0XF800071C + + +32 + + +RW + + +0x000000 + + +MIO Pin 7 Control + + + + + +MIO_PIN_08 + + + +0XF8000720 + + +32 + + +RW + + +0x000000 + + +MIO Pin 8 Control + + + + + +MIO_PIN_09 + + + +0XF8000724 + + +32 + + +RW + + +0x000000 + + +MIO Pin 9 Control + + + + + +MIO_PIN_10 + + + +0XF8000728 + + +32 + + +RW + + +0x000000 + + +MIO Pin 10 Control + + + + + +MIO_PIN_11 + + + +0XF800072C + + +32 + + +RW + + +0x000000 + + +MIO Pin 11 Control + + + + MIO_PIN_12 @@ -23012,6 +23276,50 @@ MIO_PIN_13 + +MIO_PIN_14 + + + +0XF8000738 + + +32 + + +RW + + +0x000000 + + +MIO Pin 14 Control + + + + + +MIO_PIN_15 + + + +0XF800073C + + +32 + + +RW + + +0x000000 + + +MIO Pin 15 Control + + + + MIO_PIN_16 @@ -23078,6 +23386,50 @@ MIO_PIN_18 + +MIO_PIN_19 + + + +0XF800074C + + +32 + + +RW + + +0x000000 + + +MIO Pin 19 Control + + + + + +MIO_PIN_20 + + + +0XF8000750 + + +32 + + +RW + + +0x000000 + + +MIO Pin 20 Control + + + + MIO_PIN_21 @@ -23100,6 +23452,710 @@ MIO_PIN_21 + +MIO_PIN_22 + + + +0XF8000758 + + +32 + + +RW + + +0x000000 + + +MIO Pin 22 Control + + + + + +MIO_PIN_23 + + + +0XF800075C + + +32 + + +RW + + +0x000000 + + +MIO Pin 23 Control + + + + + +MIO_PIN_24 + + + +0XF8000760 + + +32 + + +RW + + +0x000000 + + +MIO Pin 24 Control + + + + + +MIO_PIN_25 + + + +0XF8000764 + + +32 + + +RW + + +0x000000 + + +MIO Pin 25 Control + + + + + +MIO_PIN_26 + + + +0XF8000768 + + +32 + + +RW + + +0x000000 + + +MIO Pin 26 Control + + + + + +MIO_PIN_27 + + + +0XF800076C + + +32 + + +RW + + +0x000000 + + +MIO Pin 27 Control + + + + + +MIO_PIN_28 + + + +0XF8000770 + + +32 + + +RW + + +0x000000 + + +MIO Pin 28 Control + + + + + +MIO_PIN_29 + + + +0XF8000774 + + +32 + + +RW + + +0x000000 + + +MIO Pin 29 Control + + + + + +MIO_PIN_30 + + + +0XF8000778 + + +32 + + +RW + + +0x000000 + + +MIO Pin 30 Control + + + + + +MIO_PIN_31 + + + +0XF800077C + + +32 + + +RW + + +0x000000 + + +MIO Pin 31 Control + + + + + +MIO_PIN_32 + + + +0XF8000780 + + +32 + + +RW + + +0x000000 + + +MIO Pin 32 Control + + + + + +MIO_PIN_33 + + + +0XF8000784 + + +32 + + +RW + + +0x000000 + + +MIO Pin 33 Control + + + + + +MIO_PIN_34 + + + +0XF8000788 + + +32 + + +RW + + +0x000000 + + +MIO Pin 34 Control + + + + + +MIO_PIN_35 + + + +0XF800078C + + +32 + + +RW + + +0x000000 + + +MIO Pin 35 Control + + + + + +MIO_PIN_36 + + + +0XF8000790 + + +32 + + +RW + + +0x000000 + + +MIO Pin 36 Control + + + + + +MIO_PIN_37 + + + +0XF8000794 + + +32 + + +RW + + +0x000000 + + +MIO Pin 37 Control + + + + + +MIO_PIN_38 + + + +0XF8000798 + + +32 + + +RW + + +0x000000 + + +MIO Pin 38 Control + + + + + +MIO_PIN_39 + + + +0XF800079C + + +32 + + +RW + + +0x000000 + + +MIO Pin 39 Control + + + + + +MIO_PIN_40 + + + +0XF80007A0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 40 Control + + + + + +MIO_PIN_41 + + + +0XF80007A4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 41 Control + + + + + +MIO_PIN_42 + + + +0XF80007A8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 42 Control + + + + + +MIO_PIN_43 + + + +0XF80007AC + + +32 + + +RW + + +0x000000 + + +MIO Pin 43 Control + + + + + +MIO_PIN_44 + + + +0XF80007B0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 44 Control + + + + + +MIO_PIN_45 + + + +0XF80007B4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 45 Control + + + + + +MIO_PIN_46 + + + +0XF80007B8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 46 Control + + + + + +MIO_PIN_47 + + + +0XF80007BC + + +32 + + +RW + + +0x000000 + + +MIO Pin 47 Control + + + + + +MIO_PIN_48 + + + +0XF80007C0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 48 Control + + + + + +MIO_PIN_49 + + + +0XF80007C4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 49 Control + + + + + +MIO_PIN_50 + + + +0XF80007C8 + + +32 + + +RW + + +0x000000 + + +MIO Pin 50 Control + + + + + +MIO_PIN_51 + + + +0XF80007CC + + +32 + + +RW + + +0x000000 + + +MIO Pin 51 Control + + + + + +MIO_PIN_52 + + + +0XF80007D0 + + +32 + + +RW + + +0x000000 + + +MIO Pin 52 Control + + + + + +MIO_PIN_53 + + + +0XF80007D4 + + +32 + + +RW + + +0x000000 + + +MIO Pin 53 Control + + + + SLCR_LOCK @@ -26902,6 +27958,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -27436,6 +31696,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -28237,6 +33031,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -28504,6 +33832,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -32747,10 +46619,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -32810,7 +46682,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -32895,10 +46767,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -32918,7 +46790,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -33562,10 +47434,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Frequency divisor for the CPU clock source. @@ -33685,7 +47557,7 @@ SLCR_LOCK -1f000200 +1f000400 CPU Clock Control @@ -33770,10 +47642,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. @@ -33790,10 +47662,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. @@ -33810,10 +47682,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. @@ -33833,7 +47705,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -33918,10 +47790,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. @@ -33941,7 +47813,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -34605,10 +48477,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Frequency divisor for the ddr_3x clock @@ -34625,10 +48497,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Frequency divisor for the ddr_2x clock @@ -34648,7 +48520,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -36011,10 +49883,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -36031,10 +49903,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -36054,7 +49926,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -36640,10 +50512,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -36683,7 +50555,7 @@ SLCR_LOCK -400500 +400800 PL Clock 0 Output control @@ -39509,10 +53381,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. @@ -39672,7 +53544,7 @@ ddrc_ctrl -81082 +81055 Two Rank Configuration @@ -40197,10 +54069,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. @@ -40217,10 +54089,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. @@ -40260,7 +54132,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters 0 @@ -40344,10 +54216,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. @@ -40384,10 +54256,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. @@ -40404,10 +54276,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. @@ -40424,10 +54296,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. @@ -40467,7 +54339,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters 1 @@ -40591,10 +54463,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -40611,10 +54483,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM related. @@ -40651,10 +54523,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. @@ -40694,7 +54566,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters 2 @@ -40798,10 +54670,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED @@ -41021,7 +54893,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters 3 @@ -41646,10 +55518,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register @@ -41689,7 +55561,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access @@ -41793,10 +55665,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) @@ -41856,7 +55728,7 @@ ddrc_ctrl -116d4 +10f04 DRAM Burst 8 read/write @@ -44404,10 +58276,10 @@ ddrc_ctrl f000 -6 +5 -6000 +5000 This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE @@ -44424,10 +58296,10 @@ ddrc_ctrl f0000 -6 +5 -60000 +50000 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX @@ -44467,7 +58339,7 @@ ddrc_ctrl -466111 +455111 Controller register 5 @@ -45052,10 +58924,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. @@ -45072,10 +58944,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -45095,7 +58967,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters @@ -45199,10 +59071,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. @@ -45222,7 +59094,7 @@ ddrc_ctrl -1fe +156 Deep powerdown (LPDDR2) @@ -47837,10 +61709,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47860,7 +61732,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -47964,10 +61836,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -47987,7 +61859,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 1. @@ -48091,10 +61963,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48114,7 +61986,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 2. @@ -48218,10 +62090,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -48241,7 +62113,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 3. @@ -49501,10 +63373,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49564,7 +63436,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 0. @@ -49648,10 +63520,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49711,7 +63583,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 1. @@ -49795,10 +63667,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -49858,7 +63730,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 2. @@ -49942,10 +63814,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -50005,7 +63877,7 @@ ddrc_ctrl -f9 +e1 PHY FIFO write enable configuration for data slice 3. @@ -53228,10 +67100,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Units: 32 clock cycles. @@ -53271,7 +67143,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 @@ -53355,10 +67227,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -53375,10 +67247,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -53398,7 +67270,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 @@ -54248,6 +68120,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
MIO_PIN_12 @@ -54292,6 +68428,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
MIO_PIN_16 @@ -54358,6 +68538,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
MIO_PIN_21 @@ -54380,6 +68604,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
SLCR_LOCK @@ -58202,6 +73130,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Pin 1 Control +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Pin 2 Control +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Pin 3 Control +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Pin 4 Control +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Pin 5 Control +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Pin 6 Control +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

@@ -58736,6 +76868,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

@@ -59537,6 +78203,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Pin 19 Control +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

@@ -59804,6 +79004,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Pin 22 Control +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Pin 23 Control +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Pin 24 Control +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Pin 25 Control +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Pin 26 Control +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Pin 27 Control +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Pin 28 Control +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Pin 29 Control +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Pin 30 Control +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Pin 31 Control +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Pin 32 Control +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Pin 33 Control +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Pin 34 Control +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Pin 35 Control +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Pin 36 Control +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Pin 37 Control +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Pin 38 Control +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Pin 39 Control +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Pin 40 Control +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Pin 41 Control +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Pin 42 Control +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Pin 43 Control +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Pin 44 Control +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Pin 45 Control +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Pin 46 Control +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Pin 47 Control +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Pin 48 Control +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Pin 49 Control +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Pin 50 Control +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Pin 51 Control +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Pin 52 Control +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Pin 53 Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

@@ -64046,10 +91790,10 @@ SLCR_LOCK f0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
-2 +4 -20 +40 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -64109,7 +91853,7 @@ SLCR_LOCK -fa220 +fa240 ARM PLL Configuration @@ -64194,10 +91938,10 @@ SLCR_LOCK 7f000 -28 +30 -28000 +30000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -64217,7 +91961,7 @@ SLCR_LOCK -28000 +30000 ARM PLL Control @@ -64861,10 +92605,10 @@ SLCR_LOCK 3f00 -2 +4 -200 +400 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -64984,7 +92728,7 @@ SLCR_LOCK -1f000200 +1f000400 CORTEX A9 Clock Control @@ -65069,10 +92813,10 @@ SLCR_LOCK f0 -2 +c -20 +c0 Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control @@ -65089,10 +92833,10 @@ SLCR_LOCK f00 -2 +3 -200 +300 Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control @@ -65109,10 +92853,10 @@ SLCR_LOCK 3ff000 -12c +fa -12c000 +fa000 Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. @@ -65132,7 +92876,7 @@ SLCR_LOCK -12c220 +fa3c0 DDR PLL Configuration @@ -65217,10 +92961,10 @@ SLCR_LOCK 7f000 -20 +2a -20000 +2a000 Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. @@ -65240,7 +92984,7 @@ SLCR_LOCK -20000 +2a000 DDR PLL Control @@ -65904,10 +93648,10 @@ SLCR_LOCK 3f00000 -2 +4 -200000 +400000 Divisor value for the ddr_3xclk @@ -65924,10 +93668,10 @@ SLCR_LOCK fc000000 -3 +6 -c000000 +18000000 Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) @@ -65947,7 +93691,7 @@ SLCR_LOCK -c200003 +18400003 DDR Clock Control @@ -67310,10 +95054,10 @@ SLCR_LOCK 3f00 -f +2e -f00 +2e00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. @@ -67330,10 +95074,10 @@ SLCR_LOCK 3f00000 -7 +3 -700000 +300000 Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider @@ -67353,7 +95097,7 @@ SLCR_LOCK -700f01 +302e01 DCI clock control @@ -67939,10 +95683,10 @@ SLCR_LOCK 3f00 -5 +8 -500 +800 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -67982,7 +95726,7 @@ SLCR_LOCK -400500 +400800 FPGA 0 Output Clock Control @@ -70764,10 +98508,10 @@ ddrc_ctrl fff -82 +55 -82 +55 tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. @@ -70927,7 +98671,7 @@ ddrc_ctrl -81082 +81055 Two rank configuration register @@ -71452,10 +99196,10 @@ ddrc_ctrl 3f -1b +12 -1b +12 tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. @@ -71472,10 +99216,10 @@ ddrc_ctrl 3fc0 -a1 +69 -2840 +1a40 tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. @@ -71515,7 +99259,7 @@ ddrc_ctrl -4285b +41a52 DRAM Parameters register 0 @@ -71599,10 +99343,10 @@ ddrc_ctrl 1f -13 +10 -13 +10 Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. @@ -71639,10 +99383,10 @@ ddrc_ctrl fc00 -16 +e -5800 +3800 tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. @@ -71659,10 +99403,10 @@ ddrc_ctrl 3f0000 -24 +17 -240000 +170000 tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. @@ -71679,10 +99423,10 @@ ddrc_ctrl 7c00000 -13 +d -4c00000 +3400000 tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. @@ -71722,7 +99466,7 @@ ddrc_ctrl -44e458d3 +435738d0 DRAM Parameters register 1 @@ -71846,10 +99590,10 @@ ddrc_ctrl 7c00 -f +e -3c00 +3800 Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. @@ -71866,10 +99610,10 @@ ddrc_ctrl f8000 -5 +3 -28000 +18000 tXP: Minimum time after power down exit to any operation. DRAM RELATED. @@ -71906,10 +99650,10 @@ ddrc_ctrl f800000 -5 +4 -2800000 +2000000 Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED @@ -71949,7 +99693,7 @@ ddrc_ctrl -7282bce5 +7201b8e5 DRAM Parameters register 2 @@ -72053,10 +99797,10 @@ ddrc_ctrl e0 -6 +4 -c0 +80 tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED @@ -72276,7 +100020,7 @@ ddrc_ctrl -272872d0 +27287290 DRAM Parameters register 3 @@ -72901,10 +100645,10 @@ ddrc_ctrl ffff -b30 +530 -b30 +530 Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register @@ -72944,7 +100688,7 @@ ddrc_ctrl -40b30 +40530 DRAM EMR, MR access register @@ -73048,10 +100792,10 @@ ddrc_ctrl 3ff0 -16d +f0 -16d0 +f00 Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) @@ -73111,7 +100855,7 @@ ddrc_ctrl -116d4 +10f04 DRAM burst 8 read/write register @@ -75913,10 +103657,10 @@ ddrc_ctrl fffff -cb73 +8583 -cb73 +8583 Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. @@ -75933,10 +103677,10 @@ ddrc_ctrl ff00000 -69 +45 -6900000 +4500000 Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. @@ -75956,7 +103700,7 @@ ddrc_ctrl -690cb73 +4508583 Misc parameters register @@ -76060,10 +103804,10 @@ ddrc_ctrl 1fe -ff +ab -1fe +156 Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. @@ -76083,7 +103827,7 @@ ddrc_ctrl -1fe +156 Deep powerdown register @@ -78518,10 +106262,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78541,7 +106285,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78645,10 +106389,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78668,7 +106412,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78772,10 +106516,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78795,7 +106539,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -78899,10 +106643,10 @@ ddrc_ctrl ffc00 -a4 +8c -29000 +23000 The user programmable init ratio used Gate Leveling FSM @@ -78922,7 +106666,7 @@ ddrc_ctrl -29000 +23000 PHY init ratio register for data slice 0. @@ -80182,10 +107926,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80245,7 +107989,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80329,10 +108073,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80392,7 +108136,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80476,10 +108220,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80539,7 +108283,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -80623,10 +108367,10 @@ ddrc_ctrl 7ff -f9 +e1 -f9 +e1 Ratio value to be used when fifo_we_X_force_mode is set to 0. @@ -80686,7 +108430,7 @@ ddrc_ctrl -f9 +e1 PHY fifo write enable configuration register for data slice 0. @@ -83909,10 +111653,10 @@ ddrc_ctrl ff0 -12 +c -120 +c0 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. @@ -83952,7 +111696,7 @@ ddrc_ctrl -5125 +50c5 LPDDR2 Control 2 Register @@ -84036,10 +111780,10 @@ ddrc_ctrl ff -a8 +6f -a8 +6f Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. @@ -84056,10 +111800,10 @@ ddrc_ctrl 3ff00 -12 +c -1200 +c00 ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. @@ -84079,7 +111823,7 @@ ddrc_ctrl -12a8 +c6f LPDDR2 Control 3 Register @@ -84929,6 +112673,270 @@ DDRIOB_DCI_CTRL
+ +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
+ +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
+ +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
+ +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
+ +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
+ +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
+ +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
+ +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
+ +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
+ +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
+ +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
+ +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
MIO_PIN_12 @@ -84973,6 +112981,50 @@ MIO_PIN_13
+ +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
+ +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
MIO_PIN_16 @@ -85039,6 +113091,50 @@ MIO_PIN_18
+ +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
+ +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
MIO_PIN_21 @@ -85061,6 +113157,710 @@ MIO_PIN_21
+ +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
+ +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
+ +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
+ +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
+ +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
+ +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
+ +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
+ +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
+ +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
+ +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
+ +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
+ +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
+ +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
+ +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
+ +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
+ +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
+ +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
+ +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
+ +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
+ +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
+ +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
+ +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
+ +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
+ +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
+ +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
+ +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
+ +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
+ +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
+ +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
+ +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
+ +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
+ +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
SLCR_LOCK @@ -88863,6 +117663,3210 @@ SLCR_LOCK

MIO PROGRAMMING

+

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
+

+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 1 +
+

+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 2 +
+

+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 3 +
+

+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 4 +
+

+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 5 +
+

+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 6 +
+

+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
+

+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
+

+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
+

+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
+

+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

@@ -89397,6 +121401,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
+

+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

@@ -90198,6 +122736,540 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 19 +
+

+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +5 + +a0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +16a0 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

@@ -90465,6 +123537,8550 @@ SLCR_LOCK

+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 22 +
+

+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 23 +
+

+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 24 +
+

+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 25 +
+

+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 26 +
+

+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 27 +
+

+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 28 +
+

+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 29 +
+

+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 30 +
+

+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 31 +
+

+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 32 +
+

+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 33 +
+

+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 34 +
+

+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 35 +
+

+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 36 +
+

+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 37 +
+

+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 38 +
+

+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 39 +
+

+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 40 +
+

+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 41 +
+

+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 42 +
+

+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 43 +
+

+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 44 +
+

+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 45 +
+

+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 46 +
+

+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 47 +
+

+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 48 +
+

+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 49 +
+

+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 50 +
+

+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 51 +
+

+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 52 +
+

+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +
+Register Name + +Address + +Width + +Type + +Reset Value + +Description +
+MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 53 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl index f05eec4..b54cbac 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl @@ -1,21 +1,21 @@ proc ps7_pll_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} { } proc ps7_clock_init_data_3_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006004 0x0007FFFF 0x00001055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} { mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_3_0 {} { @@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} { } proc ps7_pll_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} { } proc ps7_clock_init_data_2_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF800606C 0x0000FFFF 0x00001610 - mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF8006078 0x03FFFFFF 0x00455111 mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_2_0 {} { @@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} { } proc ps7_pll_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000110 0x003FFFF0 0x000FA220 - mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000110 0x003FFFF0 0x000FA240 + mask_write 0XF8000100 0x0007F000 0x00030000 mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000001 mask_write 0XF8000100 0x00000010 0x00000000 - mask_write 0XF8000120 0x1F003F30 0x1F000200 - mask_write 0XF8000114 0x003FFFF0 0x0012C220 - mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000120 0x1F003F30 0x1F000400 + mask_write 0XF8000114 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000104 0x0007F000 0x0002A000 mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000000 mask_poll 0XF800010C 0x00000002 mask_write 0XF8000104 0x00000010 0x00000000 - mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000124 0xFFF00003 0x18400003 mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x00000010 0x00000010 @@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} { } proc ps7_clock_init_data_1_0 {} { mwr -force 0XF8000008 0x0000DF0D - mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000128 0x03F03F01 0x00302E01 mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 - mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000170 0x03F03F30 0x00400800 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x016C400D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006000 0x0001FFFF 0x00000084 - mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006004 0x1FFFFFFF 0x00081055 mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF8006010 0x03FFFFFF 0x00014001 - mask_write 0XF8006014 0x001FFFFF 0x0004285B - mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 - mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 - mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006014 0x001FFFFF 0x00041A52 + mask_write 0XF8006018 0xF7FFFFFF 0x435738D0 + mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF800602C 0xFFFFFFFF 0x00000008 - mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 - mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006030 0xFFFFFFFF 0x00040530 + mask_write 0XF8006034 0x13FF3FFF 0x00010F04 mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 @@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 - mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 - mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060A8 0x0FFFFFFF 0x04508583 + mask_write 0XF80060AC 0x000001FF 0x00000156 mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 @@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000 - mask_write 0XF800612C 0x000FFFFF 0x00029000 - mask_write 0XF8006130 0x000FFFFF 0x00029000 - mask_write 0XF8006134 0x000FFFFF 0x00029000 - mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF800612C 0x000FFFFF 0x00023000 + mask_write 0XF8006130 0x000FFFFF 0x00023000 + mask_write 0XF8006134 0x000FFFFF 0x00023000 + mask_write 0XF8006138 0x000FFFFF 0x00023000 mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035 @@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080 - mask_write 0XF8006168 0x001FFFFF 0x000000F9 - mask_write 0XF800616C 0x001FFFFF 0x000000F9 - mask_write 0XF8006170 0x001FFFFF 0x000000F9 - mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF8006168 0x001FFFFF 0x000000E1 + mask_write 0XF800616C 0x001FFFFF 0x000000E1 + mask_write 0XF8006170 0x001FFFFF 0x000000E1 + mask_write 0XF8006174 0x001FFFFF 0x000000E1 mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0 @@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 - mask_write 0XF80062B0 0x003FFFFF 0x00005125 - mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_write 0XF80062B0 0x003FFFFF 0x000050C5 + mask_write 0XF80062B4 0x0003FFFF 0x00000C6F mask_poll 0XF8000B74 0x00002000 mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_poll 0XF8006054 0x00000007 @@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} { mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001600 + mask_write 0XF8000708 0x00003FFF 0x00000600 + mask_write 0XF800070C 0x00003FFF 0x00000600 + mask_write 0XF8000710 0x00003FFF 0x00000600 + mask_write 0XF8000714 0x00003FFF 0x00000600 + mask_write 0XF8000718 0x00003FFF 0x00000600 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000734 0x00003FFF 0x000016E1 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0 + mask_write 0XF800074C 0x00003FFF 0x000016A0 + mask_write 0XF8000750 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0 + mask_write 0XF8000758 0x00003FFF 0x00001600 + mask_write 0XF800075C 0x00003FFF 0x00001600 + mask_write 0XF8000760 0x00003FFF 0x00001600 + mask_write 0XF8000764 0x00003FFF 0x00001600 + mask_write 0XF8000768 0x00003FFF 0x00001600 + mask_write 0XF800076C 0x00003FFF 0x00001600 + mask_write 0XF8000770 0x00003FFF 0x00001600 + mask_write 0XF8000774 0x00003FFF 0x00001600 + mask_write 0XF8000778 0x00003FFF 0x00001600 + mask_write 0XF800077C 0x00003FFF 0x00001600 + mask_write 0XF8000780 0x00003FFF 0x00001600 + mask_write 0XF8000784 0x00003FFF 0x00001600 + mask_write 0XF8000788 0x00003FFF 0x00001600 + mask_write 0XF800078C 0x00003FFF 0x00001600 + mask_write 0XF8000790 0x00003FFF 0x00001600 + mask_write 0XF8000794 0x00003FFF 0x00001600 + mask_write 0XF8000798 0x00003FFF 0x00001600 + mask_write 0XF800079C 0x00003FFF 0x00001600 + mask_write 0XF80007A0 0x00003FFF 0x00001600 + mask_write 0XF80007A4 0x00003FFF 0x00001600 + mask_write 0XF80007A8 0x00003FFF 0x00001600 + mask_write 0XF80007AC 0x00003FFF 0x00001600 + mask_write 0XF80007B0 0x00003FFF 0x00001600 + mask_write 0XF80007B4 0x00003FFF 0x00001600 + mask_write 0XF80007B8 0x00003FFF 0x00001600 + mask_write 0XF80007BC 0x00003FFF 0x00001600 + mask_write 0XF80007C0 0x00003FFF 0x00001600 + mask_write 0XF80007C4 0x00003FFF 0x00001600 + mask_write 0XF80007C8 0x00003FFF 0x00001600 + mask_write 0XF80007CC 0x00003FFF 0x00001600 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 mwr -force 0XF8000004 0x0000767B } proc ps7_peripherals_init_data_1_0 {} { @@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} { set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_3_0 "0x2" -set APU_FREQ 666666666 +set APU_FREQ 400000000 diff --git a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init_gpl.h b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init_gpl.h index 01bde91..5477b32 100644 --- a/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init_gpl.h +++ b/project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init_gpl.h @@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158730 +#define APU_FREQ 400000000 +#define DDR_FREQ 350000000 +#define DCI_FREQ 10144927 #define QSPI_FREQ 10000000 #define SMC_FREQ 10000000 #define ENET0_FREQ 10000000 @@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data; #define SDIO_FREQ 10000000 #define UART_FREQ 100000000 #define SPI_FREQ 166666672 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 +#define I2C_FREQ 66666664 +#define WDT_FREQ 66666672 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 +#define FPGA0_FREQ 10000000 #define FPGA1_FREQ 10000000 #define FPGA2_FREQ 10000000 #define FPGA3_FREQ 10000000 diff --git a/project_1/project_1.runs/.jobs/vrs_config_10.xml b/project_1/project_1.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_11.xml b/project_1/project_1.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..dcec4ed --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_12.xml b/project_1/project_1.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_13.xml b/project_1/project_1.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_14.xml b/project_1/project_1.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_15.xml b/project_1/project_1.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..dcec4ed --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_16.xml b/project_1/project_1.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..304b8c6 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_17.xml b/project_1/project_1.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_18.xml b/project_1/project_1.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_19.xml b/project_1/project_1.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_20.xml b/project_1/project_1.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_21.xml b/project_1/project_1.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..9b0a49f --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_22.xml b/project_1/project_1.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..dcec4ed --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_23.xml b/project_1/project_1.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_24.xml b/project_1/project_1.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_25.xml b/project_1/project_1.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..dcec4ed --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_26.xml b/project_1/project_1.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_26.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_27.xml b/project_1/project_1.runs/.jobs/vrs_config_27.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_28.xml b/project_1/project_1.runs/.jobs/vrs_config_28.xml new file mode 100644 index 0000000..9b0a49f --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_29.xml b/project_1/project_1.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_3.xml b/project_1/project_1.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_30.xml b/project_1/project_1.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_31.xml b/project_1/project_1.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..dcec4ed --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_32.xml b/project_1/project_1.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..304b8c6 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_33.xml b/project_1/project_1.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..6b3d129 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_34.xml b/project_1/project_1.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_35.xml b/project_1/project_1.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_36.xml b/project_1/project_1.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_37.xml b/project_1/project_1.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_38.xml b/project_1/project_1.runs/.jobs/vrs_config_38.xml new file mode 100644 index 0000000..304b8c6 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_38.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_39.xml b/project_1/project_1.runs/.jobs/vrs_config_39.xml new file mode 100644 index 0000000..6b3d129 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_39.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_4.xml b/project_1/project_1.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_40.xml b/project_1/project_1.runs/.jobs/vrs_config_40.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_40.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_41.xml b/project_1/project_1.runs/.jobs/vrs_config_41.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_41.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_42.xml b/project_1/project_1.runs/.jobs/vrs_config_42.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_42.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_43.xml b/project_1/project_1.runs/.jobs/vrs_config_43.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_44.xml b/project_1/project_1.runs/.jobs/vrs_config_44.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_5.xml b/project_1/project_1.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_6.xml b/project_1/project_1.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..ac9fab3 --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_7.xml b/project_1/project_1.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_8.xml b/project_1/project_1.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..f26b2fc --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/project_1/project_1.runs/.jobs/vrs_config_9.xml b/project_1/project_1.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..266fbee --- /dev/null +++ b/project_1/project_1.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.Xil/design_1_processing_system7_0_0_propImpl.xdc b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.Xil/design_1_processing_system7_0_0_propImpl.xdc index b9cef4e..e096d46 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.Xil/design_1_processing_system7_0_0_propImpl.xdc +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.Xil/design_1_processing_system7_0_0_propImpl.xdc @@ -1,168 +1,262 @@ set_property SRC_FILE_INFO {cfile:d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc rfile:../../../project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design] current_instance inst -set_property src_info {type:SCOPED_XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_input_jitter clk_fpga_0 0.6 -set_property src_info {type:SCOPED_XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] -set_property src_info {type:SCOPED_XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] -set_property src_info {type:SCOPED_XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"] -set_property src_info {type:SCOPED_XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"] -set_property src_info {type:SCOPED_XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] -set_property src_info {type:SCOPED_XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"] -set_property src_info {type:SCOPED_XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] -set_property src_info {type:SCOPED_XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"] -set_property src_info {type:SCOPED_XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"] +set_property src_info {type:SCOPED_XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"] +set_property src_info {type:SCOPED_XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"] +set_property src_info {type:SCOPED_XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"] +set_property src_info {type:SCOPED_XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"] +set_property src_info {type:SCOPED_XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"] +set_property src_info {type:SCOPED_XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"] +set_property src_info {type:SCOPED_XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"] +set_property src_info {type:SCOPED_XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"] set_property src_info {type:SCOPED_XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"] -set_property src_info {type:SCOPED_XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"] -set_property src_info {type:SCOPED_XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"] -set_property src_info {type:SCOPED_XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"] -set_property src_info {type:SCOPED_XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"] -set_property src_info {type:SCOPED_XDC file:1 line:110 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] -set_property src_info {type:SCOPED_XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"] +set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"] +set_property src_info {type:SCOPED_XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"] +set_property src_info {type:SCOPED_XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"] +set_property src_info {type:SCOPED_XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"] +set_property src_info {type:SCOPED_XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"] set_property src_info {type:SCOPED_XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"] -set_property src_info {type:SCOPED_XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"] -set_property src_info {type:SCOPED_XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"] -set_property src_info {type:SCOPED_XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"] +set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"] +set_property src_info {type:SCOPED_XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"] +set_property src_info {type:SCOPED_XDC file:1 line:133 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"] set_property src_info {type:SCOPED_XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"] -set_property src_info {type:SCOPED_XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"] -set_property src_info {type:SCOPED_XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"] -set_property src_info {type:SCOPED_XDC file:1 line:152 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"] -set_property src_info {type:SCOPED_XDC file:1 line:156 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"] -set_property src_info {type:SCOPED_XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"] -set_property src_info {type:SCOPED_XDC file:1 line:165 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"] -set_property src_info {type:SCOPED_XDC file:1 line:170 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:174 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"] -set_property src_info {type:SCOPED_XDC file:1 line:179 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"] -set_property src_info {type:SCOPED_XDC file:1 line:184 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"] +set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"] +set_property src_info {type:SCOPED_XDC file:1 line:147 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"] +set_property src_info {type:SCOPED_XDC file:1 line:154 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"] +set_property src_info {type:SCOPED_XDC file:1 line:161 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"] +set_property src_info {type:SCOPED_XDC file:1 line:168 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"] +set_property src_info {type:SCOPED_XDC file:1 line:175 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"] +set_property src_info {type:SCOPED_XDC file:1 line:182 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"] set_property src_info {type:SCOPED_XDC file:1 line:189 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"] -set_property src_info {type:SCOPED_XDC file:1 line:194 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"] -set_property src_info {type:SCOPED_XDC file:1 line:199 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"] -set_property src_info {type:SCOPED_XDC file:1 line:204 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"] -set_property src_info {type:SCOPED_XDC file:1 line:209 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"] -set_property src_info {type:SCOPED_XDC file:1 line:214 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"] -set_property src_info {type:SCOPED_XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"] +set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"] +set_property src_info {type:SCOPED_XDC file:1 line:196 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"] +set_property src_info {type:SCOPED_XDC file:1 line:203 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"] +set_property src_info {type:SCOPED_XDC file:1 line:210 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"] +set_property src_info {type:SCOPED_XDC file:1 line:217 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"] set_property src_info {type:SCOPED_XDC file:1 line:224 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"] -set_property src_info {type:SCOPED_XDC file:1 line:228 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"] -set_property src_info {type:SCOPED_XDC file:1 line:233 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"] +set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"] +set_property src_info {type:SCOPED_XDC file:1 line:231 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"] set_property src_info {type:SCOPED_XDC file:1 line:238 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"] -set_property src_info {type:SCOPED_XDC file:1 line:243 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"] -set_property src_info {type:SCOPED_XDC file:1 line:248 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"] +set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"] +set_property src_info {type:SCOPED_XDC file:1 line:245 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"] set_property src_info {type:SCOPED_XDC file:1 line:252 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"] -set_property src_info {type:SCOPED_XDC file:1 line:256 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"] -set_property src_info {type:SCOPED_XDC file:1 line:260 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"] -set_property src_info {type:SCOPED_XDC file:1 line:264 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"] -set_property src_info {type:SCOPED_XDC file:1 line:268 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"] -set_property src_info {type:SCOPED_XDC file:1 line:272 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"] -set_property src_info {type:SCOPED_XDC file:1 line:276 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"] -set_property src_info {type:SCOPED_XDC file:1 line:281 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:286 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"] -set_property src_info {type:SCOPED_XDC file:1 line:290 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"] +set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] +set_property src_info {type:SCOPED_XDC file:1 line:259 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"] +set_property src_info {type:SCOPED_XDC file:1 line:266 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"] +set_property src_info {type:SCOPED_XDC file:1 line:273 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] +set_property src_info {type:SCOPED_XDC file:1 line:280 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"] +set_property src_info {type:SCOPED_XDC file:1 line:287 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"] set_property src_info {type:SCOPED_XDC file:1 line:294 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"] -set_property src_info {type:SCOPED_XDC file:1 line:298 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"] -set_property src_info {type:SCOPED_XDC file:1 line:302 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"] -set_property src_info {type:SCOPED_XDC file:1 line:306 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"] -set_property src_info {type:SCOPED_XDC file:1 line:310 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"] -set_property src_info {type:SCOPED_XDC file:1 line:314 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:318 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"] +set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"] +set_property src_info {type:SCOPED_XDC file:1 line:301 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"] +set_property src_info {type:SCOPED_XDC file:1 line:308 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] +set_property src_info {type:SCOPED_XDC file:1 line:315 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"] set_property src_info {type:SCOPED_XDC file:1 line:322 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"] -set_property src_info {type:SCOPED_XDC file:1 line:326 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"] -set_property src_info {type:SCOPED_XDC file:1 line:330 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"] -set_property src_info {type:SCOPED_XDC file:1 line:334 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"] -set_property src_info {type:SCOPED_XDC file:1 line:338 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"] -set_property src_info {type:SCOPED_XDC file:1 line:342 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"] -set_property src_info {type:SCOPED_XDC file:1 line:346 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"] -set_property src_info {type:SCOPED_XDC file:1 line:350 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"] -set_property src_info {type:SCOPED_XDC file:1 line:354 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"] -set_property src_info {type:SCOPED_XDC file:1 line:358 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"] -set_property src_info {type:SCOPED_XDC file:1 line:362 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"] -set_property src_info {type:SCOPED_XDC file:1 line:366 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"] -set_property src_info {type:SCOPED_XDC file:1 line:370 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"] -set_property src_info {type:SCOPED_XDC file:1 line:374 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"] -set_property src_info {type:SCOPED_XDC file:1 line:378 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"] -set_property src_info {type:SCOPED_XDC file:1 line:382 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"] -set_property src_info {type:SCOPED_XDC file:1 line:386 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"] -set_property src_info {type:SCOPED_XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"] +set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"] +set_property src_info {type:SCOPED_XDC file:1 line:329 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"] +set_property src_info {type:SCOPED_XDC file:1 line:336 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"] +set_property src_info {type:SCOPED_XDC file:1 line:343 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"] +set_property src_info {type:SCOPED_XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"] +set_property src_info {type:SCOPED_XDC file:1 line:355 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"] +set_property src_info {type:SCOPED_XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"] +set_property src_info {type:SCOPED_XDC file:1 line:367 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"] +set_property src_info {type:SCOPED_XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:379 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"] set_property src_info {type:SCOPED_XDC file:1 line:392 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:398 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] +set_property src_info {type:SCOPED_XDC file:1 line:402 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"] +set_property src_info {type:SCOPED_XDC file:1 line:406 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"] +set_property src_info {type:SCOPED_XDC file:1 line:410 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"] +set_property src_info {type:SCOPED_XDC file:1 line:414 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"] +set_property src_info {type:SCOPED_XDC file:1 line:418 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"] +set_property src_info {type:SCOPED_XDC file:1 line:422 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:427 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:432 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:436 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:440 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:445 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:450 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:454 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:458 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"] +set_property src_info {type:SCOPED_XDC file:1 line:462 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"] +set_property src_info {type:SCOPED_XDC file:1 line:466 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"] +set_property src_info {type:SCOPED_XDC file:1 line:470 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"] +set_property src_info {type:SCOPED_XDC file:1 line:474 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"] +set_property src_info {type:SCOPED_XDC file:1 line:478 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"] +set_property src_info {type:SCOPED_XDC file:1 line:482 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:486 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"] +set_property src_info {type:SCOPED_XDC file:1 line:491 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"] +set_property src_info {type:SCOPED_XDC file:1 line:496 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:500 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"] +set_property src_info {type:SCOPED_XDC file:1 line:505 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"] +set_property src_info {type:SCOPED_XDC file:1 line:510 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"] +set_property src_info {type:SCOPED_XDC file:1 line:515 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"] +set_property src_info {type:SCOPED_XDC file:1 line:520 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"] +set_property src_info {type:SCOPED_XDC file:1 line:525 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"] +set_property src_info {type:SCOPED_XDC file:1 line:530 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"] +set_property src_info {type:SCOPED_XDC file:1 line:535 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"] +set_property src_info {type:SCOPED_XDC file:1 line:540 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"] +set_property src_info {type:SCOPED_XDC file:1 line:545 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"] +set_property src_info {type:SCOPED_XDC file:1 line:550 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:554 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"] +set_property src_info {type:SCOPED_XDC file:1 line:559 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"] +set_property src_info {type:SCOPED_XDC file:1 line:564 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"] +set_property src_info {type:SCOPED_XDC file:1 line:569 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"] +set_property src_info {type:SCOPED_XDC file:1 line:574 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"] +set_property src_info {type:SCOPED_XDC file:1 line:578 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"] +set_property src_info {type:SCOPED_XDC file:1 line:582 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"] +set_property src_info {type:SCOPED_XDC file:1 line:586 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"] +set_property src_info {type:SCOPED_XDC file:1 line:590 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"] +set_property src_info {type:SCOPED_XDC file:1 line:594 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"] +set_property src_info {type:SCOPED_XDC file:1 line:598 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:602 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:607 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:612 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:616 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:620 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"] +set_property src_info {type:SCOPED_XDC file:1 line:624 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"] +set_property src_info {type:SCOPED_XDC file:1 line:628 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"] +set_property src_info {type:SCOPED_XDC file:1 line:632 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"] +set_property src_info {type:SCOPED_XDC file:1 line:636 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"] +set_property src_info {type:SCOPED_XDC file:1 line:640 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:644 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:648 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:652 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"] +set_property src_info {type:SCOPED_XDC file:1 line:656 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"] +set_property src_info {type:SCOPED_XDC file:1 line:660 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"] +set_property src_info {type:SCOPED_XDC file:1 line:664 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"] +set_property src_info {type:SCOPED_XDC file:1 line:668 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"] +set_property src_info {type:SCOPED_XDC file:1 line:672 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"] +set_property src_info {type:SCOPED_XDC file:1 line:676 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"] +set_property src_info {type:SCOPED_XDC file:1 line:680 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"] +set_property src_info {type:SCOPED_XDC file:1 line:684 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"] +set_property src_info {type:SCOPED_XDC file:1 line:688 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"] +set_property src_info {type:SCOPED_XDC file:1 line:692 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"] +set_property src_info {type:SCOPED_XDC file:1 line:696 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"] +set_property src_info {type:SCOPED_XDC file:1 line:700 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"] +set_property src_info {type:SCOPED_XDC file:1 line:704 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"] +set_property src_info {type:SCOPED_XDC file:1 line:708 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"] +set_property src_info {type:SCOPED_XDC file:1 line:712 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"] +set_property src_info {type:SCOPED_XDC file:1 line:715 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"] +set_property src_info {type:SCOPED_XDC file:1 line:718 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"] diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.vivado.begin.rst b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.vivado.begin.rst index 944b765..4b1fe3b 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.vivado.begin.rst +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp index 8d6a2fa..b44361e 100644 Binary files a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp and b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp differ diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.tcl b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.tcl index fa1fad3..9287ed2 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.tcl +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.tcl @@ -70,6 +70,8 @@ proc create_report { reportName command } { } } OPTRACE "design_1_processing_system7_0_0_synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 3 +set_param xicom.use_bs_reader 1 set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run OPTRACE "Creating in-memory project" START { } @@ -87,7 +89,7 @@ set_property ip_output_repo d:/project/hdl/zynq_lvgl/project_1/project_1.cache/i set_property ip_cache_permissions {read write} [current_project] OPTRACE "Creating in-memory project" END { } OPTRACE "Adding files" START { } -read_ip -quiet d:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci +read_ip -quiet D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci set_property used_in_implementation false [get_files -all d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] OPTRACE "Adding files" END { } diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds index faa44cd..83e49e8 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 21:34:31 2024 -# Process ID: 65888 +# Start of session at: Fri Oct 25 01:47:05 2024 +# Process ID: 228936 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1 # Command line: vivado.exe -log design_1_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_processing_system7_0_0.tcl # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds @@ -11,6 +11,7 @@ # Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB #----------------------------------------------------------- source design_1_processing_system7_0_0.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 374.160 ; gain = 62.629 Command: synth_design -top design_1_processing_system7_0_0 -part xc7z010clg400-1 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' @@ -18,34 +19,32 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 48220 +INFO: [Synth 8-7075] Helper process launched with PID 231912 INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1208.160 ; gain = 413.414 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1208.879 ; gain = 412.934 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -INFO: [Synth 8-6157] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082] -INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082] INFO: [Synth 8-6157] synthesizing module 'BIBUF' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:729] INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:729] INFO: [Synth 8-6157] synthesizing module 'PS7' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:109424] INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:109424] INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] +WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:53] WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load @@ -127,18 +126,18 @@ WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[2] in module processing_system7_v WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1306.793 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -151,32 +150,32 @@ Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_pro Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1326.699 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1326.699 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Designutils 20-5008] Incremental synthesis strategy off INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -221,25 +220,25 @@ WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5 WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1426.195 ; gain = 631.449 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1435.078 ; gain = 639.133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1446.109 ; gain = 651.363 +Finished Timing Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1435.297 ; gain = 639.352 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1457.562 ; gain = 662.816 +Finished Technology Mapping : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1454.469 ; gain = 658.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -257,37 +256,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -304,29 +303,28 @@ Report Cell Usage: | |Cell |Count | +------+------+------+ |1 |BIBUF | 130| -|2 |BUFG | 1| -|3 |LUT1 | 24| -|4 |PS7 | 1| +|2 |LUT1 | 24| +|3 |PS7 | 1| +------+------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 80 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1464.770 ; gain = 649.805 -Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 1461.738 ; gain = 665.793 +Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1464.770 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1461.738 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1487.992 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1489.543 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 665ebd95 +Synth Design complete, checksum: 7b0246e2 INFO: [Common 17-83] Releasing license: Synthesis -27 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. +25 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1487.992 ; gain = 1073.133 +synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:42 . Memory (MB): peak = 1489.543 ; gain = 1075.207 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file design_1_processing_system7_0_0_utilization_synth.rpt -pb design_1_processing_system7_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 21:35:16 2024... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:47:57 2024... diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.pb b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.pb index 0c1af24..32b5ff9 100644 Binary files a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.pb and b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.pb differ diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.rpt b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.rpt index bc2aab1..c42cf1b 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.rpt +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 21:35:16 2024 +| Date : Fri Oct 25 01:47:57 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_utilization -file design_1_processing_system7_0_0_utilization_synth.rpt -pb design_1_processing_system7_0_0_utilization_synth.pb | Design : design_1_processing_system7_0_0 @@ -115,7 +115,7 @@ Warning! LUT value is adjusted to account for LUT combining. +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | | BUFIO | 0 | 0 | 0 | 8 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 | @@ -151,7 +151,6 @@ Warning! LUT value is adjusted to account for LUT combining. | BIBUF | 130 | IO | | LUT1 | 24 | LUT | | PS7 | 1 | Specialized Resource | -| BUFG | 1 | Clock | +----------+------+----------------------+ diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc index 11af5e5..2eb614c 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc @@ -1,14 +1,14 @@ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. -# IP: d:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci +# IP: D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci # IP: The module: 'design_1_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc # XDC: The top module name and the constraint reference have the same name: 'design_1_processing_system7_0_0'. Do not add the DONT_TOUCH constraint. set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet -# IP: d:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci +# IP: D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci # IP: The module: 'design_1_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint. # XDC: d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/gen_run.xml b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/gen_run.xml index a9f64fc..d777b23 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/gen_run.xml +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -12,6 +12,7 @@ + @@ -25,6 +26,7 @@ + @@ -37,14 +39,20 @@ + + + + + + + + - - Vivado Synthesis Defaults - + diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/project.wdf b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/project.wdf index ed061fb..b173ce0 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/project.wdf +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/project.wdf @@ -1,6 +1,6 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 @@ -21,12 +21,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3138:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3138:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3534626431336132626430633430393761313364643966646636616461613737:506172656e742050412070726f6a656374204944:00 -eof:1062151599 +eof:2971538641 diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/runme.log b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/runme.log index 709d024..4878dd9 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/runme.log +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/runme.log @@ -10,6 +10,7 @@ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source design_1_processing_system7_0_0.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 374.160 ; gain = 62.629 Command: synth_design -top design_1_processing_system7_0_0 -part xc7z010clg400-1 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' @@ -17,34 +18,32 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 48220 +INFO: [Synth 8-7075] Helper process launched with PID 231912 INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1208.160 ; gain = 413.414 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1208.879 ; gain = 412.934 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -INFO: [Synth 8-6157] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082] -INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082] INFO: [Synth 8-6157] synthesizing module 'BIBUF' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:729] INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:729] INFO: [Synth 8-6157] synthesizing module 'PS7' [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:109424] INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [C:/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:109424] INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] -WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:194] +WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] +WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:186] INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v:53] WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load @@ -126,18 +125,18 @@ WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[2] in module processing_system7_v WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.480 ; gain = 511.734 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1306.793 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -150,32 +149,32 @@ Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_pro Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1326.699 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1326.699 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1306.309 ; gain = 0.000 INFO: [Designutils 20-5008] Incremental synthesis strategy off INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -220,25 +219,25 @@ WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5 WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1326.699 ; gain = 531.953 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.309 ; gain = 510.363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1426.195 ; gain = 631.449 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1435.078 ; gain = 639.133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1446.109 ; gain = 651.363 +Finished Timing Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1435.297 ; gain = 639.352 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1457.562 ; gain = 662.816 +Finished Technology Mapping : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1454.469 ; gain = 658.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -256,37 +255,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -303,29 +302,28 @@ Report Cell Usage: | |Cell |Count | +------+------+------+ |1 |BIBUF | 130| -|2 |BUFG | 1| -|3 |LUT1 | 24| -|4 |PS7 | 1| +|2 |LUT1 | 24| +|3 |PS7 | 1| +------+------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 80 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1464.770 ; gain = 649.805 -Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1464.770 ; gain = 670.023 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 1461.738 ; gain = 665.793 +Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 1461.738 ; gain = 665.793 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1464.770 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1461.738 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1487.992 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1489.543 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 665ebd95 +Synth Design complete, checksum: 7b0246e2 INFO: [Common 17-83] Releasing license: Synthesis -27 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. +25 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1487.992 ; gain = 1073.133 +synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:42 . Memory (MB): peak = 1489.543 ; gain = 1075.207 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file design_1_processing_system7_0_0_utilization_synth.rpt -pb design_1_processing_system7_0_0_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 21:35:16 2024... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:47:57 2024... diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.jou b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.jou index 53122e2..5ef92bf 100644 --- a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.jou +++ b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 21:34:31 2024 -# Process ID: 65888 +# Start of session at: Fri Oct 25 01:47:05 2024 +# Process ID: 228936 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1 # Command line: vivado.exe -log design_1_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_processing_system7_0_0.tcl # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/design_1_processing_system7_0_0.vds diff --git a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.pb b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.pb index 93296c7..e51a987 100644 Binary files a/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.pb and b/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1/vivado.pb differ diff --git a/project_1/project_1.runs/impl_1/.init_design.begin.rst b/project_1/project_1.runs/impl_1/.init_design.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.init_design.begin.rst +++ b/project_1/project_1.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.opt_design.begin.rst b/project_1/project_1.runs/impl_1/.opt_design.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.opt_design.begin.rst +++ b/project_1/project_1.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.phys_opt_design.begin.rst b/project_1/project_1.runs/impl_1/.phys_opt_design.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.phys_opt_design.begin.rst +++ b/project_1/project_1.runs/impl_1/.phys_opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.place_design.begin.rst b/project_1/project_1.runs/impl_1/.place_design.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.place_design.begin.rst +++ b/project_1/project_1.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.route_design.begin.rst b/project_1/project_1.runs/impl_1/.route_design.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.route_design.begin.rst +++ b/project_1/project_1.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.vivado.begin.rst b/project_1/project_1.runs/impl_1/.vivado.begin.rst index d18c145..93fd18c 100644 --- a/project_1/project_1.runs/impl_1/.vivado.begin.rst +++ b/project_1/project_1.runs/impl_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/.write_bitstream.begin.rst b/project_1/project_1.runs/impl_1/.write_bitstream.begin.rst index dadaef1..5012472 100644 --- a/project_1/project_1.runs/impl_1/.write_bitstream.begin.rst +++ b/project_1/project_1.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper.bit b/project_1/project_1.runs/impl_1/design_1_wrapper.bit index fbe17cf..962e936 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper.bit and b/project_1/project_1.runs/impl_1/design_1_wrapper.bit differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper.tcl b/project_1/project_1.runs/impl_1/design_1_wrapper.tcl index f813408..98a68cd 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper.tcl +++ b/project_1/project_1.runs/impl_1/design_1_wrapper.tcl @@ -123,6 +123,7 @@ set ACTIVE_STEP init_design set rc [catch { create_msg_db init_design.pb set_param chipscope.maxJobs 3 + set_param xicom.use_bs_reader 1 OPTRACE "create in-memory project" START { } create_project -in_memory -part xc7z010clg400-1 set_property design_mode GateLvl [current_fileset] @@ -141,6 +142,7 @@ OPTRACE "add files" START { } add_files D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd set_param project.isImplRun false OPTRACE "read constraints: implementation" START { } + read_xdc D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc OPTRACE "read constraints: implementation" END { } OPTRACE "add files" END { } OPTRACE "link_design" START { } diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper.vdi b/project_1/project_1.runs/impl_1/design_1_wrapper.vdi index 629aa81..e598b50 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper.vdi +++ b/project_1/project_1.runs/impl_1/design_1_wrapper.vdi @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 22:21:24 2024 -# Process ID: 78520 +# Start of session at: Fri Oct 25 01:51:13 2024 +# Process ID: 224604 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 # Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi @@ -11,6 +11,7 @@ # Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB #----------------------------------------------------------- source design_1_wrapper.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 374.613 ; gain = 63.391 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'. @@ -19,19 +20,21 @@ Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-454] Reading design checkpoint 'd:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 819.957 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 819.367 ; gain = 0.000 INFO: [Project 1-479] Netlist was created with Vivado 2022.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 949.297 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 945.301 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 949.297 ; gain = 534.078 +link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 945.301 ; gain = 529.055 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -42,54 +45,54 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 974.305 ; gain = 25.008 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 973.383 ; gain = 28.082 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 981f6d8d +Ending Cache Timing Information Task | Checksum: 13ac7fd5f -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1435.113 ; gain = 460.809 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1430.504 ; gain = 457.121 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 122f0b1b6 +Phase 1 Retarget | Checksum: 13aa10cfc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 122f0b1b6 +Phase 2 Constant propagation | Checksum: 13aa10cfc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: f26bc340 +Phase 3 Sweep | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1768.855 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1764.969 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: f26bc340 +Phase 4 BUFG optimization | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 5 Shift Register Optimization | Checksum: f26bc340 +Phase 5 Shift Register Optimization | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: f26bc340 +Phase 6 Post Processing Netlist | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= @@ -100,7 +103,7 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 24 | 0 | | Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 1 | 0 | +| Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | @@ -110,36 +113,36 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 15449c801 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.174 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 15449c801 +Ending Power Optimization Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 15449c801 +Ending Final Cleanup Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1768.855 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 15449c801 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1768.855 ; gain = 819.559 +opt_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.969 ; gain = 819.668 INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx @@ -164,73 +167,70 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1772.094 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.396 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.404 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found. -Phase 1.3 Build Placer Netlist Model | Checksum: 11ddc6f74 +Phase 1.3 Build Placer Netlist Model | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.535 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.440 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 11ddc6f74 +Phase 1.4 Constrain Clocks/Macros | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.540 . Memory (MB): peak = 1772.094 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 11ddc6f74 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.442 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.542 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.443 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 2 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.544 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.446 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1772.094 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1772.094 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed) Starting Initial Update Timing Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1776.805 ; gain = 4.711 -INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. -INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1764.969 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +52 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1780.828 ; gain = 4.023 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1774.996 ; gain = 10.027 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' @@ -249,26 +249,22 @@ Checksum: PlaceDB: 401615bb ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0 Post Restoration Checksum: NetGraph: 752172cc NumContArr: 683b9ea3 Constraints: 0 Timing: 0 Phase 1 Build RT Design | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1820.727 ; gain = 30.844 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1814.922 ; gain = 30.887 Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945 Number of Nodes with overlaps = 0 -Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: f1e72516 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1828.551 ; gain = 38.668 - Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % @@ -283,58 +279,43 @@ Router Utilization Summary Phase 2 Router Initialization | Checksum: f1e72516 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: f1e72516 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 4 Rip-up And Reroute | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 Phase 5 Delay and Skew Optimization | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 Phase 6.1 Hold Fix Iter | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 6 Post Hold Fix | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 7 Route finalize @@ -350,40 +331,61 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 +Congestion Report +North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + Phase 7 Route finalize | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 - -Phase 10 Post Router Timing -Phase 10 Post Router Timing | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -63 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1830.281 ; gain = 49.453 +route_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 1824.324 ; gain = 49.328 INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1844.137 ; gain = 13.855 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1838.148 ; gain = 13.824 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx @@ -400,15 +402,18 @@ report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -75 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +74 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt @@ -436,5 +441,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2295.570 ; gain = 432.406 -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:22:26 2024... +write_bitstream: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2291.984 ; gain = 432.449 +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:52:25 2024... diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_124484.backup.vdi b/project_1/project_1.runs/impl_1/design_1_wrapper_124484.backup.vdi new file mode 100644 index 0000000..59948dc --- /dev/null +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_124484.backup.vdi @@ -0,0 +1,426 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Thu Oct 24 19:48:35 2024 +# Process ID: 124484 +# Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi +# Journal file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1\vivado.jou +# Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'. +Command: link_design -top design_1_wrapper -part xc7z010clg400-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-454] Reading design checkpoint 'd:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0' +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 819.305 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2022.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +CRITICAL WARNING: [Common 17-69] Command failed: 'Y13' is not a valid site or package pin name. [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc:1] +CRITICAL WARNING: [Common 17-69] Command failed: 'W11' is not a valid site or package pin name. [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc:2] +CRITICAL WARNING: [Common 17-69] Command failed: 'Y12' is not a valid site or package pin name. [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc:3] +CRITICAL WARNING: [Common 17-69] Command failed: 'U9' is not a valid site or package pin name. [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc:4] +Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 938.559 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +9 Infos, 0 Warnings, 4 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 938.559 ; gain = 522.453 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.995 . Memory (MB): peak = 965.648 ; gain = 27.090 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1035af716 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1429.887 ; gain = 464.238 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 111715f58 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 111715f58 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 146035cff + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 4 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 146035cff + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 146035cff + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.143 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 146035cff + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.146 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 24 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 4 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1538c48fd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.182 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1538c48fd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1538c48fd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1538c48fd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +26 Infos, 0 Warnings, 4 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1764.859 ; gain = 826.301 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx +Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e313ed4b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b37b193a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.369 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 16efc1f54 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 16efc1f54 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 16efc1f54 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.403 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Phase 2 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.859 ; gain = 0.000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.403 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed +Ending Placer Task | Checksum: b37b193a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 0 Warnings, 4 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.859 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 97.1% nets are fully routed) + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1764.859 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +52 Infos, 0 Warnings, 4 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1776.820 ; gain = 11.961 +INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: 107d41aa ConstDB: 0 ShapeSum: a2fdd790 RouteDB: 0 +Post Restoration Checksum: NetGraph: d0766f29 NumContArr: de147005 Constraints: 0 Timing: 0 +Phase 1 Build RT Design | Checksum: 1ae8adf2e + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1816.750 ; gain = 30.867 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1ae8adf2e + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1822.805 ; gain = 36.922 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1ae8adf2e + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1822.805 ; gain = 36.922 + Number of Nodes with overlaps = 0 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 134 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 134 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 102e0bf36 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 102e0bf36 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 +Phase 4 Rip-up And Reroute | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 +Phase 6 Post Hold Fix | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0598255 % + Global Horizontal Routing Utilization = 0.0301011 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1825.449 ; gain = 39.566 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.434 ; gain = 40.551 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 176e67719 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.434 ; gain = 40.551 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.434 ; gain = 40.551 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +62 Infos, 0 Warnings, 4 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1826.434 ; gain = 49.613 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.176 . Memory (MB): peak = 1839.297 ; gain = 12.863 +INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx +Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx +Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx +Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +74 Infos, 1 Warnings, 4 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Oct 24 19:49:29 2024... diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt index 20d78f9..f76e96c 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:15 2024 +| Date : Fri Oct 25 01:52:13 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx b/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx index fde98f3..519cf47 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx and b/project_1/project_1.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt index 7546e71..22b2613 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:15 2024 +| Date : Fri Oct 25 01:52:13 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_control_sets_placed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_control_sets_placed.rpt index 187884c..b734c01 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_control_sets_placed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:21:58 2024 +| Date : Fri Oct 25 01:51:53 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt index dccfe5a..4eaab98 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:21:56 2024 +| Date : Fri Oct 25 01:51:50 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt index 42ac3ba..786e576 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:14 2024 +| Date : Fri Oct 25 01:52:12 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_io_placed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_io_placed.rpt index 4127797..1736ebb 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_io_placed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:21:58 2024 +| Date : Fri Oct 25 01:51:53 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_io -file design_1_wrapper_io_placed.rpt | Design : design_1_wrapper @@ -39,19 +39,19 @@ Table of Contents | A2 | DDR_dq[2] | | PS_DDR_DQ2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | A4 | DDR_dq[3] | | PS_DDR_DQ3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | -| A5 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A6 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A7 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | FIXED_IO_mio[6] | | PS_MIO6_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A6 | FIXED_IO_mio[5] | | PS_MIO5_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A7 | FIXED_IO_mio[1] | | PS_MIO1_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A9 | FIXED_IO_mio[43] | | PS_MIO43_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A10 | FIXED_IO_mio[37] | | PS_MIO37_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A11 | FIXED_IO_mio[36] | | PS_MIO36_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A12 | FIXED_IO_mio[34] | | PS_MIO34_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A9 | FIXED_IO_mio[43] | | PS_MIO43_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A10 | FIXED_IO_mio[37] | | PS_MIO37_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A11 | FIXED_IO_mio[36] | | PS_MIO36_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A12 | FIXED_IO_mio[34] | | PS_MIO34_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| A14 | FIXED_IO_mio[32] | | PS_MIO32_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A15 | FIXED_IO_mio[26] | | PS_MIO26_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A16 | FIXED_IO_mio[24] | | PS_MIO24_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A17 | FIXED_IO_mio[20] | | PS_MIO20_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A14 | FIXED_IO_mio[32] | | PS_MIO32_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A15 | FIXED_IO_mio[26] | | PS_MIO26_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A16 | FIXED_IO_mio[24] | | PS_MIO24_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A17 | FIXED_IO_mio[20] | | PS_MIO20_501 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | A19 | FIXED_IO_mio[16] | | PS_MIO16_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -59,19 +59,19 @@ Table of Contents | B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | B3 | DDR_dq[1] | | PS_DDR_DQ1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | B4 | DDR_reset_n | | PS_DDR_DRST_B_502 | INOUT | SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | -| B7 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B9 | FIXED_IO_mio[51] | | PS_MIO51_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B7 | FIXED_IO_mio[4] | | PS_MIO4_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B8 | FIXED_IO_mio[2] | | PS_MIO2_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B9 | FIXED_IO_mio[51] | | PS_MIO51_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | B10 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | | B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B12 | FIXED_IO_mio[48] | | PS_MIO48_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B13 | FIXED_IO_mio[50] | | PS_MIO50_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B14 | FIXED_IO_mio[47] | | PS_MIO47_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B15 | FIXED_IO_mio[45] | | PS_MIO45_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B12 | FIXED_IO_mio[48] | | PS_MIO48_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B13 | FIXED_IO_mio[50] | | PS_MIO50_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B14 | FIXED_IO_mio[47] | | PS_MIO47_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B15 | FIXED_IO_mio[45] | | PS_MIO45_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| B17 | FIXED_IO_mio[22] | | PS_MIO22_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B17 | FIXED_IO_mio[22] | | PS_MIO22_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | B18 | FIXED_IO_mio[18] | | PS_MIO18_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | | | B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -79,38 +79,38 @@ Table of Contents | C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | C3 | DDR_dq[0] | | PS_DDR_DQ0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C5 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C6 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C5 | FIXED_IO_mio[14] | | PS_MIO14_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C6 | FIXED_IO_mio[11] | | PS_MIO11_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | C7 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C8 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C8 | FIXED_IO_mio[15] | | PS_MIO15_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C10 | FIXED_IO_mio[52] | | PS_MIO52_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C11 | FIXED_IO_mio[53] | | PS_MIO53_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C12 | FIXED_IO_mio[49] | | PS_MIO49_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C13 | FIXED_IO_mio[29] | | PS_MIO29_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C10 | FIXED_IO_mio[52] | | PS_MIO52_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C11 | FIXED_IO_mio[53] | | PS_MIO53_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C12 | FIXED_IO_mio[49] | | PS_MIO49_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C13 | FIXED_IO_mio[29] | | PS_MIO29_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C15 | FIXED_IO_mio[30] | | PS_MIO30_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C16 | FIXED_IO_mio[28] | | PS_MIO28_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C17 | FIXED_IO_mio[41] | | PS_MIO41_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C18 | FIXED_IO_mio[39] | | PS_MIO39_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C15 | FIXED_IO_mio[30] | | PS_MIO30_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C16 | FIXED_IO_mio[28] | | PS_MIO28_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C17 | FIXED_IO_mio[41] | | PS_MIO41_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C18 | FIXED_IO_mio[39] | | PS_MIO39_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | | C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | | | D1 | DDR_dq[5] | | PS_DDR_DQ5_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | | D3 | DDR_dq[4] | | PS_DDR_DQ4_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | D4 | DDR_addr[13] | | PS_DDR_A13_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D5 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D6 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | FIXED_IO_mio[8] | | PS_MIO8_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D6 | FIXED_IO_mio[3] | | PS_MIO3_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | | D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | -| D8 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D8 | FIXED_IO_mio[7] | | PS_MIO7_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | | D9 | FIXED_IO_mio[12] | | PS_MIO12_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | -| D10 | FIXED_IO_mio[19] | | PS_MIO19_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D11 | FIXED_IO_mio[23] | | PS_MIO23_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D10 | FIXED_IO_mio[19] | | PS_MIO19_501 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D11 | FIXED_IO_mio[23] | | PS_MIO23_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| D13 | FIXED_IO_mio[27] | | PS_MIO27_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D14 | FIXED_IO_mio[40] | | PS_MIO40_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D15 | FIXED_IO_mio[33] | | PS_MIO33_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D16 | FIXED_IO_mio[46] | | PS_MIO46_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D13 | FIXED_IO_mio[27] | | PS_MIO27_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D14 | FIXED_IO_mio[40] | | PS_MIO40_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D15 | FIXED_IO_mio[33] | | PS_MIO33_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D16 | FIXED_IO_mio[46] | | PS_MIO46_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | | D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -120,17 +120,17 @@ Table of Contents | E3 | DDR_dq[9] | | PS_DDR_DQ9_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | | E4 | DDR_addr[12] | | PS_DDR_A12_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | | E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| E6 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E6 | FIXED_IO_mio[0] | | PS_MIO0_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | E7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | | E8 | FIXED_IO_mio[13] | | PS_MIO13_500 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | -| E9 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E9 | FIXED_IO_mio[10] | | PS_MIO10_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | | -| E12 | FIXED_IO_mio[42] | | PS_MIO42_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| E13 | FIXED_IO_mio[38] | | PS_MIO38_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E12 | FIXED_IO_mio[42] | | PS_MIO42_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E13 | FIXED_IO_mio[38] | | PS_MIO38_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | E14 | FIXED_IO_mio[17] | | PS_MIO17_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| E16 | FIXED_IO_mio[31] | | PS_MIO31_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E16 | FIXED_IO_mio[31] | | PS_MIO31_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | | | E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | | | E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -146,10 +146,10 @@ Table of Contents | F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | | F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | | | F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| F12 | FIXED_IO_mio[35] | | PS_MIO35_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| F13 | FIXED_IO_mio[44] | | PS_MIO44_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F12 | FIXED_IO_mio[35] | | PS_MIO35_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F13 | FIXED_IO_mio[44] | | PS_MIO44_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | F14 | FIXED_IO_mio[21] | | PS_MIO21_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | -| F15 | FIXED_IO_mio[25] | | PS_MIO25_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F15 | FIXED_IO_mio[25] | | PS_MIO25_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | | F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | | F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt index 510f7e0..e15d368 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:15 2024 +| Date : Fri Oct 25 01:52:13 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp b/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp index 772f2ce..c2ca6e5 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp and b/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp b/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp index 48be808..9c055c8 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp and b/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp b/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp index 87775e4..e15de4e 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp and b/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpt index 73159f6..3d112ee 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:15 2024 +| Date : Fri Oct 25 01:52:13 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx | Design : design_1_wrapper @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 1.380 | +| Total On-Chip Power (W) | 1.222 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 1.267 | -| Device Static (W) | 0.113 | +| Dynamic (W) | 1.108 | +| Device Static (W) | 0.114 | | Effective TJA (C/W) | 11.5 | -| Max Ambient (C) | 69.1 | -| Junction Temperature (C) | 40.9 | +| Max Ambient (C) | 70.9 | +| Junction Temperature (C) | 39.1 | | Confidence Level | High | | Setting File | --- | | Simulation Activity File | --- | @@ -52,13 +52,12 @@ Table of Contents +--------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +--------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.000 | 3 | --- | --- | | Slice Logic | 0.000 | 132 | --- | --- | | Others | 0.000 | 132 | --- | --- | | Signals | 0.000 | 0 | --- | --- | -| PS7 | 1.267 | 1 | --- | --- | -| Static Power | 0.113 | | | | -| Total | 1.380 | | | | +| PS7 | 1.095 | 1 | --- | --- | +| Static Power | 0.114 | | | | +| Total | 1.209 | | | | +--------------+-----------+----------+-----------+-----------------+ @@ -68,8 +67,8 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.006 | 0.000 | 0.006 | NA | Unspecified | NA | -| Vccaux | 1.800 | 0.008 | 0.000 | 0.008 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.019 | 0.013 | 0.006 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | @@ -81,12 +80,12 @@ Table of Contents | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vccpint | 1.000 | 0.687 | 0.660 | 0.027 | NA | Unspecified | NA | -| Vccpaux | 1.800 | 0.036 | 0.026 | 0.010 | NA | Unspecified | NA | -| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA | -| Vcco_ddr | 1.500 | 0.356 | 0.354 | 0.002 | NA | Unspecified | NA | -| Vcco_mio0 | 1.800 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | -| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA | +| Vccpint | 1.000 | 0.621 | 0.596 | 0.025 | NA | Unspecified | NA | +| Vccpaux | 1.800 | 0.028 | 0.017 | 0.010 | NA | Unspecified | NA | +| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA | +| Vcco_ddr | 1.500 | 0.292 | 0.290 | 0.002 | NA | Unspecified | NA | +| Vcco_mio0 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | +| Vcco_mio1 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ @@ -142,10 +141,10 @@ Table of Contents +--------------------------+-----------+ | Name | Power (W) | +--------------------------+-----------+ -| design_1_wrapper | 1.267 | -| design_1_i | 1.267 | -| processing_system7_0 | 1.267 | -| inst | 1.267 | +| design_1_wrapper | 1.095 | +| design_1_i | 1.095 | +| processing_system7_0 | 1.095 | +| inst | 1.095 | +--------------------------+-----------+ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpx b/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpx index f67d32a..88395c5 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpx and b/project_1/project_1.runs/impl_1/design_1_wrapper_power_routed.rpx differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_power_summary_routed.pb b/project_1/project_1.runs/impl_1/design_1_wrapper_power_summary_routed.pb index 1070fae..ae25909 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_power_summary_routed.pb and b/project_1/project_1.runs/impl_1/design_1_wrapper_power_summary_routed.pb differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp b/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp index f808196..4c38888 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp and b/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt index c568e2b..82ec2a6 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:22:15 2024 +| Date : Fri Oct 25 01:52:13 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation | Design : design_1_wrapper @@ -139,7 +139,7 @@ Table of Contents NA NA NA NA NA NA NA NA NA NA NA NA -All user specified timing constraints are met. +There are no user specified timing constraints. ------------------------------------------------------------------------------------------------ @@ -147,10 +147,6 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk_fpga_0 {0.000 10.000} 20.000 50.000 - ------------------------------------------------------------------------------------------------ | Intra Clock Table diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx b/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx index 654f13e..c045762 100644 Binary files a/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx and b/project_1/project_1.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx differ diff --git a/project_1/project_1.runs/impl_1/design_1_wrapper_utilization_placed.rpt b/project_1/project_1.runs/impl_1/design_1_wrapper_utilization_placed.rpt index c666547..78dd04e 100644 --- a/project_1/project_1.runs/impl_1/design_1_wrapper_utilization_placed.rpt +++ b/project_1/project_1.runs/impl_1/design_1_wrapper_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:21:58 2024 +| Date : Fri Oct 25 01:51:53 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb | Design : design_1_wrapper diff --git a/project_1/project_1.runs/impl_1/gen_run.xml b/project_1/project_1.runs/impl_1/gen_run.xml index 0a2dac1..1414d22 100644 --- a/project_1/project_1.runs/impl_1/gen_run.xml +++ b/project_1/project_1.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -103,12 +103,27 @@ + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/impl_1/init_design.pb b/project_1/project_1.runs/impl_1/init_design.pb index be6157c..93e7582 100644 Binary files a/project_1/project_1.runs/impl_1/init_design.pb and b/project_1/project_1.runs/impl_1/init_design.pb differ diff --git a/project_1/project_1.runs/impl_1/opt_design.pb b/project_1/project_1.runs/impl_1/opt_design.pb index 69c58ad..9dde3d4 100644 Binary files a/project_1/project_1.runs/impl_1/opt_design.pb and b/project_1/project_1.runs/impl_1/opt_design.pb differ diff --git a/project_1/project_1.runs/impl_1/phys_opt_design.pb b/project_1/project_1.runs/impl_1/phys_opt_design.pb index 8ce0cf5..48564a9 100644 Binary files a/project_1/project_1.runs/impl_1/phys_opt_design.pb and b/project_1/project_1.runs/impl_1/phys_opt_design.pb differ diff --git a/project_1/project_1.runs/impl_1/place_design.pb b/project_1/project_1.runs/impl_1/place_design.pb index 3e10345..f4a28e1 100644 Binary files a/project_1/project_1.runs/impl_1/place_design.pb and b/project_1/project_1.runs/impl_1/place_design.pb differ diff --git a/project_1/project_1.runs/impl_1/project.wdf b/project_1/project_1.runs/impl_1/project.wdf index fdc31ce..d80f91a 100644 --- a/project_1/project_1.runs/impl_1/project.wdf +++ b/project_1/project_1.runs/impl_1/project.wdf @@ -1,6 +1,6 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 @@ -21,12 +21,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3139:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3139:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3139:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3139:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3139:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3139:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3534626431336132626430633430393761313364643966646636616461613737:506172656e742050412070726f6a656374204944:00 -eof:3293127451 +eof:2397707485 diff --git a/project_1/project_1.runs/impl_1/route_design.pb b/project_1/project_1.runs/impl_1/route_design.pb index 9cc1cf0..14d1a5a 100644 Binary files a/project_1/project_1.runs/impl_1/route_design.pb and b/project_1/project_1.runs/impl_1/route_design.pb differ diff --git a/project_1/project_1.runs/impl_1/runme.log b/project_1/project_1.runs/impl_1/runme.log index a6aa3ef..534ad53 100644 --- a/project_1/project_1.runs/impl_1/runme.log +++ b/project_1/project_1.runs/impl_1/runme.log @@ -10,6 +10,7 @@ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source design_1_wrapper.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 374.613 ; gain = 63.391 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'. @@ -18,19 +19,21 @@ Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-454] Reading design checkpoint 'd:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 819.957 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 819.367 ; gain = 0.000 INFO: [Project 1-479] Netlist was created with Vivado 2022.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 949.297 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 945.301 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 949.297 ; gain = 534.078 +link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 945.301 ; gain = 529.055 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -41,54 +44,54 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 974.305 ; gain = 25.008 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 973.383 ; gain = 28.082 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 981f6d8d +Ending Cache Timing Information Task | Checksum: 13ac7fd5f -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1435.113 ; gain = 460.809 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1430.504 ; gain = 457.121 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 122f0b1b6 +Phase 1 Retarget | Checksum: 13aa10cfc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 122f0b1b6 +Phase 2 Constant propagation | Checksum: 13aa10cfc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: f26bc340 +Phase 3 Sweep | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1768.855 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1764.969 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: f26bc340 +Phase 4 BUFG optimization | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 5 Shift Register Optimization | Checksum: f26bc340 +Phase 5 Shift Register Optimization | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: f26bc340 +Phase 6 Post Processing Netlist | Checksum: a740edb4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= @@ -99,7 +102,7 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 24 | 0 | | Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 1 | 0 | +| Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | @@ -109,36 +112,36 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 15449c801 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.174 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 15449c801 +Ending Power Optimization Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 15449c801 +Ending Final Cleanup Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1768.855 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 15449c801 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 18965390f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1768.855 ; gain = 819.559 +opt_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.969 ; gain = 819.668 INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1768.855 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx @@ -163,73 +166,70 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1772.094 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.396 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.404 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found. -Phase 1.3 Build Placer Netlist Model | Checksum: 11ddc6f74 +Phase 1.3 Build Placer Netlist Model | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.535 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.440 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 11ddc6f74 +Phase 1.4 Constrain Clocks/Macros | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.540 . Memory (MB): peak = 1772.094 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 11ddc6f74 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.442 . Memory (MB): peak = 1764.969 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 18d9a5a3a -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.542 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.443 . Memory (MB): peak = 1764.969 ; gain = 0.000 Phase 2 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.544 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 9477fc6b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.446 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1772.094 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1772.094 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1764.969 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1772.094 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed) Starting Initial Update Timing Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1776.805 ; gain = 4.711 -INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. -INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1764.969 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +52 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1780.828 ; gain = 4.023 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1774.996 ; gain = 10.027 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' @@ -248,26 +248,22 @@ Checksum: PlaceDB: 401615bb ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0 Post Restoration Checksum: NetGraph: 752172cc NumContArr: 683b9ea3 Constraints: 0 Timing: 0 Phase 1 Build RT Design | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1820.727 ; gain = 30.844 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1814.922 ; gain = 30.887 Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dd5d116f -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1826.754 ; gain = 36.871 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945 Number of Nodes with overlaps = 0 -Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: f1e72516 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1828.551 ; gain = 38.668 - Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % @@ -282,58 +278,43 @@ Router Utilization Summary Phase 2 Router Initialization | Checksum: f1e72516 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: f1e72516 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 4 Rip-up And Reroute | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 Phase 5 Delay and Skew Optimization | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 Phase 6.1 Hold Fix Iter | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 6 Post Hold Fix | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 7 Route finalize @@ -349,40 +330,61 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 +Congestion Report +North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + Phase 7 Route finalize | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1829.293 ; gain = 39.410 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 9afecd01 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 - -Phase 10 Post Router Timing -Phase 10 Post Router Timing | Checksum: 9afecd01 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1830.281 ; gain = 40.398 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -63 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1830.281 ; gain = 49.453 +route_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 1824.324 ; gain = 49.328 INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1844.137 ; gain = 13.855 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1838.148 ; gain = 13.824 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx @@ -399,15 +401,18 @@ report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -75 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +74 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt @@ -435,5 +440,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2295.570 ; gain = 432.406 -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:22:26 2024... +write_bitstream: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2291.984 ; gain = 432.449 +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:52:25 2024... diff --git a/project_1/project_1.runs/impl_1/vivado.jou b/project_1/project_1.runs/impl_1/vivado.jou index f0d31ac..d3f571c 100644 --- a/project_1/project_1.runs/impl_1/vivado.jou +++ b/project_1/project_1.runs/impl_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 22:21:24 2024 -# Process ID: 78520 +# Start of session at: Fri Oct 25 01:51:13 2024 +# Process ID: 224604 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 # Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi diff --git a/project_1/project_1.runs/impl_1/vivado.pb b/project_1/project_1.runs/impl_1/vivado.pb index 951da89..1fb1022 100644 Binary files a/project_1/project_1.runs/impl_1/vivado.pb and b/project_1/project_1.runs/impl_1/vivado.pb differ diff --git a/project_1/project_1.runs/impl_1/vivado_119328.backup.jou b/project_1/project_1.runs/impl_1/vivado_119328.backup.jou new file mode 100644 index 0000000..e0406bb --- /dev/null +++ b/project_1/project_1.runs/impl_1/vivado_119328.backup.jou @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Thu Oct 24 20:06:30 2024 +# Process ID: 119328 +# Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi +# Journal file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1\vivado.jou +# Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace diff --git a/project_1/project_1.runs/impl_1/vivado_124484.backup.jou b/project_1/project_1.runs/impl_1/vivado_124484.backup.jou new file mode 100644 index 0000000..99b136a --- /dev/null +++ b/project_1/project_1.runs/impl_1/vivado_124484.backup.jou @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Thu Oct 24 19:48:35 2024 +# Process ID: 124484 +# Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi +# Journal file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1\vivado.jou +# Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace diff --git a/project_1/project_1.runs/impl_1/vivado_126508.backup.jou b/project_1/project_1.runs/impl_1/vivado_126508.backup.jou new file mode 100644 index 0000000..75da48c --- /dev/null +++ b/project_1/project_1.runs/impl_1/vivado_126508.backup.jou @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Thu Oct 24 21:13:20 2024 +# Process ID: 126508 +# Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper.vdi +# Journal file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1\vivado.jou +# Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace diff --git a/project_1/project_1.runs/impl_1/write_bitstream.pb b/project_1/project_1.runs/impl_1/write_bitstream.pb index a1d76a4..8a86ca8 100644 Binary files a/project_1/project_1.runs/impl_1/write_bitstream.pb and b/project_1/project_1.runs/impl_1/write_bitstream.pb differ diff --git a/project_1/project_1.runs/synth_1/.vivado.begin.rst b/project_1/project_1.runs/synth_1/.vivado.begin.rst index c8a991d..96aa724 100644 --- a/project_1/project_1.runs/synth_1/.vivado.begin.rst +++ b/project_1/project_1.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/project_1/project_1.runs/synth_1/design_1_wrapper.dcp b/project_1/project_1.runs/synth_1/design_1_wrapper.dcp index 2d33d5d..658a776 100644 Binary files a/project_1/project_1.runs/synth_1/design_1_wrapper.dcp and b/project_1/project_1.runs/synth_1/design_1_wrapper.dcp differ diff --git a/project_1/project_1.runs/synth_1/design_1_wrapper.tcl b/project_1/project_1.runs/synth_1/design_1_wrapper.tcl index 425e775..c3d8044 100644 --- a/project_1/project_1.runs/synth_1/design_1_wrapper.tcl +++ b/project_1/project_1.runs/synth_1/design_1_wrapper.tcl @@ -70,6 +70,8 @@ proc create_report { reportName command } { } } OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 3 +set_param xicom.use_bs_reader 1 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7z010clg400-1 @@ -85,7 +87,7 @@ set_property ip_output_repo d:/project/hdl/zynq_lvgl/project_1/project_1.cache/i set_property ip_cache_permissions {read write} [current_project] OPTRACE "Creating in-memory project" END { } OPTRACE "Adding files" START { } -read_verilog -library xil_defaultlib d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v +read_verilog -library xil_defaultlib D:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v add_files D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd set_property used_in_implementation false [get_files -all d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] set_property used_in_implementation false [get_files -all d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc] @@ -99,9 +101,14 @@ OPTRACE "Adding files" END { } foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } +read_xdc D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc +set_property used_in_implementation false [get_files D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] + read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 + +read_checkpoint -auto_incremental -incremental D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp close [open __synthesis_is_running__ w] OPTRACE "synth_design" START { } diff --git a/project_1/project_1.runs/synth_1/design_1_wrapper.vds b/project_1/project_1.runs/synth_1/design_1_wrapper.vds index fef26c6..1657eeb 100644 --- a/project_1/project_1.runs/synth_1/design_1_wrapper.vds +++ b/project_1/project_1.runs/synth_1/design_1_wrapper.vds @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 22:20:33 2024 -# Process ID: 80360 +# Start of session at: Fri Oct 25 01:50:16 2024 +# Process ID: 231948 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1 # Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/design_1_wrapper.vds @@ -11,339 +11,346 @@ # Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 42857 MB #----------------------------------------------------------- source design_1_wrapper.tcl -notrace +create_project: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 374.598 ; gain = 65.773 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'. +Command: read_checkpoint -auto_incremental -incremental D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top design_1_wrapper -part xc7z010clg400-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 80880 +INFO: [Synth 8-7075] Helper process launched with PID 230432 INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.152 ; gain = 413.398 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1209.953 ; gain = 415.590 --------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'design_1' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:12] -INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-80360-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] -INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-80360-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] -WARNING: [Synth 8-7071] port 'FCLK_CLK0' of module 'design_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] -WARNING: [Synth 8-7071] port 'FCLK_RESET0_N' of module 'design_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] -WARNING: [Synth 8-7023] instance 'processing_system7_0' of module 'design_1_processing_system7_0_0' has 23 connections declared, but only 21 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] +INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-231948-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-231948-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:12] -INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1295.562 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1299.285 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' +Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1307.637 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1299.285 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1307.637 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1299.285 ; gain = 0.000 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 2). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 116). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 117). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 118). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 119). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 120). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 121). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 122). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 123). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 124). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 125). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 126). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 127). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 128). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 129). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 130). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 131). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 132). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 133). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 134). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 135). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 136). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 137). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 138). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 139). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 140). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 141). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 142). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 143). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 144). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 145). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 146). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 147). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 148). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 149). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 150). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 151). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 152). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 153). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 154). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 155). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 156). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 157). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 158). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 159). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 160). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 161). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 162). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 163). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 164). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 165). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 166). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 167). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 168). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 169). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 170). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 171). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 172). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 173). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 174). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 175). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 176). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 177). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 178). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 179). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 180). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 181). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 182). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 183). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 184). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 185). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 186). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 187). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 188). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 189). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 190). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 191). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 192). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 193). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 194). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 195). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 196). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 197). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 198). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 199). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 200). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 201). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 202). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 203). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 204). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 205). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 206). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 207). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 208). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 209). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 210). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 211). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 212). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 213). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 214). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 215). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 216). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 217). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 218). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 219). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 220). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 221). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 222). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 223). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 224). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 225). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 226). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 227). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 228). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 229). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 230). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 231). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 232). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 233). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 234). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 235). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 236). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 237). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 238). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 239). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 240). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 241). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 242). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 243). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 244). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 245). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 246). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 247). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 248). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 249). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 250). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 251). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 252). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 253). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 254). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 255). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 256). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 257). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 258). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 259). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 260). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 261). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 1). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 2). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 116). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 117). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 118). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 119). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 120). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 121). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 122). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 123). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 124). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 125). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 126). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 127). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 128). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 129). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 130). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 131). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 132). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 133). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 134). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 135). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 136). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 137). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 138). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 139). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 140). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 141). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 142). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 143). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 144). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 145). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 146). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 147). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 148). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 149). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 150). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 151). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 152). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 153). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 154). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 155). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 156). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 157). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 158). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 159). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 160). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 161). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 162). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 163). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 164). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 165). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 166). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 167). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 168). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 169). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 170). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 171). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 172). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 173). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 174). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 175). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 176). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 177). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 178). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 179). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 180). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 181). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 182). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 183). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 184). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 185). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 186). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 187). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 188). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 189). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 190). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 191). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 192). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 193). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 194). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 195). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 196). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 197). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 198). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 199). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 200). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 201). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 202). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 203). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 204). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 205). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 206). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 207). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 208). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 209). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 210). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 211). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 212). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 213). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 214). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 215). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 216). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 217). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 218). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 219). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 220). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 221). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 222). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 223). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 224). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 225). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 226). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 227). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 228). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 229). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 230). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 231). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 232). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 233). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 234). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 235). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 236). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 237). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 238). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 239). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 240). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 241). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 242). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 243). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 244). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 245). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 246). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 247). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 248). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 249). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 250). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 251). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 252). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 253). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 254). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 255). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 256). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 257). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 258). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 259). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 260). Applied set_property KEEP_HIERARCHY = SOFT for design_1_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/processing_system7_0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -366,25 +373,25 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:19 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Timing Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1315.855 ; gain = 524.102 +Finished Technology Mapping : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -402,37 +409,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -452,24 +459,24 @@ Report Cell Usage: |1 |design_1_processing_system7_0 | 1| +------+------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.660 ; gain = 516.832 -Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:30 . Memory (MB): peak = 1304.461 ; gain = 510.098 +Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1320.660 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1304.461 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.863 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1326.777 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 5d13d4d5 +Synth Design complete, checksum: 59f2c487 INFO: [Common 17-83] Releasing license: Synthesis -23 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +29 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 1344.863 ; gain = 934.141 +synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:39 . Memory (MB): peak = 1326.777 ; gain = 912.219 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/design_1_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:21:16 2024... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:51:04 2024... diff --git a/project_1/project_1.runs/synth_1/design_1_wrapper_utilization_synth.rpt b/project_1/project_1.runs/synth_1/design_1_wrapper_utilization_synth.rpt index ca039fb..533699c 100644 --- a/project_1/project_1.runs/synth_1/design_1_wrapper_utilization_synth.rpt +++ b/project_1/project_1.runs/synth_1/design_1_wrapper_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 20 22:21:16 2024 +| Date : Fri Oct 25 01:51:04 2024 | Host : destop1 running 64-bit major release (build 9200) | Command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb | Design : design_1_wrapper diff --git a/project_1/project_1.runs/synth_1/dont_touch.xdc b/project_1/project_1.runs/synth_1/dont_touch.xdc index 42f24cc..2e565f4 100644 --- a/project_1/project_1.runs/synth_1/dont_touch.xdc +++ b/project_1/project_1.runs/synth_1/dont_touch.xdc @@ -1,6 +1,8 @@ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. +# XDC: new/test.xdc + # Block Designs: bd/design_1/design_1.bd set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1 || ORIG_REF_NAME==design_1} -quiet] -quiet diff --git a/project_1/project_1.runs/synth_1/gen_run.xml b/project_1/project_1.runs/synth_1/gen_run.xml index 1c634bf..99efca8 100644 --- a/project_1/project_1.runs/synth_1/gen_run.xml +++ b/project_1/project_1.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -33,12 +33,27 @@ + + + + + + + + + + + + + + + diff --git a/project_1/project_1.runs/synth_1/incr_synth_reason.pb b/project_1/project_1.runs/synth_1/incr_synth_reason.pb new file mode 100644 index 0000000..4cb4ed4 --- /dev/null +++ b/project_1/project_1.runs/synth_1/incr_synth_reason.pb @@ -0,0 +1 @@ + 6No compile time benefit to using incremental synthesis \ No newline at end of file diff --git a/project_1/project_1.runs/synth_1/runme.log b/project_1/project_1.runs/synth_1/runme.log index 2601690..37b8b39 100644 --- a/project_1/project_1.runs/synth_1/runme.log +++ b/project_1/project_1.runs/synth_1/runme.log @@ -10,339 +10,346 @@ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source design_1_wrapper.tcl -notrace +create_project: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 374.598 ; gain = 65.773 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'. +Command: read_checkpoint -auto_incremental -incremental D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top design_1_wrapper -part xc7z010clg400-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 80880 +INFO: [Synth 8-7075] Helper process launched with PID 230432 INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.152 ; gain = 413.398 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1209.953 ; gain = 415.590 --------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'design_1' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:12] -INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-80360-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] -INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-80360-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] -WARNING: [Synth 8-7071] port 'FCLK_CLK0' of module 'design_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] -WARNING: [Synth 8-7071] port 'FCLK_RESET0_N' of module 'design_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] -WARNING: [Synth 8-7023] instance 'processing_system7_0' of module 'design_1_processing_system7_0_0' has 23 connections declared, but only 21 given [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:79] +INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-231948-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/.Xil/Vivado-231948-destop1/realtime/design_1_processing_system7_0_0_stub.v:5] INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v:12] -INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [D:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1295.562 ; gain = 503.809 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1295.562 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1299.285 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' +Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] +Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc] Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1307.637 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1299.285 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1307.637 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1299.285 ; gain = 0.000 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 2). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 116). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 117). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 118). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 119). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 120). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 121). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 122). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 123). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 124). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 125). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 126). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 127). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 128). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 129). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 130). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 131). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 132). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 133). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 134). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 135). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 136). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 137). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 138). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 139). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 140). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 141). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 142). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 143). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 144). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 145). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 146). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 147). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 148). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 149). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 150). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 151). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 152). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 153). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 154). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 155). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 156). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 157). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 158). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 159). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 160). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 161). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 162). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 163). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 164). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 165). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 166). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 167). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 168). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 169). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 170). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 171). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 172). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 173). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 174). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 175). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 176). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 177). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 178). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 179). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 180). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 181). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 182). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 183). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 184). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 185). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 186). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 187). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 188). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 189). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 190). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 191). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 192). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 193). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 194). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 195). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 196). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 197). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 198). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 199). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 200). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 201). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 202). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 203). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 204). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 205). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 206). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 207). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 208). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 209). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 210). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 211). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 212). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 213). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 214). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 215). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 216). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 217). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 218). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 219). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 220). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 221). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 222). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 223). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 224). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 225). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 226). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 227). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 228). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 229). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 230). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 231). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 232). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 233). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 234). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 235). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 236). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 237). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 238). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 239). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 240). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 241). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 242). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 243). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 244). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 245). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 246). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 247). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 248). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 249). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 250). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 251). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 252). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 253). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 254). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 255). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 256). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 257). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 258). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 259). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 260). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 261). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 1). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 2). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 116). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 117). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 118). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 119). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 120). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 121). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 122). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 123). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 124). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 125). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 126). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 127). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 128). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 129). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 130). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 131). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 132). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 133). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 134). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 135). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 136). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 137). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 138). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 139). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 140). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 141). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 142). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 143). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 144). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 145). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 146). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 147). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 148). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 149). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 150). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 151). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 152). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 153). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 154). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 155). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 156). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 157). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 158). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 159). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 160). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 161). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 162). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 163). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 164). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 165). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 166). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 167). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 168). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 169). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 170). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 171). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 172). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 173). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 174). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 175). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 176). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 177). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 178). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 179). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 180). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 181). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 182). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 183). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 184). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 185). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 186). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 187). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 188). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 189). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 190). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 191). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 192). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 193). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 194). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 195). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 196). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 197). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 198). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 199). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 200). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 201). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 202). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 203). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 204). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 205). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 206). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 207). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 208). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 209). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 210). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 211). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 212). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 213). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 214). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 215). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 216). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 217). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 218). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 219). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 220). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 221). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 222). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 223). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 224). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 225). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 226). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 227). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 228). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 229). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 230). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 231). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 232). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 233). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 234). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 235). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 236). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 237). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 238). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 239). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 240). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 241). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 242). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 243). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 244). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 245). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 246). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 247). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 248). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 249). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 250). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 251). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 252). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 253). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 254). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 255). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 256). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 257). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 258). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 259). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 260). Applied set_property KEEP_HIERARCHY = SOFT for design_1_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/processing_system7_0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -365,25 +372,25 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:19 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1307.637 ; gain = 515.883 +Finished Timing Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1315.855 ; gain = 524.102 +Finished Technology Mapping : Time (s): cpu = 00:00:05 ; elapsed = 00:00:25 . Memory (MB): peak = 1299.285 ; gain = 504.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -401,37 +408,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -451,24 +458,24 @@ Report Cell Usage: |1 |design_1_processing_system7_0 | 1| +------+------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.660 ; gain = 516.832 -Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.660 ; gain = 528.906 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:30 . Memory (MB): peak = 1304.461 ; gain = 510.098 +Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1304.461 ; gain = 510.098 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1320.660 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1304.461 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.863 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1326.777 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete, checksum: 5d13d4d5 +Synth Design complete, checksum: 59f2c487 INFO: [Common 17-83] Releasing license: Synthesis -23 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +29 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 1344.863 ; gain = 934.141 +synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:39 . Memory (MB): peak = 1326.777 ; gain = 912.219 INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/design_1_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:21:16 2024... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:51:04 2024... diff --git a/project_1/project_1.runs/synth_1/vivado.jou b/project_1/project_1.runs/synth_1/vivado.jou index 1a93e1d..611ec80 100644 --- a/project_1/project_1.runs/synth_1/vivado.jou +++ b/project_1/project_1.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 20 22:20:33 2024 -# Process ID: 80360 +# Start of session at: Fri Oct 25 01:50:16 2024 +# Process ID: 231948 # Current directory: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1 # Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl # Log file: D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1/design_1_wrapper.vds diff --git a/project_1/project_1.runs/synth_1/vivado.pb b/project_1/project_1.runs/synth_1/vivado.pb index ee706da..b80a59f 100644 Binary files a/project_1/project_1.runs/synth_1/vivado.pb and b/project_1/project_1.runs/synth_1/vivado.pb differ diff --git a/project_1/project_1.srcs/constrs_1/new/test.xdc b/project_1/project_1.srcs/constrs_1/new/test.xdc new file mode 100644 index 0000000..f3183f6 --- /dev/null +++ b/project_1/project_1.srcs/constrs_1/new/test.xdc @@ -0,0 +1,7 @@ + +#set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports SPI0_MISO_I_0] +#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports SPI0_MOSI_O_0] +#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports SPI0_SCLK_O_0] +#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports SPI0_SS_O_0] + +#set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports GPIO_O_0[0]] diff --git a/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd b/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd index d659e4b..9868602 100644 --- a/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd +++ b/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0xCC6CFA539DDF0AAD", + "boundary_crc": "0xCC6CFA535221FB6E", "device": "xc7z010clg400-1", "gen_directory": "../../../../project_1.gen/sources_1/bd/design_1", "name": "design_1", @@ -191,13 +191,13 @@ "inst_hier_path": "processing_system7_0", "parameters": { "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { - "value": "666.666687" + "value": "400.000000" }, "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { "value": "10.000000" }, "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { - "value": "10.158730" + "value": "10.144927" }, "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { "value": "10.000000" @@ -206,7 +206,7 @@ "value": "10.000000" }, "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { - "value": "50.000000" + "value": "10.000000" }, "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { "value": "10.000000" @@ -236,31 +236,34 @@ "value": "200.000000" }, "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" }, "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { "value": "100.000000" }, "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { - "value": "111.111115" + "value": "66.666672" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "400" }, "PCW_CLK0_FREQ": { - "value": "50000000" + "value": "10000000" }, "PCW_CLK1_FREQ": { "value": "10000000" @@ -274,12 +277,24 @@ "PCW_DDR_RAM_HIGHADDR": { "value": "0x1FFFFFFF" }, + "PCW_EN_CLK0_PORT": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "0" + }, "PCW_EN_EMIO_SPI0": { "value": "0" }, "PCW_EN_EMIO_UART0": { "value": "0" }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_RST0_PORT": { + "value": "0" + }, "PCW_EN_SPI0": { "value": "1" }, @@ -289,9 +304,45 @@ "PCW_EN_UART1": { "value": "1" }, - "PCW_FPGA_FCLK0_ENABLE": { + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { "value": "1" }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "0" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, "PCW_MIO_12_IOTYPE": { "value": "LVCMOS 3.3V" }, @@ -310,6 +361,24 @@ "PCW_MIO_13_SLEW": { "value": "slow" }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, "PCW_MIO_16_IOTYPE": { "value": "LVCMOS 3.3V" }, @@ -337,6 +406,33 @@ "PCW_MIO_18_SLEW": { "value": "slow" }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "slow" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "slow" + }, "PCW_MIO_21_IOTYPE": { "value": "LVCMOS 3.3V" }, @@ -346,21 +442,359 @@ "PCW_MIO_21_SLEW": { "value": "slow" }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "slow" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "slow" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "slow" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "slow" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "slow" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "slow" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_28_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_28_SLEW": { + "value": "slow" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_29_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_29_SLEW": { + "value": "slow" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_30_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_30_SLEW": { + "value": "slow" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_31_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_31_SLEW": { + "value": "slow" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_32_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_32_SLEW": { + "value": "slow" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_33_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_33_SLEW": { + "value": "slow" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_34_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_34_SLEW": { + "value": "slow" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_35_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_35_SLEW": { + "value": "slow" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_36_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_36_SLEW": { + "value": "slow" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_37_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_37_SLEW": { + "value": "slow" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_38_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_38_SLEW": { + "value": "slow" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_39_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_39_SLEW": { + "value": "slow" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_50_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_51_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, "PCW_MIO_TREE_PERIPHERALS": { "value": [ - "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#SPI 0#SPI 0#SPI", - "0#unassigned#unassigned#SPI", - "0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" + "GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI", + "0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO" ] }, "PCW_MIO_TREE_SIGNALS": { - "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#sclk#miso#ss[0]#unassigned#unassigned#mosi#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" + "value": "gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#tx#rx#gpio[14]#gpio[15]#sclk#miso#ss[0]#ss[1]#ss[2]#mosi#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53]" }, "PCW_SPI0_GRP_SS1_ENABLE": { - "value": "0" + "value": "1" }, "PCW_SPI0_GRP_SS2_ENABLE": { - "value": "0" + "value": "1" }, "PCW_SPI0_PERIPHERAL_ENABLE": { "value": "1" @@ -393,7 +827,7 @@ "value": "1" }, "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { - "value": "533.333374" + "value": "350.000000" }, "PCW_UIPARAM_DDR_BUS_WIDTH": { "value": "16 Bit" @@ -401,9 +835,15 @@ "PCW_UIPARAM_DDR_ECC": { "value": "Disabled" }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "350" + }, "PCW_UIPARAM_DDR_PARTNO": { "value": "MT41K256M16 RE-125" }, + "PCW_USB_RESET_ENABLE": { + "value": "0" + }, "PCW_USE_M_AXI_GP0": { "value": "0" } diff --git a/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bda b/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bda index 71fde4b..62d5f22 100644 --- a/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bda +++ b/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bda @@ -23,9 +23,8 @@ - 2 design_1 - VR + BC active @@ -33,10 +32,11 @@ PM + 2 design_1 - BC + VR - - + + diff --git a/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci b/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci index b98b5e3..f99a5a5 100644 --- a/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci +++ b/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci @@ -26,8 +26,8 @@ "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], - "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], - "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], @@ -44,11 +44,11 @@ "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], - "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "FALSE", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK_CLK1_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK_CLK2_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK_CLK3_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "533.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "350", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_UIPARAM_DDR_BANK_ADDR_COUNT": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "PCW_UIPARAM_DDR_ROW_ADDR_COUNT": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "PCW_UIPARAM_DDR_COL_ADDR_COUNT": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -114,7 +114,7 @@ "PCW_PACKAGE_DDR_BOARD_DELAY3": [ { "value": "0.068", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CPU_CPU_6X4X_MAX_RANGE": [ { "value": "667", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": [ { "value": "33.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_APU_PERIPHERAL_FREQMHZ": [ { "value": "666.666666", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_APU_PERIPHERAL_FREQMHZ": [ { "value": "400", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_DCI_PERIPHERAL_FREQMHZ": [ { "value": "10.159", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_QSPI_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "PCW_SMC_PERIPHERAL_FREQMHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -141,9 +141,9 @@ "PCW_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_APU_PERIPHERAL_FREQMHZ": [ { "value": "666.666687", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": [ { "value": "533.333374", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": [ { "value": "10.158730", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": [ { "value": "400.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": [ { "value": "350.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": [ { "value": "10.144927", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -157,27 +157,27 @@ "PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_I2C_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PCW_CLK0_FREQ": [ { "value": "50000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "66.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK0_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK1_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK2_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_CLK3_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCW_OVERRIDE_BASIC_CLOCK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_CPU_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_DDR_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_PERIPHERAL_DIVISOR0": [ { "value": "4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PERIPHERAL_DIVISOR0": [ { "value": "4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_SMC_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_QSPI_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_SDIO_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -185,11 +185,11 @@ "PCW_SPI_PERIPHERAL_DIVISOR0": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_CAN_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_CAN_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_FCLK0_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK3_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK2_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_FCLK3_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -198,8 +198,8 @@ "PCW_ENET0_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_ENET1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_TPIU_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_DCI_PERIPHERAL_DIVISOR0": [ { "value": "15", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_DCI_PERIPHERAL_DIVISOR1": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DCI_PERIPHERAL_DIVISOR0": [ { "value": "46", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DCI_PERIPHERAL_DIVISOR1": [ { "value": "3", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_PCAP_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], @@ -208,12 +208,12 @@ "PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "PCW_WDT_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], - "PCW_ARMPLL_CTRL_FBDIV": [ { "value": "40", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ARMPLL_CTRL_FBDIV": [ { "value": "48", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_IOPLL_CTRL_FBDIV": [ { "value": "30", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_DDRPLL_CTRL_FBDIV": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_CPU_CPU_PLL_FREQMHZ": [ { "value": "1333.333", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDRPLL_CTRL_FBDIV": [ { "value": "42", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_CPU_PLL_FREQMHZ": [ { "value": "1600.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_IO_IO_PLL_FREQMHZ": [ { "value": "1000.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_DDR_DDR_PLL_FREQMHZ": [ { "value": "1066.667", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_DDR_PLL_FREQMHZ": [ { "value": "1400.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_SMC_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_SDIO_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_SPI_PERIPHERAL_VALID": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -225,7 +225,7 @@ "PCW_EN_EMIO_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_PTP_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_PTP_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_EN_EMIO_GPIO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_GPIO": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_EMIO_I2C0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_EMIO_I2C1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_EMIO_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -295,7 +295,7 @@ "PCW_USE_EXPANDED_PS_SLCR_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "PCW_USE_CORESIGHT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_EMIO_SRAM_INT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_GPIO_EMIO_GPIO_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "PCW_GP0_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_GP0_NUM_READ_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_GP1_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -334,7 +334,7 @@ "PCW_EN_CAN1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_EN_GPIO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_GPIO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_I2C0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_I2C1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -356,11 +356,11 @@ "PCW_DQS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_DM_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_MIO_PRIMITIVE": [ { "value": "54", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_EN_CLK0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK0_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_CLK1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_CLK2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_CLK3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PCW_EN_RST0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST0_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_RST1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_RST2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCW_EN_RST3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -476,15 +476,15 @@ "PCW_ENET0_ENET0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_ENET_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_ENET_RESET_SELECT": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_ENET1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PCW_ENET1_ENET1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_ENET1_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_ENET1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -514,10 +514,10 @@ "PCW_SPI0_SPI0_IO": [ { "value": "MIO 16 .. 21", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_SPI0_GRP_SS0_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_SPI0_GRP_SS0_IO": [ { "value": "MIO 18", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PCW_SPI0_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI0_GRP_SS1_IO": [ { "value": "MIO 19", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS2_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI0_GRP_SS2_IO": [ { "value": "MIO 20", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_SPI1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PCW_SPI1_SPI1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_USB0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PCW_USB0_USB0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_USB0_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_USB0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_USB1_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_USB1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_I2C0_GRP_INT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_I2C0_GRP_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], "PCW_I2C1_I2C1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_I2C_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PCW_I2C_RESET_SELECT": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PCW_GPIO_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], - "PCW_GPIO_MIO_GPIO_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], - "PCW_GPIO_MIO_GPIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_IO": [ { "value": "MIO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_0_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_0_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_1_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_1_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_2_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_2_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_3_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_3_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_4_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_4_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_5_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_5_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_6_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_6_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_7_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_7_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_8_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_8_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_9_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_9_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_10_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_10_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_11_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_11_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_14_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_14_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_15_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_15_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_19_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_19_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_20_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_20_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_22_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_22_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_23_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_23_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_24_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_24_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_25_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_25_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_26_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_26_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_27_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_27_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_28_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_28_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_29_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_29_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_30_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_30_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_31_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_31_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_32_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_32_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_33_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_33_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_34_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_34_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_35_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_35_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_36_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_36_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_37_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_37_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_38_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_38_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_39_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_39_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_40_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_40_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_41_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_41_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_42_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_42_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_43_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_43_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_44_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_44_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_45_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_45_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_46_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_46_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_47_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_47_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_48_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_48_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_49_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_49_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_50_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_50_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_51_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "PCW_MIO_51_SLEW": [ { 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