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zcy 2024-10-25 12:55:27 +08:00
parent 21f4731077
commit 7948e459e3
890 changed files with 752507 additions and 17604 deletions
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13
Packages/.repos.xml Normal file
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@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<repositories>
<repository>
<type>CMSIS Pack</type>
<name>Keil</name>
<url>http://www.keil.com/pack/index.idx</url>
</repository>
<repository>
<type>XCDL/CMSIS Pack</type>
<name>GNU ARM Eclipse</name>
<url>http://gnuarmeclipse.sourceforge.net/packages/content.xml</url>
</repository>
</repositories>

BIN
project_1/design_1_wrapper.xsa
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4
project_1/project_1.cache/wt/project.wpc
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@ -1,4 +1,4 @@
version:1 version:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:1 57656254616c6b5472616e736d697373696f6e417474656d70746564:8
6d6f64655f636f756e7465727c4755494d6f6465:1 6d6f64655f636f756e7465727c4755494d6f6465:4
eof: eof:

8
project_1/project_1.cache/wt/synthesis.wdf
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@ -41,7 +41,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333573:00:00 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333773:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313332302e3636304d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313330342e3436314d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3930362e3531364d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3838342e3331324d42:00:00
eof:2809958735 eof:2933133820

4
project_1/project_1.cache/wt/webtalk_pa.xml
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@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun Oct 20 22:20:28 2024"> <application name="pa" timeStamp="Fri Oct 25 01:50:11 2024">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="0163bad0787f46ce826c3743d9378f81" type="ProjectID"/> <property name="ProjectID" value="0163bad0787f46ce826c3743d9378f81" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/> <property name="ProjectIteration" value="29" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">

10
project_1/project_1.gen/sources_1/bd/design_1/design_1.bda
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@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

8
project_1/project_1.gen/sources_1/bd/design_1/design_1.bxml
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@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40"> <Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true"> <CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description> <Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1729431264"/> <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1729792018"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1729431264"/> <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1729792018"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1729431264"/> <Generation Name="SIMULATION" State="GENERATED" Timestamp="1729792018"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1729431264"/> <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1729792018"/>
<FileCollection Name="SOURCES" Type="SOURCES"> <FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.v" Type="Verilog"> <File Name="synth\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/> <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>

1
project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc
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@ -6,6 +6,5 @@
# This constraints file is not used in normal top-down synthesis (default flow # This constraints file is not used in normal top-down synthesis (default flow
# of Vivado) # of Vivado)
################################################################################ ################################################################################
create_clock -name processing_system7_0_FCLK_CLK0 -period 20 [get_pins processing_system7_0/FCLK_CLK0]
################################################################################ ################################################################################

2
project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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@ -1,7 +1,7 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024 //Date : Fri Oct 25 01:46:36 2024
//Host : destop1 running 64-bit major release (build 9200) //Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd //Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper //Design : design_1_wrapper

470
project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Oct 20 21:34:24 2024" VIVADOVERSION="2022.2"> <EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Oct 25 01:46:58 2024" VIVADOVERSION="2022.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z010" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/> <SYSTEMINFO ARCH="zynq" DEVICE="7z010" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
@ -14,12 +14,12 @@
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CKE"/> <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk_n"> <PORT DIR="IO" NAME="DDR_ck_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Clk_n">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/> <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk"> <PORT DIR="IO" NAME="DDR_ck_p" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Clk">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk"/> <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
</CONNECTIONS> </CONNECTIONS>
@ -29,7 +29,7 @@
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CS_n"/> <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB"> <PORT DIR="IO" NAME="DDR_reset_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DRSTB">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/> <CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
</CONNECTIONS> </CONNECTIONS>
@ -213,7 +213,7 @@
<PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/> <PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/>
<PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="0"/> <PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="0"/>
<PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/> <PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/>
<PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="TRUE"/> <PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="FALSE"/>
<PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/> <PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/>
<PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/> <PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/>
<PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/> <PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/>
@ -256,11 +256,11 @@
<PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/> <PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/>
<PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/> <PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/>
<PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/> <PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/>
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE"/> <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="FALSE"/>
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/> <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/>
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/> <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/>
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/> <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/>
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333"/> <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="350"/>
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/> <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/>
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15"/> <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15"/>
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/> <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/>
@ -326,7 +326,7 @@
<PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.068"/> <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.068"/>
<PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/> <PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/>
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333"/> <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333"/>
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666"/> <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="400"/>
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/> <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/>
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200"/> <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200"/>
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/> <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/>
@ -353,9 +353,9 @@
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50"/> <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50"/>
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50"/> <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50"/>
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/> <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/>
<PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="666.666687"/> <PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="400.000000"/>
<PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="533.333374"/> <PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="350.000000"/>
<PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.158730"/> <PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.144927"/>
<PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
@ -369,27 +369,27 @@
<PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/> <PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
<PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/> <PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
<PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/> <PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/>
<PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/> <PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
<PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/> <PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
<PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/> <PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
<PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50.000000"/> <PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/> <PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
<PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/> <PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="66.666672"/>
<PARAMETER NAME="PCW_CLK0_FREQ" VALUE="50000000"/> <PARAMETER NAME="PCW_CLK0_FREQ" VALUE="10000000"/>
<PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/> <PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/>
<PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/> <PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/>
<PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/> <PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/>
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/> <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/>
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2"/> <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="4"/>
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2"/> <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="4"/>
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1"/>
@ -397,11 +397,11 @@
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="6"/> <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="6"/>
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5"/> <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4"/> <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/>
@ -410,8 +410,8 @@
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/> <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/>
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15"/> <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="46"/>
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7"/> <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="3"/>
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5"/> <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5"/>
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
@ -420,12 +420,12 @@
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/> <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/>
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40"/> <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="48"/>
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30"/> <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30"/>
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32"/> <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="42"/>
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333"/> <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1600.000"/>
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000"/> <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000"/>
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667"/> <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1400.000"/>
<PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/> <PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/>
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="0"/> <PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="0"/>
<PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="1"/> <PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="1"/>
@ -546,7 +546,7 @@
<PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/> <PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/>
<PARAMETER NAME="PCW_EN_ENET0" VALUE="0"/> <PARAMETER NAME="PCW_EN_ENET0" VALUE="0"/>
<PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/> <PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/>
<PARAMETER NAME="PCW_EN_GPIO" VALUE="0"/> <PARAMETER NAME="PCW_EN_GPIO" VALUE="1"/>
<PARAMETER NAME="PCW_EN_I2C0" VALUE="0"/> <PARAMETER NAME="PCW_EN_I2C0" VALUE="0"/>
<PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/> <PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/>
<PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/> <PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/>
@ -568,11 +568,11 @@
<PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/> <PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/>
<PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/> <PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/>
<PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/> <PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/>
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1"/> <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="1"/> <PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/>
<PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/> <PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/>
@ -726,10 +726,10 @@
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 16 .. 21"/> <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 16 .. 21"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1"/> <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 18"/> <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 18"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="1"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="MIO 19"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="1"/>
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="MIO 20"/>
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="&lt;Select>"/>
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="0"/>
@ -792,8 +792,8 @@
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="&lt;Select>"/>
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1"/>
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO"/>
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="&lt;Select>"/>
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/> <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/>
@ -828,54 +828,54 @@
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/> <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/>
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/> <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/>
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/> <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/>
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out"/>
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled"/>
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out"/>
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled"/> <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V"/> <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out"/> <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out"/>
@ -884,14 +884,14 @@
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V"/> <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="in"/> <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="in"/>
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow"/> <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled"/> <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 3.3V"/> <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout"/> <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout"/>
@ -904,152 +904,152 @@
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 3.3V"/> <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout"/> <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow"/> <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out"/>
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out"/>
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled"/> <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 3.3V"/> <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout"/> <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow"/> <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow"/>
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled"/>
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 3.3V"/>
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout"/>
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="&lt;Select>"/> <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow"/>
<PARAMETER NAME="preset" VALUE="None"/> <PARAMETER NAME="preset" VALUE="None"/>
<PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/> <PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/>
<PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#SPI 0#SPI 0#SPI 0#unassigned#unassigned#SPI 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"/> <PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#GPIO#GPIO#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO"/>
<PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#sclk#miso#ss[0]#unassigned#unassigned#mosi#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"/> <PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#tx#rx#gpio[14]#gpio[15]#sclk#miso#ss[0]#ss[1]#ss[2]#mosi#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53]"/>
<PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/> <PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/>
<PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="1"/> <PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/>
<PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/> <PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/>
@ -1101,8 +1101,6 @@
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/> <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS> </PARAMETERS>
<PORTS> <PORTS>
<PORT CLKFREQUENCY="50000000" DIR="O" NAME="FCLK_CLK0" SIGIS="clk"/>
<PORT DIR="O" NAME="FCLK_RESET0_N" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
<PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO"> <PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="design_1_imp" PORT="FIXED_IO_mio"/> <CONNECTION INSTANCE="design_1_imp" PORT="FIXED_IO_mio"/>

BIN
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp
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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc
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@ -17,15 +17,236 @@
############################################################################ ############################################################################
# Clock constraints # # Clock constraints #
############################################################################ ############################################################################
create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
set_input_jitter clk_fpga_0 0.6
#The clocks are asynchronous, user should constrain them appropriately.#
############################################################################ ############################################################################
# I/O STANDARDS and Location Constraints # # I/O STANDARDS and Location Constraints #
############################################################################ ############################################################################
# GPIO / gpio[53] / MIO[53]
set_property iostandard "LVCMOS33" [get_ports "MIO[53]"]
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
set_property slew "slow" [get_ports "MIO[53]"]
set_property drive "8" [get_ports "MIO[53]"]
set_property pullup "TRUE" [get_ports "MIO[53]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
# GPIO / gpio[52] / MIO[52]
set_property iostandard "LVCMOS33" [get_ports "MIO[52]"]
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
set_property slew "slow" [get_ports "MIO[52]"]
set_property drive "8" [get_ports "MIO[52]"]
set_property pullup "TRUE" [get_ports "MIO[52]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[52]"]
# GPIO / gpio[51] / MIO[51]
set_property iostandard "LVCMOS33" [get_ports "MIO[51]"]
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
set_property slew "slow" [get_ports "MIO[51]"]
set_property drive "8" [get_ports "MIO[51]"]
set_property pullup "TRUE" [get_ports "MIO[51]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
# GPIO / gpio[50] / MIO[50]
set_property iostandard "LVCMOS33" [get_ports "MIO[50]"]
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
set_property slew "slow" [get_ports "MIO[50]"]
set_property drive "8" [get_ports "MIO[50]"]
set_property pullup "TRUE" [get_ports "MIO[50]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
# GPIO / gpio[49] / MIO[49]
set_property iostandard "LVCMOS33" [get_ports "MIO[49]"]
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
set_property slew "slow" [get_ports "MIO[49]"]
set_property drive "8" [get_ports "MIO[49]"]
set_property pullup "TRUE" [get_ports "MIO[49]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[49]"]
# GPIO / gpio[48] / MIO[48]
set_property iostandard "LVCMOS33" [get_ports "MIO[48]"]
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
set_property slew "slow" [get_ports "MIO[48]"]
set_property drive "8" [get_ports "MIO[48]"]
set_property pullup "TRUE" [get_ports "MIO[48]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[48]"]
# GPIO / gpio[47] / MIO[47]
set_property iostandard "LVCMOS33" [get_ports "MIO[47]"]
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
set_property slew "slow" [get_ports "MIO[47]"]
set_property drive "8" [get_ports "MIO[47]"]
set_property pullup "TRUE" [get_ports "MIO[47]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"]
# GPIO / gpio[46] / MIO[46]
set_property iostandard "LVCMOS33" [get_ports "MIO[46]"]
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
set_property slew "slow" [get_ports "MIO[46]"]
set_property drive "8" [get_ports "MIO[46]"]
set_property pullup "TRUE" [get_ports "MIO[46]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
# GPIO / gpio[45] / MIO[45]
set_property iostandard "LVCMOS33" [get_ports "MIO[45]"]
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
set_property slew "slow" [get_ports "MIO[45]"]
set_property drive "8" [get_ports "MIO[45]"]
set_property pullup "TRUE" [get_ports "MIO[45]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
# GPIO / gpio[44] / MIO[44]
set_property iostandard "LVCMOS33" [get_ports "MIO[44]"]
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
set_property slew "slow" [get_ports "MIO[44]"]
set_property drive "8" [get_ports "MIO[44]"]
set_property pullup "TRUE" [get_ports "MIO[44]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
# GPIO / gpio[43] / MIO[43]
set_property iostandard "LVCMOS33" [get_ports "MIO[43]"]
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
set_property slew "slow" [get_ports "MIO[43]"]
set_property drive "8" [get_ports "MIO[43]"]
set_property pullup "TRUE" [get_ports "MIO[43]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
# GPIO / gpio[42] / MIO[42]
set_property iostandard "LVCMOS33" [get_ports "MIO[42]"]
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
set_property slew "slow" [get_ports "MIO[42]"]
set_property drive "8" [get_ports "MIO[42]"]
set_property pullup "TRUE" [get_ports "MIO[42]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
# GPIO / gpio[41] / MIO[41]
set_property iostandard "LVCMOS33" [get_ports "MIO[41]"]
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
set_property slew "slow" [get_ports "MIO[41]"]
set_property drive "8" [get_ports "MIO[41]"]
set_property pullup "TRUE" [get_ports "MIO[41]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
# GPIO / gpio[40] / MIO[40]
set_property iostandard "LVCMOS33" [get_ports "MIO[40]"]
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
set_property slew "slow" [get_ports "MIO[40]"]
set_property drive "8" [get_ports "MIO[40]"]
set_property pullup "TRUE" [get_ports "MIO[40]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
# GPIO / gpio[39] / MIO[39]
set_property iostandard "LVCMOS33" [get_ports "MIO[39]"]
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
set_property slew "slow" [get_ports "MIO[39]"]
set_property drive "8" [get_ports "MIO[39]"]
set_property pullup "TRUE" [get_ports "MIO[39]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
# GPIO / gpio[38] / MIO[38]
set_property iostandard "LVCMOS33" [get_ports "MIO[38]"]
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
set_property slew "slow" [get_ports "MIO[38]"]
set_property drive "8" [get_ports "MIO[38]"]
set_property pullup "TRUE" [get_ports "MIO[38]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
# GPIO / gpio[37] / MIO[37]
set_property iostandard "LVCMOS33" [get_ports "MIO[37]"]
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
set_property slew "slow" [get_ports "MIO[37]"]
set_property drive "8" [get_ports "MIO[37]"]
set_property pullup "TRUE" [get_ports "MIO[37]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
# GPIO / gpio[36] / MIO[36]
set_property iostandard "LVCMOS33" [get_ports "MIO[36]"]
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
set_property slew "slow" [get_ports "MIO[36]"]
set_property drive "8" [get_ports "MIO[36]"]
set_property pullup "TRUE" [get_ports "MIO[36]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"]
# GPIO / gpio[35] / MIO[35]
set_property iostandard "LVCMOS33" [get_ports "MIO[35]"]
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
set_property slew "slow" [get_ports "MIO[35]"]
set_property drive "8" [get_ports "MIO[35]"]
set_property pullup "TRUE" [get_ports "MIO[35]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
# GPIO / gpio[34] / MIO[34]
set_property iostandard "LVCMOS33" [get_ports "MIO[34]"]
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
set_property slew "slow" [get_ports "MIO[34]"]
set_property drive "8" [get_ports "MIO[34]"]
set_property pullup "TRUE" [get_ports "MIO[34]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
# GPIO / gpio[33] / MIO[33]
set_property iostandard "LVCMOS33" [get_ports "MIO[33]"]
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
set_property slew "slow" [get_ports "MIO[33]"]
set_property drive "8" [get_ports "MIO[33]"]
set_property pullup "TRUE" [get_ports "MIO[33]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
# GPIO / gpio[32] / MIO[32]
set_property iostandard "LVCMOS33" [get_ports "MIO[32]"]
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
set_property slew "slow" [get_ports "MIO[32]"]
set_property drive "8" [get_ports "MIO[32]"]
set_property pullup "TRUE" [get_ports "MIO[32]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
# GPIO / gpio[31] / MIO[31]
set_property iostandard "LVCMOS33" [get_ports "MIO[31]"]
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
set_property slew "slow" [get_ports "MIO[31]"]
set_property drive "8" [get_ports "MIO[31]"]
set_property pullup "TRUE" [get_ports "MIO[31]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"]
# GPIO / gpio[30] / MIO[30]
set_property iostandard "LVCMOS33" [get_ports "MIO[30]"]
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
set_property slew "slow" [get_ports "MIO[30]"]
set_property drive "8" [get_ports "MIO[30]"]
set_property pullup "TRUE" [get_ports "MIO[30]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"]
# GPIO / gpio[29] / MIO[29]
set_property iostandard "LVCMOS33" [get_ports "MIO[29]"]
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
set_property slew "slow" [get_ports "MIO[29]"]
set_property drive "8" [get_ports "MIO[29]"]
set_property pullup "TRUE" [get_ports "MIO[29]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"]
# GPIO / gpio[28] / MIO[28]
set_property iostandard "LVCMOS33" [get_ports "MIO[28]"]
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
set_property slew "slow" [get_ports "MIO[28]"]
set_property drive "8" [get_ports "MIO[28]"]
set_property pullup "TRUE" [get_ports "MIO[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
# GPIO / gpio[27] / MIO[27]
set_property iostandard "LVCMOS33" [get_ports "MIO[27]"]
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
set_property slew "slow" [get_ports "MIO[27]"]
set_property drive "8" [get_ports "MIO[27]"]
set_property pullup "TRUE" [get_ports "MIO[27]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"]
# GPIO / gpio[26] / MIO[26]
set_property iostandard "LVCMOS33" [get_ports "MIO[26]"]
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
set_property slew "slow" [get_ports "MIO[26]"]
set_property drive "8" [get_ports "MIO[26]"]
set_property pullup "TRUE" [get_ports "MIO[26]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"]
# GPIO / gpio[25] / MIO[25]
set_property iostandard "LVCMOS33" [get_ports "MIO[25]"]
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
set_property slew "slow" [get_ports "MIO[25]"]
set_property drive "8" [get_ports "MIO[25]"]
set_property pullup "TRUE" [get_ports "MIO[25]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[25]"]
# GPIO / gpio[24] / MIO[24]
set_property iostandard "LVCMOS33" [get_ports "MIO[24]"]
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
set_property slew "slow" [get_ports "MIO[24]"]
set_property drive "8" [get_ports "MIO[24]"]
set_property pullup "TRUE" [get_ports "MIO[24]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[24]"]
# GPIO / gpio[23] / MIO[23]
set_property iostandard "LVCMOS33" [get_ports "MIO[23]"]
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
set_property slew "slow" [get_ports "MIO[23]"]
set_property drive "8" [get_ports "MIO[23]"]
set_property pullup "TRUE" [get_ports "MIO[23]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"]
# GPIO / gpio[22] / MIO[22]
set_property iostandard "LVCMOS33" [get_ports "MIO[22]"]
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
set_property slew "slow" [get_ports "MIO[22]"]
set_property drive "8" [get_ports "MIO[22]"]
set_property pullup "TRUE" [get_ports "MIO[22]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"]
# SPI 0 / mosi / MIO[21] # SPI 0 / mosi / MIO[21]
set_property iostandard "LVCMOS33" [get_ports "MIO[21]"] set_property iostandard "LVCMOS33" [get_ports "MIO[21]"]
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"] set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
@ -33,6 +254,20 @@ set_property slew "slow" [get_ports "MIO[21]"]
set_property drive "8" [get_ports "MIO[21]"] set_property drive "8" [get_ports "MIO[21]"]
set_property pullup "TRUE" [get_ports "MIO[21]"] set_property pullup "TRUE" [get_ports "MIO[21]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"] set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"]
# SPI 0 / ss[2] / MIO[20]
set_property iostandard "LVCMOS33" [get_ports "MIO[20]"]
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
set_property slew "slow" [get_ports "MIO[20]"]
set_property drive "8" [get_ports "MIO[20]"]
set_property pullup "TRUE" [get_ports "MIO[20]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
# SPI 0 / ss[1] / MIO[19]
set_property iostandard "LVCMOS33" [get_ports "MIO[19]"]
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
set_property slew "slow" [get_ports "MIO[19]"]
set_property drive "8" [get_ports "MIO[19]"]
set_property pullup "TRUE" [get_ports "MIO[19]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
# SPI 0 / ss[0] / MIO[18] # SPI 0 / ss[0] / MIO[18]
set_property iostandard "LVCMOS33" [get_ports "MIO[18]"] set_property iostandard "LVCMOS33" [get_ports "MIO[18]"]
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"] set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
@ -54,6 +289,20 @@ set_property slew "slow" [get_ports "MIO[16]"]
set_property drive "8" [get_ports "MIO[16]"] set_property drive "8" [get_ports "MIO[16]"]
set_property pullup "TRUE" [get_ports "MIO[16]"] set_property pullup "TRUE" [get_ports "MIO[16]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"] set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"]
# GPIO / gpio[15] / MIO[15]
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
set_property slew "slow" [get_ports "MIO[15]"]
set_property drive "8" [get_ports "MIO[15]"]
set_property pullup "TRUE" [get_ports "MIO[15]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
# GPIO / gpio[14] / MIO[14]
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
set_property slew "slow" [get_ports "MIO[14]"]
set_property drive "8" [get_ports "MIO[14]"]
set_property pullup "TRUE" [get_ports "MIO[14]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
# UART 1 / rx / MIO[13] # UART 1 / rx / MIO[13]
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"] set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"] set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
@ -68,6 +317,83 @@ set_property slew "slow" [get_ports "MIO[12]"]
set_property drive "8" [get_ports "MIO[12]"] set_property drive "8" [get_ports "MIO[12]"]
set_property pullup "TRUE" [get_ports "MIO[12]"] set_property pullup "TRUE" [get_ports "MIO[12]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[12]"] set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[12]"]
# GPIO / gpio[11] / MIO[11]
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
set_property slew "slow" [get_ports "MIO[11]"]
set_property drive "8" [get_ports "MIO[11]"]
set_property pullup "TRUE" [get_ports "MIO[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
# GPIO / gpio[10] / MIO[10]
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
set_property slew "slow" [get_ports "MIO[10]"]
set_property drive "8" [get_ports "MIO[10]"]
set_property pullup "TRUE" [get_ports "MIO[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
# GPIO / gpio[9] / MIO[9]
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
set_property slew "slow" [get_ports "MIO[9]"]
set_property drive "8" [get_ports "MIO[9]"]
set_property pullup "TRUE" [get_ports "MIO[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
# GPIO / gpio[8] / MIO[8]
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
set_property slew "slow" [get_ports "MIO[8]"]
set_property drive "8" [get_ports "MIO[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
# GPIO / gpio[7] / MIO[7]
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
set_property slew "slow" [get_ports "MIO[7]"]
set_property drive "8" [get_ports "MIO[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
# GPIO / gpio[6] / MIO[6]
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
set_property slew "slow" [get_ports "MIO[6]"]
set_property drive "8" [get_ports "MIO[6]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[6]"]
# GPIO / gpio[5] / MIO[5]
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
set_property slew "slow" [get_ports "MIO[5]"]
set_property drive "8" [get_ports "MIO[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
# GPIO / gpio[4] / MIO[4]
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
set_property slew "slow" [get_ports "MIO[4]"]
set_property drive "8" [get_ports "MIO[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
# GPIO / gpio[3] / MIO[3]
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
set_property slew "slow" [get_ports "MIO[3]"]
set_property drive "8" [get_ports "MIO[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
# GPIO / gpio[2] / MIO[2]
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
set_property slew "slow" [get_ports "MIO[2]"]
set_property drive "8" [get_ports "MIO[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
# GPIO / gpio[1] / MIO[1]
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
set_property slew "slow" [get_ports "MIO[1]"]
set_property drive "8" [get_ports "MIO[1]"]
set_property pullup "TRUE" [get_ports "MIO[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[1]"]
# GPIO / gpio[0] / MIO[0]
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
set_property slew "slow" [get_ports "MIO[0]"]
set_property drive "8" [get_ports "MIO[0]"]
set_property pullup "TRUE" [get_ports "MIO[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"] set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"] set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
set_property slew "FAST" [get_ports "DDR_VRP"] set_property slew "FAST" [get_ports "DDR_VRP"]

1768
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39
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
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@ -1,7 +1,7 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 // Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
// Date : Sun Oct 20 21:35:16 2024 // Date : Fri Oct 25 01:47:57 2024
// Host : destop1 running 64-bit major release (build 9200) // Host : destop1 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim // Command : write_verilog -force -mode funcsim
// d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v // d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
@ -15,9 +15,7 @@
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *) (* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *)
(* NotValidForBitStream *) (* NotValidForBitStream *)
module design_1_processing_system7_0_0 module design_1_processing_system7_0_0
(FCLK_CLK0, (MIO,
FCLK_RESET0_N,
MIO,
DDR_CAS_n, DDR_CAS_n,
DDR_CKE, DDR_CKE,
DDR_Clk_n, DDR_Clk_n,
@ -38,8 +36,6 @@ module design_1_processing_system7_0_0
PS_SRSTB, PS_SRSTB,
PS_CLK, PS_CLK,
PS_PORB); PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
@ -79,8 +75,6 @@ module design_1_processing_system7_0_0
wire DDR_VRN; wire DDR_VRN;
wire DDR_VRP; wire DDR_VRP;
wire DDR_WEB; wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO; wire [53:0]MIO;
wire PS_CLK; wire PS_CLK;
wire PS_PORB; wire PS_PORB;
@ -130,9 +124,11 @@ module design_1_processing_system7_0_0
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED; wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK0_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED; wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED; wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED; wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET0_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
@ -414,7 +410,7 @@ module design_1_processing_system7_0_0
(* C_EN_EMIO_ENET1 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *) (* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *) (* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
@ -462,7 +458,7 @@ module design_1_processing_system7_0_0
(* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} />/>" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={400} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={350} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS33} bidis={32} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={14} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1600.000} /><PLL domain={Memory} vco={1400.000} /><PLL domain={IO} vco={1000.000} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0), (.CAN0_PHY_RX(1'b0),
@ -581,7 +577,7 @@ module design_1_processing_system7_0_0
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0), .FCLK_CLK0(NLW_inst_FCLK_CLK0_UNCONNECTED),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED), .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED), .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED), .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
@ -589,7 +585,7 @@ module design_1_processing_system7_0_0
.FCLK_CLKTRIG1_N(1'b0), .FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0), .FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0), .FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET0_N(NLW_inst_FCLK_RESET0_N_UNCONNECTED),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
@ -1154,7 +1150,7 @@ endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *) (* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) (* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) (* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) (* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) (* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *) (* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
@ -1171,7 +1167,7 @@ endmodule
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) (* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *) (* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={400} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={350} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS33} bidis={32} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={14} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1600.000} /><PLL domain={Memory} vco={1400.000} /><PLL domain={IO} vco={1000.000} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX, (CAN0_PHY_TX,
CAN0_PHY_RX, CAN0_PHY_RX,
@ -2564,9 +2560,6 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
wire DDR_WEB; wire DDR_WEB;
wire ENET0_MDIO_T_n; wire ENET0_MDIO_T_n;
wire ENET1_MDIO_T_n; wire ENET1_MDIO_T_n;
wire FCLK_CLK0;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire I2C0_SCL_T_n; wire I2C0_SCL_T_n;
wire I2C0_SDA_T_n; wire I2C0_SDA_T_n;
wire I2C1_SCL_T_n; wire I2C1_SCL_T_n;
@ -3575,10 +3568,12 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
wire PS7_i_n_705; wire PS7_i_n_705;
wire PS7_i_n_706; wire PS7_i_n_706;
wire PS7_i_n_707; wire PS7_i_n_707;
wire PS7_i_n_708;
wire PS7_i_n_709; wire PS7_i_n_709;
wire PS7_i_n_71; wire PS7_i_n_71;
wire PS7_i_n_710; wire PS7_i_n_710;
wire PS7_i_n_711; wire PS7_i_n_711;
wire PS7_i_n_712;
wire PS7_i_n_713; wire PS7_i_n_713;
wire PS7_i_n_714; wire PS7_i_n_714;
wire PS7_i_n_715; wire PS7_i_n_715;
@ -3965,9 +3960,11 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
assign EVENT_STANDBYWFE[0] = \<const0> ; assign EVENT_STANDBYWFE[0] = \<const0> ;
assign EVENT_STANDBYWFI[1] = \<const0> ; assign EVENT_STANDBYWFI[1] = \<const0> ;
assign EVENT_STANDBYWFI[0] = \<const0> ; assign EVENT_STANDBYWFI[0] = \<const0> ;
assign FCLK_CLK0 = \<const0> ;
assign FCLK_CLK1 = \<const0> ; assign FCLK_CLK1 = \<const0> ;
assign FCLK_CLK2 = \<const0> ; assign FCLK_CLK2 = \<const0> ;
assign FCLK_CLK3 = \<const0> ; assign FCLK_CLK3 = \<const0> ;
assign FCLK_RESET0_N = \<const0> ;
assign FCLK_RESET1_N = \<const0> ; assign FCLK_RESET1_N = \<const0> ;
assign FCLK_RESET2_N = \<const0> ; assign FCLK_RESET2_N = \<const0> ;
assign FCLK_RESET3_N = \<const0> ; assign FCLK_RESET3_N = \<const0> ;
@ -5526,9 +5523,9 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
.EVENTEVENTO(PS7_i_n_88), .EVENTEVENTO(PS7_i_n_88),
.EVENTSTANDBYWFE({PS7_i_n_236,PS7_i_n_237}), .EVENTSTANDBYWFE({PS7_i_n_236,PS7_i_n_237}),
.EVENTSTANDBYWFI({PS7_i_n_238,PS7_i_n_239}), .EVENTSTANDBYWFI({PS7_i_n_238,PS7_i_n_239}),
.FCLKCLK({PS7_i_n_705,PS7_i_n_706,PS7_i_n_707,FCLK_CLK_unbuffered}), .FCLKCLK({PS7_i_n_705,PS7_i_n_706,PS7_i_n_707,PS7_i_n_708}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({PS7_i_n_709,PS7_i_n_710,PS7_i_n_711,FCLK_RESET0_N}), .FCLKRESETN({PS7_i_n_709,PS7_i_n_710,PS7_i_n_711,PS7_i_n_712}),
.FPGAIDLEN(1'b0), .FPGAIDLEN(1'b0),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(1'b0), .FTMDTRACEINCLOCK(1'b0),
@ -5945,10 +5942,6 @@ module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
(.IO(buffered_PS_SRSTB), (.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB)); .PAD(PS_SRSTB));
(* BOX_TYPE = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]), (.IO(buffered_MIO[0]),
.PAD(MIO[0])); .PAD(MIO[0]));

39
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl
View File

@ -1,7 +1,7 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- -------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
-- Date : Sun Oct 20 21:35:16 2024 -- Date : Fri Oct 25 01:47:57 2024
-- Host : destop1 running 64-bit major release (build 9200) -- Host : destop1 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -- Command : write_vhdl -force -mode funcsim
-- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl -- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl
@ -719,7 +719,7 @@ entity design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK1_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF : string;
@ -817,7 +817,7 @@ entity design_1_processing_system7_0_0_processing_system7_v5_5_processing_system
attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7"; attribute ORIG_REF_NAME of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string; attribute POWER : string;
attribute POWER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} />/>"; attribute POWER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={400} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={350} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS33} bidis={32} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={14} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1600.000} /><PLL domain={Memory} vco={1400.000} /><PLL domain={IO} vco={1000.000} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; attribute USE_TRACE_DATA_EDGE_DETECTOR of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7; end design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7;
@ -826,7 +826,6 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_
signal \<const0>\ : STD_LOGIC; signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC;
@ -1834,10 +1833,12 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_
signal PS7_i_n_705 : STD_LOGIC; signal PS7_i_n_705 : STD_LOGIC;
signal PS7_i_n_706 : STD_LOGIC; signal PS7_i_n_706 : STD_LOGIC;
signal PS7_i_n_707 : STD_LOGIC; signal PS7_i_n_707 : STD_LOGIC;
signal PS7_i_n_708 : STD_LOGIC;
signal PS7_i_n_709 : STD_LOGIC; signal PS7_i_n_709 : STD_LOGIC;
signal PS7_i_n_71 : STD_LOGIC; signal PS7_i_n_71 : STD_LOGIC;
signal PS7_i_n_710 : STD_LOGIC; signal PS7_i_n_710 : STD_LOGIC;
signal PS7_i_n_711 : STD_LOGIC; signal PS7_i_n_711 : STD_LOGIC;
signal PS7_i_n_712 : STD_LOGIC;
signal PS7_i_n_713 : STD_LOGIC; signal PS7_i_n_713 : STD_LOGIC;
signal PS7_i_n_714 : STD_LOGIC; signal PS7_i_n_714 : STD_LOGIC;
signal PS7_i_n_715 : STD_LOGIC; signal PS7_i_n_715 : STD_LOGIC;
@ -2180,7 +2181,6 @@ architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
@ -2371,9 +2371,11 @@ begin
EVENT_STANDBYWFE(0) <= \<const0>\; EVENT_STANDBYWFE(0) <= \<const0>\;
EVENT_STANDBYWFI(1) <= \<const0>\; EVENT_STANDBYWFI(1) <= \<const0>\;
EVENT_STANDBYWFI(0) <= \<const0>\; EVENT_STANDBYWFI(0) <= \<const0>\;
FCLK_CLK0 <= \<const0>\;
FCLK_CLK1 <= \<const0>\; FCLK_CLK1 <= \<const0>\;
FCLK_CLK2 <= \<const0>\; FCLK_CLK2 <= \<const0>\;
FCLK_CLK3 <= \<const0>\; FCLK_CLK3 <= \<const0>\;
FCLK_RESET0_N <= \<const0>\;
FCLK_RESET1_N <= \<const0>\; FCLK_RESET1_N <= \<const0>\;
FCLK_RESET2_N <= \<const0>\; FCLK_RESET2_N <= \<const0>\;
FCLK_RESET3_N <= \<const0>\; FCLK_RESET3_N <= \<const0>\;
@ -4037,12 +4039,12 @@ PS7_i: unisim.vcomponents.PS7
FCLKCLK(3) => PS7_i_n_705, FCLKCLK(3) => PS7_i_n_705,
FCLKCLK(2) => PS7_i_n_706, FCLKCLK(2) => PS7_i_n_706,
FCLKCLK(1) => PS7_i_n_707, FCLKCLK(1) => PS7_i_n_707,
FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLK(0) => PS7_i_n_708,
FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => PS7_i_n_709, FCLKRESETN(3) => PS7_i_n_709,
FCLKRESETN(2) => PS7_i_n_710, FCLKRESETN(2) => PS7_i_n_710,
FCLKRESETN(1) => PS7_i_n_711, FCLKRESETN(1) => PS7_i_n_711,
FCLKRESETN(0) => FCLK_RESET0_N, FCLKRESETN(0) => PS7_i_n_712,
FPGAIDLEN => '0', FPGAIDLEN => '0',
FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => '0', FTMDTRACEINCLOCK => '0',
@ -5380,11 +5382,6 @@ PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
IO => buffered_PS_SRSTB, IO => buffered_PS_SRSTB,
PAD => PS_SRSTB PAD => PS_SRSTB
); );
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map ( port map (
IO => buffered_MIO(0), IO => buffered_MIO(0),
@ -6164,8 +6161,6 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL; use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_0 is entity design_1_processing_system7_0_0 is
port ( port (
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC; DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC;
@ -6244,9 +6239,11 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET0_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
@ -6536,7 +6533,7 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is
attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK0_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF : string;
@ -6632,7 +6629,7 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is
attribute HW_HANDOFF : string; attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef"; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef";
attribute POWER : string; attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} />/>"; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={400} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={350} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS33} bidis={32} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={14} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1600.000} /><PLL domain={Memory} vco={1400.000} /><PLL domain={IO} vco={1000.000} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO : string;
@ -6647,13 +6644,9 @@ architecture STRUCTURE of design_1_processing_system7_0_0 is
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
@ -6783,7 +6776,7 @@ inst: entity work.design_1_processing_system7_0_0_processing_system7_v5_5_proces
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0, FCLK_CLK0 => NLW_inst_FCLK_CLK0_UNCONNECTED,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
@ -6791,7 +6784,7 @@ inst: entity work.design_1_processing_system7_0_0_processing_system7_v5_5_proces
FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0', FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET0_N => NLW_inst_FCLK_RESET0_N_UNCONNECTED,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,

12
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
View File

@ -1,7 +1,7 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 // Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
// Date : Sun Oct 20 21:35:16 2024 // Date : Fri Oct 25 01:47:57 2024
// Host : destop1 running 64-bit major release (build 9200) // Host : destop1 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub // Command : write_verilog -force -mode synth_stub
// d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v // d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
@ -14,12 +14,10 @@
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source. // Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2022.2" *)
module design_1_processing_system7_0_0(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, module design_1_processing_system7_0_0(MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk,
DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM,
DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; /* synthesis syn_black_box black_box_pad_pin="MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO; inout [53:0]MIO;
inout DDR_CAS_n; inout DDR_CAS_n;
inout DDR_CKE; inout DDR_CKE;

6
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl
View File

@ -1,7 +1,7 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- -------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
-- Date : Sun Oct 20 21:35:16 2024 -- Date : Fri Oct 25 01:47:57 2024
-- Host : destop1 running 64-bit major release (build 9200) -- Host : destop1 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -- Command : write_vhdl -force -mode synth_stub
-- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl -- d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.vhdl
@ -14,8 +14,6 @@ use IEEE.STD_LOGIC_1164.ALL;
entity design_1_processing_system7_0_0 is entity design_1_processing_system7_0_0 is
Port ( Port (
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC; DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC;
@ -45,7 +43,7 @@ architecture stub of design_1_processing_system7_0_0 is
attribute syn_black_box : boolean; attribute syn_black_box : boolean;
attribute black_box_pad_pin : string; attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true; attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute black_box_pad_pin of stub : architecture is "MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string; attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2022.2"; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2022.2";
begin begin

BIN
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/design_1_processing_system7_0_0.hwdef
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Binary file not shown.

12
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
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@ -149,13 +149,13 @@
// CR #682573 // CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports // Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} />/>" *) (*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={400} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={350} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS33} bidis={32} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={14} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p1} clockFreq={166.666672} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1600.000} /><PLL domain={Memory} vco={1400.000} /><PLL domain={IO} vco={1000.000} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ (* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=350, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\ , PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=400, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=48, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=42, PCW_CPU_CPU_PLL_FREQMHZ=1600.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1400.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 3.3V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\ , PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 3.3V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=0, PCW_QSPI_GRP_SINGLE_SS_ENABLE=0, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 12 .. 13, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=MIO 16 .. 21, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=MIO 18, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0\ , PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=0, PCW_QSPI_GRP_SINGLE_SS_ENABLE=0, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 12 .. 13, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=MIO 16 .. 21, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=MIO 18, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=MIO 19, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=MIO 20, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0\
, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL\ , PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) , PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=0, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7 module processing_system7_v5_5_processing_system7

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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c
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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h
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@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.html
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project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

5068
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c
View File

File diff suppressed because it is too large Load Diff

12
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

430
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml
View File

@ -4,8 +4,8 @@
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" > <MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
<PARAMETERS > <PARAMETERS >
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" /> <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" /> <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="400" />
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" /> <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="48" />
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" /> <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" /> <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
@ -22,21 +22,21 @@
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" /> <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" /> <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" /> <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" /> <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1600.000" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" /> <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" /> <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="4" />
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" /> <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" /> <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" /> <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="46" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" /> <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="3" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" /> <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" /> <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="42" />
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" /> <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1400.000" />
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" /> <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" /> <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" /> <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" /> <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" /> <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="4" />
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
@ -76,13 +76,13 @@
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" /> <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" /> <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" /> <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" /> <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" /> <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" /> <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" /> <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" /> <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" /> <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4" /> <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" /> <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" /> <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" /> <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
@ -92,7 +92,7 @@
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" /> <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" /> <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" /> <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" /> <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" /> <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" /> <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" /> <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
@ -110,8 +110,8 @@
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" /> <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" /> <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" /> <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" /> <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
@ -125,24 +125,24 @@
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" /> <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" /> <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" /> <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" /> <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" /> <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" /> <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out" /> <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" /> <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" /> <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
@ -151,14 +151,14 @@
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" /> <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" /> <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" /> <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" /> <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 3.3V" /> <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" /> <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
@ -171,182 +171,182 @@
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 3.3V" /> <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" /> <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" /> <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" /> <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 3.3V" /> <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" /> <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" /> <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" /> <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" /> <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" /> <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" /> <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" /> <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" /> <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" /> <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
@ -448,10 +448,10 @@
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" /> <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1" /> <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 18" /> <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 18" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" /> <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="MIO 19" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0" /> <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" /> <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="MIO 20" />
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1" /> <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 16 .. 21" /> <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 16 .. 21" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
@ -578,7 +578,7 @@
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" /> <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" /> <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" /> <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" /> <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="350" />
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" /> <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" /> <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" /> <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
@ -603,7 +603,7 @@
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" /> <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" /> <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" /> <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" /> <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" /> <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" /> <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
@ -634,7 +634,7 @@
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" /> <BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
</BUSINTERFACES> </BUSINTERFACES>
<CLOCKOUTS > <CLOCKOUTS >
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" /> <CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" /> <CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" /> <CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" /> <CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />

20
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.cpp
View File

@ -61,12 +61,10 @@
#ifdef XILINX_SIMULATOR #ifdef XILINX_SIMULATOR
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{ {
// initialize pins // initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO); mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE); mp_impl->DDR_CKE(DDR_CKE);
@ -101,12 +99,10 @@ void design_1_processing_system7_0_0::before_end_of_elaboration()
#ifdef XM_SYSTEMC #ifdef XM_SYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{ {
// initialize pins // initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO); mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE); mp_impl->DDR_CKE(DDR_CKE);
@ -141,12 +137,10 @@ void design_1_processing_system7_0_0::before_end_of_elaboration()
#ifdef RIVIERA #ifdef RIVIERA
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{ {
// initialize pins // initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO); mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE); mp_impl->DDR_CKE(DDR_CKE);
@ -181,11 +175,9 @@ void design_1_processing_system7_0_0::before_end_of_elaboration()
#ifdef VCSSYSTEMC #ifdef VCSSYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{ {
// initialize pins // initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO); mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE); mp_impl->DDR_CKE(DDR_CKE);
@ -223,11 +215,9 @@ void design_1_processing_system7_0_0::before_end_of_elaboration()
#ifdef MTI_SYSTEMC #ifdef MTI_SYSTEMC
design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB") design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{ {
// initialize pins // initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO); mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n); mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE); mp_impl->DDR_CKE(DDR_CKE);

10
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.h
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@ -80,8 +80,6 @@ public:
// module pin-to-pin RTL interface // module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE; sc_core::sc_out< bool > DDR_CKE;
@ -130,8 +128,6 @@ public:
// module pin-to-pin RTL interface // module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO; sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout< bool > DDR_CAS_n; sc_core::sc_inout< bool > DDR_CAS_n;
sc_core::sc_inout< bool > DDR_CKE; sc_core::sc_inout< bool > DDR_CKE;
@ -180,8 +176,6 @@ public:
// module pin-to-pin RTL interface // module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE; sc_core::sc_out< bool > DDR_CKE;
@ -230,8 +224,6 @@ public:
// module pin-to-pin RTL interface // module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE; sc_core::sc_out< bool > DDR_CKE;
@ -284,8 +276,6 @@ public:
// module pin-to-pin RTL interface // module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO; sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n; sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE; sc_core::sc_out< bool > DDR_CKE;

22
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.sv
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@ -677,8 +677,6 @@
//MODULE DECLARATION //MODULE DECLARATION
module design_1_processing_system7_0_0 ( module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO, MIO,
DDR_CAS_n, DDR_CAS_n,
DDR_CKE, DDR_CKE,
@ -753,7 +751,7 @@
parameter C_USE_S_AXI_HP3 = 0; parameter C_USE_S_AXI_HP3 = 0;
parameter C_USE_S_AXI_ACP = 0; parameter C_USE_S_AXI_ACP = 0;
parameter C_PS7_SI_REV = "PRODUCTION"; parameter C_PS7_SI_REV = "PRODUCTION";
parameter C_FCLK_CLK0_BUF = "TRUE"; parameter C_FCLK_CLK0_BUF = "FALSE";
parameter C_FCLK_CLK1_BUF = "FALSE"; parameter C_FCLK_CLK1_BUF = "FALSE";
parameter C_FCLK_CLK2_BUF = "FALSE"; parameter C_FCLK_CLK2_BUF = "FALSE";
parameter C_FCLK_CLK3_BUF = "FALSE"; parameter C_FCLK_CLK3_BUF = "FALSE";
@ -763,8 +761,6 @@
//INPUT AND OUTPUT PORTS //INPUT AND OUTPUT PORTS
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53 : 0] MIO; inout [53 : 0] MIO;
inout DDR_CAS_n; inout DDR_CAS_n;
inout DDR_CKE; inout DDR_CKE;
@ -789,8 +785,6 @@
//REG DECLARATIONS //REG DECLARATIONS
reg FCLK_CLK0;
reg FCLK_RESET0_N;
string ip_name; string ip_name;
reg disable_port; reg disable_port;
@ -799,7 +793,6 @@ import "DPI-C" function void ps7_set_ip_context(input string ip_name);
import "DPI-C" function void ps7_set_str_param(input string name,input string val); import "DPI-C" function void ps7_set_str_param(input string name,input string val);
import "DPI-C" function void ps7_set_int_param(input string name,input longint val); import "DPI-C" function void ps7_set_int_param(input string name,input longint val);
import "DPI-C" function void ps7_init_c_model(); import "DPI-C" function void ps7_init_c_model();
import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0();
export "DPI-C" function ps7_stop_sim; export "DPI-C" function ps7_stop_sim;
function void ps7_stop_sim(); function void ps7_stop_sim();
$display("End of simulation"); $display("End of simulation");
@ -895,18 +888,5 @@ import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0();
ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN ); ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN );
ps7_init_c_model(); ps7_init_c_model();
end end
initial
begin
FCLK_CLK0 = 1'b0;
end
always #(10.0) FCLK_CLK0 <= ~FCLK_CLK0;
always@(posedge FCLK_CLK0)
begin
ps7_set_ip_context(ip_name);
ps7_simulate_single_cycle_FCLK_CLK0();
end
endmodule endmodule

10
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v
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@ -56,8 +56,6 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module design_1_processing_system7_0_0 ( module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO, MIO,
DDR_CAS_n, DDR_CAS_n,
DDR_CKE, DDR_CKE,
@ -80,8 +78,6 @@ PS_SRSTB,
PS_CLK, PS_CLK,
PS_PORB PS_PORB
); );
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO; input [53 : 0] MIO;
input DDR_CAS_n; input DDR_CAS_n;
input DDR_CKE; input DDR_CKE;
@ -119,7 +115,7 @@ input PS_PORB;
.C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64), .C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0), .C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(50.0), .C_FCLK_CLK0_FREQ(10.0),
.C_FCLK_CLK1_FREQ(10.0), .C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0), .C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0), .C_FCLK_CLK3_FREQ(10.0),
@ -481,14 +477,14 @@ input PS_PORB;
.S_AXI_HP3_WID(6'B0), .S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0), .S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0), .S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0), .FCLK_CLK0(),
.FCLK_CLK1(), .FCLK_CLK1(),
.FCLK_CLK2(), .FCLK_CLK2(),
.FCLK_CLK3(), .FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET0_N(),
.FCLK_RESET1_N(), .FCLK_RESET1_N(),
.FCLK_RESET2_N(), .FCLK_RESET2_N(),
.FCLK_RESET3_N(), .FCLK_RESET3_N(),

2
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_sc.cpp
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@ -112,7 +112,7 @@ design_1_processing_system7_0_0_sc::design_1_processing_system7_0_0_sc(const sc_
model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1"); model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT"); model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
model_param_props.addString("C_PS7_SI_REV", "PRODUCTION"); model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE"); model_param_props.addString("C_FCLK_CLK0_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE"); model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");

6
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0_stub.sv
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@ -66,8 +66,6 @@ typedef bit bit_as_bool;
(* SC_MODULE_EXPORT *) (* SC_MODULE_EXPORT *)
module design_1_processing_system7_0_0 ( module design_1_processing_system7_0_0 (
output bit_as_bool FCLK_CLK0,
output bit_as_bool FCLK_RESET0_N,
output bit [53 : 0] MIO, output bit [53 : 0] MIO,
output bit_as_bool DDR_CAS_n, output bit_as_bool DDR_CAS_n,
output bit_as_bool DDR_CKE, output bit_as_bool DDR_CKE,
@ -95,11 +93,9 @@ endmodule
`ifdef XCELIUM `ifdef XCELIUM
(* XMSC_MODULE_EXPORT *) (* XMSC_MODULE_EXPORT *)
module design_1_processing_system7_0_0 (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB) module design_1_processing_system7_0_0 (MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
(* integer foreign = "SystemC"; (* integer foreign = "SystemC";
*); *);
output wire FCLK_CLK0;
output wire FCLK_RESET0_N;
inout wire [53 : 0] MIO; inout wire [53 : 0] MIO;
inout wire DDR_CAS_n; inout wire DDR_CAS_n;
inout wire DDR_CKE; inout wire DDR_CKE;

16
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.cpp
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@ -144,8 +144,6 @@ void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic
processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name, processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent
,FCLK_CLK0("FCLK_CLK0")
,FCLK_RESET0_N("FCLK_RESET0_N")
,MIO("MIO") ,MIO("MIO")
,DDR_CAS_n("DDR_CAS_n") ,DDR_CAS_n("DDR_CAS_n")
,DDR_CKE("DDR_CKE") ,DDR_CKE("DDR_CKE")
@ -167,7 +165,6 @@ processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_n
,PS_SRSTB("PS_SRSTB") ,PS_SRSTB("PS_SRSTB")
,PS_CLK("PS_CLK") ,PS_CLK("PS_CLK")
,PS_PORB("PS_PORB") ,PS_PORB("PS_PORB")
,FCLK_CLK0_clk("FCLK_CLK0_clk", sc_time(20000.0,sc_core::SC_PS))//clock period in picoseconds = 1000000/freq(in MZ)
,prop(_prop) ,prop(_prop)
{ {
//creating instances of xtlm slave sockets //creating instances of xtlm slave sockets
@ -202,27 +199,14 @@ processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_n
m_zynq_tlm_model->tie_off(); m_zynq_tlm_model->tie_off();
SC_METHOD(trigger_FCLK_CLK0_pin);
sensitive << FCLK_CLK0_clk;
dont_initialize();
m_zynq_tlm_model->rst(qemu_rst); m_zynq_tlm_model->rst(qemu_rst);
} }
processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() { processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() {
//deleteing dynamically created objects //deleteing dynamically created objects
} }
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void processing_system7_v5_5_tlm ::trigger_FCLK_CLK0_pin() {
FCLK_CLK0.write(FCLK_CLK0_clk.read());
}
//ps2pl_rst[0] output reset pin
void processing_system7_v5_5_tlm :: FCLK_RESET0_N_trigger() {
FCLK_RESET0_N.write(m_zynq_tlm_model->ps2pl_rst[0].read());
}
void processing_system7_v5_5_tlm ::start_of_simulation() void processing_system7_v5_5_tlm ::start_of_simulation()
{ {
//temporary fix to drive the enabled reset pin //temporary fix to drive the enabled reset pin
FCLK_RESET0_N.write(true);
qemu_rst.write(false); qemu_rst.write(false);
} }

9
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h
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@ -134,8 +134,6 @@ class processing_system7_v5_5_tlm : public sc_core::sc_module {
public: public:
// Non-AXI ports are declared here // Non-AXI ports are declared here
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO; sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n; sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE; sc_core::sc_inout<bool> DDR_CKE;
@ -192,16 +190,9 @@ processing_system7_v5_5_tlm(sc_core::sc_module_name name,
// sc_clocks for generating pl clocks // sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks // output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst; sc_signal<bool> qemu_rst;
void start_of_simulation(); void start_of_simulation();

18
project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v
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@ -54,12 +54,10 @@
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\ (* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\
ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\ ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\
_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=0,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TX\ _M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=0,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=FALSE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_T\
N=1,C_GP1_EN_MODIFIABLE_TXN=1}" *) XN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_processing_system7_0_0 ( module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO, MIO,
DDR_CAS_n, DDR_CAS_n,
DDR_CKE, DDR_CKE,
@ -83,12 +81,6 @@ module design_1_processing_system7_0_0 (
PS_PORB PS_PORB
); );
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO; inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
@ -184,7 +176,7 @@ inout wire PS_PORB;
.C_USE_S_AXI_HP3(0), .C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0), .C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"), .C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"), .C_FCLK_CLK0_BUF("FALSE"),
.C_FCLK_CLK1_BUF("FALSE"), .C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"), .C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"), .C_FCLK_CLK3_BUF("FALSE"),
@ -803,7 +795,7 @@ inout wire PS_PORB;
.DMA1_DRTYPE(2'B0), .DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0), .DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0), .DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0), .FCLK_CLK0(),
.FCLK_CLK1(), .FCLK_CLK1(),
.FCLK_CLK2(), .FCLK_CLK2(),
.FCLK_CLK3(), .FCLK_CLK3(),
@ -811,7 +803,7 @@ inout wire PS_PORB;
.FCLK_CLKTRIG1_N(1'B0), .FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0), .FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0), .FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET0_N(),
.FCLK_RESET1_N(), .FCLK_RESET1_N(),
.FCLK_RESET2_N(), .FCLK_RESET2_N(),
.FCLK_RESET3_N(), .FCLK_RESET3_N(),

2
project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v
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@ -1,7 +1,7 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024 //Date : Fri Oct 25 01:46:36 2024
//Host : destop1 running 64-bit major release (build 9200) //Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd //Command : generate_target design_1.bd
//Design : design_1 //Design : design_1

BIN
project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef
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Binary file not shown.

2
project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v
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@ -1,7 +1,7 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024 //Date : Fri Oct 25 01:46:36 2024
//Host : destop1 running 64-bit major release (build 9200) //Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd //Command : generate_target design_1.bd
//Design : design_1 //Design : design_1

15
project_1/project_1.hw/hw_1/hw.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2022.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<hwsession version="1" minor="2">
<device name="xc7z010_1" gui_info=""/>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7z010_1" gui_info="">
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/design_1_wrapper.bit"/>
<Properties Property="SLR.COUNT" value="1"/>
</Object>
</ObjectList>
<probeset name="hw project" active="false"/>
</hwsession>

4
project_1/project_1.hw/project_1.lpr
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@ -3,4 +3,6 @@
<!-- --> <!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/> <labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>

10
project_1/project_1.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v
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@ -56,8 +56,6 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module design_1_processing_system7_0_0 ( module design_1_processing_system7_0_0 (
FCLK_CLK0,
FCLK_RESET0_N,
MIO, MIO,
DDR_CAS_n, DDR_CAS_n,
DDR_CKE, DDR_CKE,
@ -80,8 +78,6 @@ PS_SRSTB,
PS_CLK, PS_CLK,
PS_PORB PS_PORB
); );
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO; input [53 : 0] MIO;
input DDR_CAS_n; input DDR_CAS_n;
input DDR_CKE; input DDR_CKE;
@ -119,7 +115,7 @@ input PS_PORB;
.C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64), .C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0), .C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(50.0), .C_FCLK_CLK0_FREQ(10.0),
.C_FCLK_CLK1_FREQ(10.0), .C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0), .C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0), .C_FCLK_CLK3_FREQ(10.0),
@ -481,14 +477,14 @@ input PS_PORB;
.S_AXI_HP3_WID(6'B0), .S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0), .S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0), .S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0), .FCLK_CLK0(),
.FCLK_CLK1(), .FCLK_CLK1(),
.FCLK_CLK2(), .FCLK_CLK2(),
.FCLK_CLK3(), .FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET0_N(),
.FCLK_RESET1_N(), .FCLK_RESET1_N(),
.FCLK_RESET2_N(), .FCLK_RESET2_N(),
.FCLK_RESET3_N(), .FCLK_RESET3_N(),

2
project_1/project_1.ip_user_files/bd/design_1/sim/design_1.v
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@ -1,7 +1,7 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 //Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
//Date : Sun Oct 20 21:34:05 2024 //Date : Fri Oct 25 01:46:36 2024
//Host : destop1 running 64-bit major release (build 9200) //Host : destop1 running 64-bit major release (build 9200)
//Command : generate_target design_1.bd //Command : generate_target design_1.bd
//Design : design_1 //Design : design_1

10
project_1/project_1.ip_user_files/mem_init_files/design_1.bda
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@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

12
project_1/project_1.ip_user_files/mem_init_files/ps7_init.h
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@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/mem_init_files/ps7_init.html
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312
project_1/project_1.ip_user_files/mem_init_files/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/mem_init_files/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

7
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10
@ -90,11 +90,10 @@ setup()
map_setup_file() map_setup_file()
{ {
file="library.cfg" file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>" if [[ ($1 != "") ]]; then
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1" lib_map_path="$1"
else else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/activehdl"
fi fi
if [[ ($lib_map_path != "") ]]; then if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file" src_file="$lib_map_path/$file"

12
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.html
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File diff suppressed because it is too large Load Diff

312
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init.tcl
View File

@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/activehdl/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

7
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10
@ -92,11 +92,10 @@ setup()
copy_setup_file() copy_setup_file()
{ {
file="modelsim.ini" file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>" if [[ ($1 != "") ]]; then
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1" lib_map_path="$1"
else else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/modelsim"
fi fi
if [[ ($lib_map_path != "") ]]; then if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file" src_file="$lib_map_path/$file"

12
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.html
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project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/modelsim/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

7
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10
@ -99,11 +99,10 @@ setup()
copy_setup_file() copy_setup_file()
{ {
file="modelsim.ini" file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>" if [[ ($1 != "") ]]; then
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1" lib_map_path="$1"
else else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/questa"
fi fi
if [[ ($lib_map_path != "") ]]; then if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file" src_file="$lib_map_path/$file"

12
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.html
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File diff suppressed because it is too large Load Diff

312
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init.tcl
View File

@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/questa/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

7
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/design_1.sh
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@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10
@ -90,11 +90,10 @@ setup()
map_setup_file() map_setup_file()
{ {
file="library.cfg" file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>" if [[ ($1 != "") ]]; then
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path="$1" lib_map_path="$1"
else else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" lib_map_path="D:/project/hdl/zynq_lvgl/project_1/project_1.cache/compile_simlib/riviera"
fi fi
if [[ ($lib_map_path != "") ]]; then if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file" src_file="$lib_map_path/$file"

12
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.html
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312
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/riviera/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

2
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10

12
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.html
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File diff suppressed because it is too large Load Diff

312
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/vcs/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

2
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10

12
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.html
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File diff suppressed because it is too large Load Diff

312
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init.tcl
View File

@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/xcelium/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

2
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/README.txt
View File

@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to # README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files. # run the exported script and information about the source files.
# #
# Generated by export_simulation on Sun Oct 20 21:34:26 +0800 2024 # Generated by export_simulation on Fri Oct 25 01:47:00 +0800 2024
# #
################################################################################ ################################################################################

10
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.bda
View File

@ -23,9 +23,8 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/> <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0"> <node id="n0">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">VR</data> <data key="VT">BC</data>
</node> </node>
<node id="n1"> <node id="n1">
<data key="TU">active</data> <data key="TU">active</data>
@ -33,10 +32,11 @@
<data key="VT">PM</data> <data key="VT">PM</data>
</node> </node>
<node id="n2"> <node id="n2">
<data key="VH">2</data>
<data key="VM">design_1</data> <data key="VM">design_1</data>
<data key="VT">BC</data> <data key="VT">VR</data>
</node> </node>
<edge id="e0" source="n2" target="n0"/> <edge id="e0" source="n0" target="n2"/>
<edge id="e1" source="n0" target="n1"/> <edge id="e1" source="n2" target="n1"/>
</graph> </graph>
</graphml> </graphml>

2
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/design_1.sh
View File

@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default # directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps. # 'do/prj' file, execute compilation, elaboration and simulation steps.
# #
# Generated by Vivado on Sun Oct 20 21:34:26 +0800 2024 # Generated by Vivado on Fri Oct 25 01:47:00 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# #
# Tool Version Limit: 2022.10 # Tool Version Limit: 2022.10

12
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.h
View File

@ -70,9 +70,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -82,13 +82,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

42848
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.html
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File diff suppressed because it is too large Load Diff

312
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init.tcl
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@ -1,21 +1,21 @@
proc ps7_pll_init_data_3_0 {} { proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -27,30 +27,30 @@ proc ps7_pll_init_data_3_0 {} {
} }
proc ps7_clock_init_data_3_0 {} { proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_3_0 {} { proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x0007FFFF 0x00001082 mask_write 0XF8006004 0x0007FFFF 0x00001055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000 mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00000003 0x00000000 mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -63,11 +63,11 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -81,10 +81,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF800611C 0x7FFFFFCF 0x40000001 mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000000 mask_write 0XF8006120 0x7FFFFFCF 0x40000000
mask_write 0XF8006124 0x7FFFFFCF 0x40000000 mask_write 0XF8006124 0x7FFFFFCF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -93,10 +93,10 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -114,8 +114,8 @@ proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000 mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -137,12 +137,60 @@ proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000B70 0x00000001 0x00000001 mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823 mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_3_0 {} { proc ps7_peripherals_init_data_3_0 {} {
@ -172,22 +220,22 @@ proc ps7_debug_3_0 {} {
} }
proc ps7_pll_init_data_2_0 {} { proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -199,30 +247,30 @@ proc ps7_pll_init_data_2_0 {} {
} }
proc ps7_clock_init_data_2_0 {} { proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_2_0 {} { proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -235,12 +283,12 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006064 0x00021FE0 0x00020000 mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141 mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111 mask_write 0XF8006078 0x03FFFFFF 0x00455111
mask_write 0XF800607C 0x000FFFFF 0x00032222 mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -254,10 +302,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -266,10 +314,10 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -287,8 +335,8 @@ proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -310,12 +358,60 @@ proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_2_0 {} { proc ps7_peripherals_init_data_2_0 {} {
@ -345,22 +441,22 @@ proc ps7_debug_2_0 {} {
} }
proc ps7_pll_init_data_1_0 {} { proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220 mask_write 0XF8000110 0x003FFFF0 0x000FA240
mask_write 0XF8000100 0x0007F000 0x00028000 mask_write 0XF8000100 0x0007F000 0x00030000
mask_write 0XF8000100 0x00000010 0x00000010 mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001 mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000 mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001 mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000 mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200 mask_write 0XF8000120 0x1F003F30 0x1F000400
mask_write 0XF8000114 0x003FFFF0 0x0012C220 mask_write 0XF8000114 0x003FFFF0 0x000FA3C0
mask_write 0XF8000104 0x0007F000 0x00020000 mask_write 0XF8000104 0x0007F000 0x0002A000
mask_write 0XF8000104 0x00000010 0x00000010 mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001 mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000 mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002 mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000 mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003 mask_write 0XF8000124 0xFFF00003 0x18400003
mask_write 0XF8000118 0x003FFFF0 0x001452C0 mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000 mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010 mask_write 0XF8000108 0x00000010 0x00000010
@ -372,30 +468,30 @@ proc ps7_pll_init_data_1_0 {} {
} }
proc ps7_clock_init_data_1_0 {} { proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01 mask_write 0XF8000128 0x03F03F01 0x00302E01
mask_write 0XF8000154 0x00003F33 0x00000A02 mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000158 0x00003F33 0x00000601
mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00400500 mask_write 0XF8000170 0x03F03F30 0x00400800
mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x016C400D mask_write 0XF800012C 0x01FFCCCD 0x016C400D
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_ddr_init_data_1_0 {} { proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000084 mask_write 0XF8006000 0x0001FFFF 0x00000084
mask_write 0XF8006004 0x1FFFFFFF 0x00081082 mask_write 0XF8006004 0x1FFFFFFF 0x00081055
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001 mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001 mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B mask_write 0XF8006014 0x001FFFFF 0x00041A52
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 mask_write 0XF8006018 0xF7FFFFFF 0x435738D0
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 mask_write 0XF800601C 0xFFFFFFFF 0x7201B8E5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007 mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008 mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 mask_write 0XF8006030 0xFFFFFFFF 0x00040530
mask_write 0XF8006034 0x13FF3FFF 0x000116D4 mask_write 0XF8006034 0x13FF3FFF 0x00010F04
mask_write 0XF8006038 0x00001FC3 0x00000000 mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000666 mask_write 0XF800603C 0x000FFFFF 0x00000666
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
@ -410,8 +506,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800606C 0x0000FFFF 0x00001610 mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000 mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 mask_write 0XF80060A8 0x0FFFFFFF 0x04508583
mask_write 0XF80060AC 0x000001FF 0x000001FE mask_write 0XF80060AC 0x000001FF 0x00000156
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066 mask_write 0XF80060B8 0x01FFFFFF 0x00200066
@ -425,10 +521,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF800611C 0x7FFFFFFF 0x40000001 mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000000 mask_write 0XF8006120 0x7FFFFFFF 0x40000000
mask_write 0XF8006124 0x7FFFFFFF 0x40000000 mask_write 0XF8006124 0x7FFFFFFF 0x40000000
mask_write 0XF800612C 0x000FFFFF 0x00029000 mask_write 0XF800612C 0x000FFFFF 0x00023000
mask_write 0XF8006130 0x000FFFFF 0x00029000 mask_write 0XF8006130 0x000FFFFF 0x00023000
mask_write 0XF8006134 0x000FFFFF 0x00029000 mask_write 0XF8006134 0x000FFFFF 0x00023000
mask_write 0XF8006138 0x000FFFFF 0x00029000 mask_write 0XF8006138 0x000FFFFF 0x00023000
mask_write 0XF8006140 0x000FFFFF 0x00000035 mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035 mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035 mask_write 0XF8006148 0x000FFFFF 0x00000035
@ -437,10 +533,10 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006158 0x000FFFFF 0x00000080 mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080 mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080 mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9 mask_write 0XF8006168 0x001FFFFF 0x000000E1
mask_write 0XF800616C 0x001FFFFF 0x000000F9 mask_write 0XF800616C 0x001FFFFF 0x000000E1
mask_write 0XF8006170 0x001FFFFF 0x000000F9 mask_write 0XF8006170 0x001FFFFF 0x000000E1
mask_write 0XF8006174 0x001FFFFF 0x000000F9 mask_write 0XF8006174 0x001FFFFF 0x000000E1
mask_write 0XF800617C 0x000FFFFF 0x000000C0 mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0 mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0 mask_write 0XF8006184 0x000FFFFF 0x000000C0
@ -458,8 +554,8 @@ proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006224 0x000F03FF 0x000003FF mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000 mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125 mask_write 0XF80062B0 0x003FFFFF 0x000050C5
mask_write 0XF80062B4 0x0003FFFF 0x000012A8 mask_write 0XF80062B4 0x0003FFFF 0x00000C6F
mask_poll 0XF8000B74 0x00002000 mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000085 mask_write 0XF8006000 0x0001FFFF 0x00000085
mask_poll 0XF8006054 0x00000007 mask_poll 0XF8006054 0x00000007
@ -481,12 +577,60 @@ proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000B70 0x00000021 0x00000021 mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020 mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823 mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003FFF 0x00001600
mask_write 0XF8000704 0x00003FFF 0x00001600
mask_write 0XF8000708 0x00003FFF 0x00000600
mask_write 0XF800070C 0x00003FFF 0x00000600
mask_write 0XF8000710 0x00003FFF 0x00000600
mask_write 0XF8000714 0x00003FFF 0x00000600
mask_write 0XF8000718 0x00003FFF 0x00000600
mask_write 0XF800071C 0x00003FFF 0x00000600
mask_write 0XF8000720 0x00003FFF 0x00000600
mask_write 0XF8000724 0x00003FFF 0x00001600
mask_write 0XF8000728 0x00003FFF 0x00001600
mask_write 0XF800072C 0x00003FFF 0x00001600
mask_write 0XF8000730 0x00003FFF 0x000016E0 mask_write 0XF8000730 0x00003FFF 0x000016E0
mask_write 0XF8000734 0x00003FFF 0x000016E1 mask_write 0XF8000734 0x00003FFF 0x000016E1
mask_write 0XF8000738 0x00003FFF 0x00001600
mask_write 0XF800073C 0x00003FFF 0x00001600
mask_write 0XF8000740 0x00003FFF 0x000016A0 mask_write 0XF8000740 0x00003FFF 0x000016A0
mask_write 0XF8000744 0x00003FFF 0x000016A0 mask_write 0XF8000744 0x00003FFF 0x000016A0
mask_write 0XF8000748 0x00003FFF 0x000016A0 mask_write 0XF8000748 0x00003FFF 0x000016A0
mask_write 0XF800074C 0x00003FFF 0x000016A0
mask_write 0XF8000750 0x00003FFF 0x000016A0
mask_write 0XF8000754 0x00003FFF 0x000016A0 mask_write 0XF8000754 0x00003FFF 0x000016A0
mask_write 0XF8000758 0x00003FFF 0x00001600
mask_write 0XF800075C 0x00003FFF 0x00001600
mask_write 0XF8000760 0x00003FFF 0x00001600
mask_write 0XF8000764 0x00003FFF 0x00001600
mask_write 0XF8000768 0x00003FFF 0x00001600
mask_write 0XF800076C 0x00003FFF 0x00001600
mask_write 0XF8000770 0x00003FFF 0x00001600
mask_write 0XF8000774 0x00003FFF 0x00001600
mask_write 0XF8000778 0x00003FFF 0x00001600
mask_write 0XF800077C 0x00003FFF 0x00001600
mask_write 0XF8000780 0x00003FFF 0x00001600
mask_write 0XF8000784 0x00003FFF 0x00001600
mask_write 0XF8000788 0x00003FFF 0x00001600
mask_write 0XF800078C 0x00003FFF 0x00001600
mask_write 0XF8000790 0x00003FFF 0x00001600
mask_write 0XF8000794 0x00003FFF 0x00001600
mask_write 0XF8000798 0x00003FFF 0x00001600
mask_write 0XF800079C 0x00003FFF 0x00001600
mask_write 0XF80007A0 0x00003FFF 0x00001600
mask_write 0XF80007A4 0x00003FFF 0x00001600
mask_write 0XF80007A8 0x00003FFF 0x00001600
mask_write 0XF80007AC 0x00003FFF 0x00001600
mask_write 0XF80007B0 0x00003FFF 0x00001600
mask_write 0XF80007B4 0x00003FFF 0x00001600
mask_write 0XF80007B8 0x00003FFF 0x00001600
mask_write 0XF80007BC 0x00003FFF 0x00001600
mask_write 0XF80007C0 0x00003FFF 0x00001600
mask_write 0XF80007C4 0x00003FFF 0x00001600
mask_write 0XF80007C8 0x00003FFF 0x00001600
mask_write 0XF80007CC 0x00003FFF 0x00001600
mask_write 0XF80007D0 0x00003FFF 0x00001600
mask_write 0XF80007D4 0x00003FFF 0x00001600
mwr -force 0XF8000004 0x0000767B mwr -force 0XF8000004 0x0000767B
} }
proc ps7_peripherals_init_data_1_0 {} { proc ps7_peripherals_init_data_1_0 {} {
@ -517,7 +661,7 @@ proc ps7_debug_1_0 {} {
set PCW_SILICON_VER_1_0 "0x0" set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1" set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2" set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666 set APU_FREQ 400000000

12
project_1/project_1.ip_user_files/sim_scripts/design_1/xsim/ps7_init_gpl.h
View File

@ -84,9 +84,9 @@ extern unsigned long * ps7_peripherals_init_data;
/* Freq of all peripherals */ /* Freq of all peripherals */
#define APU_FREQ 666666687 #define APU_FREQ 400000000
#define DDR_FREQ 533333374 #define DDR_FREQ 350000000
#define DCI_FREQ 10158730 #define DCI_FREQ 10144927
#define QSPI_FREQ 10000000 #define QSPI_FREQ 10000000
#define SMC_FREQ 10000000 #define SMC_FREQ 10000000
#define ENET0_FREQ 10000000 #define ENET0_FREQ 10000000
@ -96,13 +96,13 @@ extern unsigned long * ps7_peripherals_init_data;
#define SDIO_FREQ 10000000 #define SDIO_FREQ 10000000
#define UART_FREQ 100000000 #define UART_FREQ 100000000
#define SPI_FREQ 166666672 #define SPI_FREQ 166666672
#define I2C_FREQ 111111115 #define I2C_FREQ 66666664
#define WDT_FREQ 111111115 #define WDT_FREQ 66666672
#define TTC_FREQ 50000000 #define TTC_FREQ 50000000
#define CAN_FREQ 10000000 #define CAN_FREQ 10000000
#define PCAP_FREQ 200000000 #define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000 #define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000 #define FPGA0_FREQ 10000000
#define FPGA1_FREQ 10000000 #define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000 #define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000 #define FPGA3_FREQ 10000000

12
project_1/project_1.runs/.jobs/vrs_config_10.xml Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

9
project_1/project_1.runs/.jobs/vrs_config_11.xml Normal file
View File

@ -0,0 +1,9 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

12
project_1/project_1.runs/.jobs/vrs_config_12.xml Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

9
project_1/project_1.runs/.jobs/vrs_config_13.xml Normal file
View File

@ -0,0 +1,9 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="design_1_processing_system7_0_0_synth_1" LaunchDir="D:/project/hdl/zynq_lvgl/project_1/project_1.runs/design_1_processing_system7_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

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