zcy 21f4731077 zynq lvgl init		2024-10-20 23:34:36 +08:00
..
.init_design.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.init_design.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.opt_design.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.opt_design.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.phys_opt_design.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.phys_opt_design.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.place_design.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.place_design.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.route_design.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.route_design.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.Vivado_Implementation.queue.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.vivado.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.vivado.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.write_bitstream.begin.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
.write_bitstream.end.rst	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_bus_skew_routed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_bus_skew_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_bus_skew_routed.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_clock_utilization_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_control_sets_placed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_opted.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_opted.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_opted.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_routed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_drc_routed.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_io_placed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_methodology_drc_routed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_methodology_drc_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_methodology_drc_routed.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_opt.dcp	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_physopt.dcp	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_placed.dcp	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_power_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_power_routed.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_power_summary_routed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_route_status.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_route_status.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_routed.dcp	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_timing_summary_routed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_timing_summary_routed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_timing_summary_routed.rpx	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_utilization_placed.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper_utilization_placed.rpt	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper.bit	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper.tcl	zynq lvgl init	2024-10-20 23:34:36 +08:00
design_1_wrapper.vdi	zynq lvgl init	2024-10-20 23:34:36 +08:00
gen_run.xml	zynq lvgl init	2024-10-20 23:34:36 +08:00
htr.txt	zynq lvgl init	2024-10-20 23:34:36 +08:00
init_design.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
ISEWrap.js	zynq lvgl init	2024-10-20 23:34:36 +08:00
ISEWrap.sh	zynq lvgl init	2024-10-20 23:34:36 +08:00
opt_design.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
phys_opt_design.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
place_design.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
project.wdf	zynq lvgl init	2024-10-20 23:34:36 +08:00
route_design.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
rundef.js	zynq lvgl init	2024-10-20 23:34:36 +08:00
runme.bat	zynq lvgl init	2024-10-20 23:34:36 +08:00
runme.log	zynq lvgl init	2024-10-20 23:34:36 +08:00
runme.sh	zynq lvgl init	2024-10-20 23:34:36 +08:00
vivado.jou	zynq lvgl init	2024-10-20 23:34:36 +08:00
vivado.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00
write_bitstream.pb	zynq lvgl init	2024-10-20 23:34:36 +08:00