445 lines
24 KiB
Plaintext
445 lines
24 KiB
Plaintext
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*** Running vivado
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with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
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****** Vivado v2022.2 (64-bit)
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**** SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
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**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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source design_1_wrapper.tcl -notrace
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create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 374.613 ; gain = 63.391
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'.
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Command: link_design -top design_1_wrapper -part xc7z010clg400-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Device 21-403] Loading part xc7z010clg400-1
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INFO: [Project 1-454] Reading design checkpoint 'd:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0'
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 819.367 ; gain = 0.000
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INFO: [Project 1-479] Netlist was created with Vivado 2022.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc]
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Finished Parsing XDC File [D:/project/hdl/zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 945.301 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 945.301 ; gain = 529.055
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 973.383 ; gain = 28.082
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: 13ac7fd5f
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1430.504 ; gain = 457.121
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 13aa10cfc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 13aa10cfc
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: a740edb4
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: a740edb4
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
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Phase 5 Shift Register Optimization | Checksum: a740edb4
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: a740edb4
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 24 | 0 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 18965390f
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.174 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 18965390f
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: 18965390f
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: 18965390f
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1764.969 ; gain = 819.668
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
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Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.404 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 18d9a5a3a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.440 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 18d9a5a3a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.442 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 1 Placer Initialization | Checksum: 18d9a5a3a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.443 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Phase 2 Final Placement Cleanup
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
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Ending Placer Task | Checksum: 9477fc6b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.446 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1764.969 ; gain = 0.000
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Command: phys_opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
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Starting Initial Update Timing Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1764.969 ; gain = 0.000
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INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
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INFO: [Common 17-83] Releasing license: Implementation
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52 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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phys_opt_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1774.996 ; gain = 10.027
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Phase 1 Build RT Design
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Checksum: PlaceDB: 401615bb ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0
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Post Restoration Checksum: NetGraph: 752172cc NumContArr: 683b9ea3 Constraints: 0 Timing: 0
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Phase 1 Build RT Design | Checksum: dd5d116f
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1814.922 ; gain = 30.887
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: dd5d116f
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: dd5d116f
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1820.980 ; gain = 36.945
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Number of Nodes with overlaps = 0
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Router Utilization Summary
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Global Vertical Routing Utilization = 0 %
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Global Horizontal Routing Utilization = 0 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 130
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 130
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Phase 2 Router Initialization | Checksum: f1e72516
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 3 Initial Routing
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Phase 3.1 Global Routing
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Phase 3.1 Global Routing | Checksum: f1e72516
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Number of Nodes with overlaps = 0
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Phase 3 Initial Routing | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Phase 4.1 Global Iteration 0 | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 4 Rip-up And Reroute | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 6 Post Hold Fix | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0 %
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Global Horizontal Routing Utilization = 0 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: East
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: West
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Phase 7 Route finalize | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.309 ; gain = 39.273
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: 9afecd01
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1824.324 ; gain = 40.289
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 1824.324 ; gain = 49.328
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1838.148 ; gain = 13.824
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INFO: [Common 17-1381] The checkpoint 'D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
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Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
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Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/project/hdl/zynq_lvgl/project_1/project_1.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
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Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
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Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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74 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
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INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
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INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
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INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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Command: write_bitstream -force design_1_wrapper.bit
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
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Running DRC as a precondition to command write_bitstream
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado 12-3199] DRC finished with 0 Errors
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
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INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
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Loading data files...
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Loading site data...
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Loading route data...
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream ./design_1_wrapper.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
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INFO: [Common 17-83] Releasing license: Implementation
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12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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|
write_bitstream completed successfully
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write_bitstream: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2291.984 ; gain = 432.449
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INFO: [Common 17-206] Exiting Vivado at Fri Oct 25 01:52:25 2024...
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