13 lines
662 B
Tcl
13 lines
662 B
Tcl
# This file is automatically generated.
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# It contains project source information necessary for synthesis and implementation.
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# XDC: new/test.xdc
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# Block Designs: bd/design_1/design_1.bd
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set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1 || ORIG_REF_NAME==design_1} -quiet] -quiet
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# IP: bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
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set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_processing_system7_0_0 || ORIG_REF_NAME==design_1_processing_system7_0_0} -quiet] -quiet
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# XDC: d:/project/hdl/zynq_lvgl/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc
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