zynq_lvgl/project_1/project_1.srcs/constrs_1/new/test.xdc
2024-10-25 12:55:27 +08:00

8 lines
433 B
Tcl

#set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports SPI0_MISO_I_0]
#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports SPI0_MOSI_O_0]
#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports SPI0_SCLK_O_0]
#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports SPI0_SS_O_0]
#set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports GPIO_O_0[0]]