540 lines
21 KiB
C
540 lines
21 KiB
C
/******************************************************************************
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* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file fsbl.h
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*
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* Contains the function prototypes, defines and macros for the
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* First Stage Boot Loader (FSBL) functionality
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 03/04/11 Initial release
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* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
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* xparameters.h file
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* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
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* Added the debug levels
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* 4.00a sgd 02/28/13 Removed DDR initialization check
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* Removed DDR ECC initialization code
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* Modified hand off address check to 1MB
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* Added RSA authentication support
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* Removed LPBK_DLY_ADJ register setting code as we use
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* divisor 8
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* Removed check for Fabric is already initialized
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*
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* CR's fixed and description
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* 689026: FSBL doesn't hold PL resets active during
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* bit download
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* Resolution: PL resets are released just before
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* handoff
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*
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* 689077: FSBL hangs at Handoff clearing the
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* TX UART buffer
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* Resolution: STDOUT_BASEADDRESS macro value changes
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* based UART select, hence used STDOUT_BASEADDRESS
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* as UART base address
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*
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* 695578: FSBL failed to load standalone application
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* in secure bootmode
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* Resolution: Application will be placed at load address
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* instead of DDR temporary address
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*
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* 699475: FSBL functionality is broken and its
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* not able to boot in QSPI/NAND bootmode
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* Resolution: New flags are added DevCfg driver
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* for handling loopback
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* XDCFG_CONCURRENT_NONSEC_READ_WRITE
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* XDCFG_CONCURRENT_SECURE_READ_WRITE
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*
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* 683145: Define stack area for FIQ, UNDEF modes
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* in linker file
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* Resolution: FSBL linker modified to create stack area
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* for FIQ, UNDEF
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*
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* 705664: FSBL fails to decrypt the bitstream when
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* the image is AES encrypted using non-zero key value
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* Resolution: Fabric cleaning will not be done
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* for AES-E-Fuse encryption
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*
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* Watchdog disabled for AES E-Fuse encryption
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*
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* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
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* Added QSPI Flash Size > 128Mbit support
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* QSPI Dual Stack support
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* Added Md5 checksum support
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*
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* CR's fixed and description
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* 692045 FSBL: Linker script of FSBL has PHDR workaround,
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* this needs to be fixed
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* Resolution: Removed PHDR from Linker file
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*
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* 704287 FSBL: fsbl.h file has a few error codes that
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* are not used by FSBL, that needs to be removed
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* Resolution: Removed unused error codes
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*
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* 704379 FSBL: Check if DDR is in proper state before
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* handoff
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* Resolution: Added DDR initialization check
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*
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* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
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* the debug level is FSBL_DEBUG only.
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*
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* 710128 FSBL: Linux boot failing without load attribute
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* set for Linux partitions in BIF
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* Resolution: FSBL will load partitions with valid load
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* address and stop loading if any invalid load address
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*
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* 708728 Issues seen while making HP interconnect
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* 32 bit wide
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* Resolution: ps7_post_config function generated by PCW
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* will be called after Bit stream download
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* Added MMC support
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* 6.00a kc 07/31/2013 CR's fixed and description
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* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
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* for authenticating the Partition images
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* Resolution: FSBL now uses the PPK left by Boot ROM in
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* OCM for authencating the SPK
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*
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* 724165 Partition Header used by FSBL is not
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* authenticated
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* Resolution: FSBL now authenticates the partition header
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*
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* 691150 ps7_init does not check for peripheral
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* initialization failures or timeout on polls
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* Resolution: Return value of ps7_init() is now checked
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* by FSBL and prints the error string
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*
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* 708316 PS7_init.tcl file should have Error mechanism
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* for all mask_poll
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* Resolution: Return value of ps7_init() is now checked
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* by FSBL and prints the error string
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*
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* 732062 FSBL fails to build if UART not available
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* Resolution: Added define to call xil_printf only
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* if uart is defined
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*
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* 722979 Provide customer-friendly changelogs in FSBL
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* Resolution: Added CR description for all the files
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*
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* 732865 Backward compatibility for ps7_init function
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* Resolution: Added a new define for ps7_init success
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* and value is defined based on ps7_init define
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*
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* Fix for CR#739711 - FSBL not able to read Large
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* QSPI (512M) in IO Mode
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* Resolution: Modified the address calculation
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* algorithm in dual parallel mode for QSPI
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*
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* 7.00a kc 10/18/13 Integrated SD/MMC driver
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* 10/23/13 Support for armcc compiler added
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* 741003 FSBL has to check the HMAC error status after
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* decryption
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* Resolution: Added code for checking the error status
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* after PCAP completion
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* 739968 FSBL should do the QSPI config settings for
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* Dual parallel configuration in IO mode
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* Resolution: Added QSPI config settings in qspi.c
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* 724620 FSBL: How to handle PCAP_MODE after bitstream
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* configuration.
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* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
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* after PCAP transfer completion
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* 726178 In the 14.6 FSBL function FabricInit() PROG_B
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* is kept active for 5mS.
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* Resolution: PROG_B is now kept active for 5ms only in case
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* if efuse is the aes key source.
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* 755245 FSBL does not load partition if eMMC has only
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* one partition
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* Resolution: Changed the if condition for MMC
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* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
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* configuration
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* Resolution: Reverted back the changes of 724620. PCAP_MODE
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* and PCAP_PR bits are not changed
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* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
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* Resolution: For checksum enabled partitions, total
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* total partition image length is copied now.
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* 761895 FSBL should authenticate image only if
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* partition owner was not set to u-boot
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* Resolution: Partition owner check added in
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* image_mover.c
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* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
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* Resolution: Function argument is updated from value
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* to pointer to reflect updated value
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* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
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* unless FSBL* and FSBL are identical in length
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* Resolution: PPK is set only once now.
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* 785778 - FSBL takes 8 seconds to
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* authenticate (RSA) a bitstream on zc706
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* Resolution: Data Caches are enabled only for
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* authentication.
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* 791245 - Use of xilrsa in fsbl
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* Resolution: Rsa library is removed from fsbl source
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* and xilrsa is used from BSP
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* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
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* fallback image offset handling using MD5
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* Resolution: Updated the checksum offset to add with
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* image base address
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* 782309 Fallback support for AES
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* encryption with E-Fuse - Enhancement
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* Resolution: Same as 773866
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* 809336 Minor code cleanup
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* Resolution Minor code changes
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* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
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* Resolution: Change of __asm__ to __asm
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* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
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* in IO mode case.Due to which the variable is
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* remaining in unknown state.
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* Resolution: LinearBootDeviceFlag is initialized 0
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* in main.c
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* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
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* two arguments but f_mount is expecting the 3 arguments
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* from build 2015.1_1210_1, causing compilation error.
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* Resolution: Arguments for f_mount in InitSD() are
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* changed as per new signature.
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* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
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* count, devcfg.INT_STS register is written to, which is
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* not correct.
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* Resolution: Corresponding fields in the devcfg.STATUS
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* register are written to, for clearing DMA done count.
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* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
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* read command from LQSPI_CFG register instead of hard
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* coded read command (0x6B).
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* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
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* Fabric Initialization sequence is modified to check
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* the PL power before sequence starts and checking INIT_B
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* reset status twice in case of failure.
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* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
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* In pcap.c, check pl power through MCTRL register
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* for 3.0 and later versions of silicon.
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* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
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* to enable level shifters in jtag boot mode.
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* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
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* 19.0 vns 03/18/22 Fixed CR#1125470, added FsblPrintArray() prototype
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*
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* </pre>
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*
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* </pre>
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*
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* @note
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*
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* Flags in FSBL
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*
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* FSBL_PERF
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*
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* This Flag can be set at compilation time. This flag is set for
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* measuring the performance of FSBL.That is the time taken to execute is
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* measured.when this flag is set.Execution time with reference to
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* global timer is taken here
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*
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* Total Execution time is the time taken for executing FSBL till handoff
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* to any application .
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* If there is a bitstream in the partition header then the
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* execution time includes the copying of the bitstream to DDR
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* (in case of SD/NAND bootmode)
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* and programming the devcfg dma is accounted.
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*
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* FSBL provides two debug levels
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* DEBUG GENERAL - fsbl_printf under this category will appear only when the
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* FSBL_DEBUG flag is set during compilation
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* DEBUG_INFO - fsbl_printf under this category will appear when the
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* FSBL_DEBUG_INFO flag is set during compilation
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* For a more detailed output log can be used.
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* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
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* RSA functions
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* These macros are input to the fsbl_printf function
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*
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* DEBUG LEVELS
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* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
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* that are with the DEBUG_GENERAL argument are shown
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* FSBL_DEBUG_INFO is level 2, when this flag is set during the
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* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
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*
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* DEFAULT LEVEL
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* By default no print messages will appear.
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*
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* NON_PS_INSTANTIATED_BITSTREAM
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*
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* FSBL will not enable the level shifters for a NON PS instantiated
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* Bitstream.This flag can be set during compilation for a NON PS instantiated
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* bitstream
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*
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* ECC_ENABLE
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* This flag will be defined in the ps7_init.h file when ECC is enabled
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* in the DDR configuration (XPS GUI)
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*
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* RSA_SUPPORT
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* This flag is used to enable authentication feature
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* Default this macro disabled, reason to avoid increase in code size
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*
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* MMC_SUPPORT
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* This flag is used to enable MMC support feature
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*
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* JTAG_ENABLE_LEVEL_SHIFTERS
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* FSBL will not enable the level shifters for jtag boot mode. This flag can be
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* set during compilation for jtag boot mode to enable level shifters.
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*
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* FORCE_USE_AES_EXCLUDE
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* Defining this flag will exclude the feature, forcing every partition to be
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* encrypted when EFUSE_SEC_EN bit is set.
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* This flag can be set/unset during compilation.
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* By default this flag is unset/undefined which enables the above feature
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* Note : Changing the default behaviour is not recommended from
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* Security perspective.
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*
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*******************************************************************************/
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#ifndef XIL_FSBL_H
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#define XIL_FSBL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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#include "xparameters.h"
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#include "xpseudo_asm.h"
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#include "xil_printf.h"
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#include "pcap.h"
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#include "fsbl_debug.h"
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#include "ps7_init.h"
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#ifdef FSBL_PERF
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#include "xtime_l.h"
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#include <stdio.h>
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#endif
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/************************** Constant Definitions *****************************/
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/*
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* SDK release version
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*/
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#define SDK_RELEASE_YEAR 2022
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#define SDK_RELEASE_QUARTER 2
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#define WORD_LENGTH_SHIFT 2
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/*
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* On a Successful handoff to an application FSBL sets this SUCCESS code
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*/
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#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
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/*
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* Backward compatibility for ps7_init
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*/
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#ifdef NEW_PS7_ERR_CODE
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#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
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#else
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#define FSBL_PS7_INIT_SUCCESS (1)
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#endif
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/*
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* ERROR CODES
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* The following are the Error codes that FSBL uses
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* If the Debug prints are enabled only then the error codes will be
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* seen on the com port.Without the debug prints enabled no error codes will
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* be visible.There are not saved in any register
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* Boot Mode States used for error and status output
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* Error codes are defined below
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*/
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#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
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#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
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#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
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#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
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#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
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#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
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#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
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#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
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#define NO_DDR 0xA008 /**< DDR missing */
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#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
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#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
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#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
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#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
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#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
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#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
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#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
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#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
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#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
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#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
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#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
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/*
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* FSBL Exception error codes
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*/
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#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
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#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
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#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
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#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
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#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
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#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
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/*
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* FSBL hook routine failures
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*/
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#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
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#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
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download hook failed */
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#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
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download hook failed */
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/*
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* Watchdog related Error codes
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*/
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#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
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#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
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/*
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* SLCR Registers
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*/
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#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
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#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
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#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
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#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
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#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
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#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
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#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
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/*
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* Efuse Status Register
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*/
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#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
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#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
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/*
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* PS reset control register define
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*/
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#define PS_RST_MASK 0x1 /**< PS software reset */
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/*
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* SLCR BOOT Mode Register defines
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*/
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#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
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/*
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* Boot Modes
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*/
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#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
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#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
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#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
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#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
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#define SD_MODE 0x00000005 /**< SD Boot Mode */
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#define MMC_MODE 0x00000006 /**< MMC Boot Device */
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#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
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#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
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/*
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* Golden image offset
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*/
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#define GOLDEN_IMAGE_OFFSET 0x8000
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/*
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* Silicon Version
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*/
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#define SILICON_VERSION_1 0
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#define SILICON_VERSION_2 1
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#define SILICON_VERSION_3 2
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#define SILICON_VERSION_3_1 3
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/*
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* DDR start address for storing the data temporarily(1M)
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* Need to finalize correct logic
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*/
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#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
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#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
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#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
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#else
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/*
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* In case of PL DDR, this macros defined based PL DDR address
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*/
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#define DDR_START_ADDR 0x00
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#define DDR_END_ADDR 0x00
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#endif
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#define DDR_TEMP_START_ADDR DDR_START_ADDR
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/*
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* DDR test pattern
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*/
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#define DDR_TEST_PATTERN 0xAA55AA55
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#define DDR_TEST_OFFSET 0x100000
|
||
/*
|
||
*
|
||
*/
|
||
#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
|
||
#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
|
||
#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
|
||
#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
|
||
#define LQSPI_CFG_OFFSET 0xA0
|
||
#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
|
||
|
||
/*
|
||
* These are the SLCR lock and unlock macros
|
||
*/
|
||
#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
|
||
#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
|
||
|
||
#define IMAGE_HEADER_CHECKSUM_COUNT 10
|
||
|
||
/* Boot ROM Image defines */
|
||
#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
|
||
#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
|
||
#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
|
||
#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
|
||
#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
|
||
#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
|
||
#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
|
||
#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
|
||
#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
|
||
#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
|
||
#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
|
||
#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
|
||
|
||
/* Reboot status register defines:
|
||
* 0xF0000000 for FSBL fallback mask to notify Boot Rom
|
||
* 0x60000000 for FSBL to mark that FSBL has not handoff yet
|
||
* 0x00FFFFFF for user application to use across soft reset
|
||
*/
|
||
#define FSBL_FAIL_MASK 0xF0000000
|
||
#define FSBL_IN_MASK 0x60000000
|
||
|
||
/* The address that holds the base address for the image Boot ROM found */
|
||
#define BASEADDR_HOLDER 0xFFFFFFF8
|
||
|
||
/**************************** Type Definitions *******************************/
|
||
|
||
/************************** Function Prototypes ******************************/
|
||
|
||
void OutputStatus(u32 State);
|
||
void FsblFallback(void);
|
||
|
||
int FsblSetNextPartition(int Num);
|
||
void *(memcpy_rom)(void * s1, const void * s2, u32 n);
|
||
char *strcpy_rom(char *Dest, const char *Src);
|
||
|
||
void ClearFSBLIn(void);
|
||
void MarkFSBLIn(void);
|
||
void FsblHandoff(u32 FsblStartAddr);
|
||
u32 GetResetReason(void);
|
||
|
||
#ifdef FSBL_PERF
|
||
void FsblGetGlobalTime (XTime * tCur);
|
||
void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
|
||
#endif
|
||
void GetSiliconVersion(void);
|
||
void FsblHandoffExit(u32 FsblStartAddr);
|
||
void FsblHandoffJtagExit();
|
||
void FsblPrintArray (u8 *Buf, u32 Len, char *Str);
|
||
/************************** Variable Definitions *****************************/
|
||
extern int SkipPartition;
|
||
|
||
/***************** Macros (Inline Functions) Definitions *********************/
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|
||
|
||
#endif /* end of protection macro */
|