HardwareDriver/nuvoton/nuc120/NuClockConfig/MyProject/MyProject.c

/****************************************************************************
 * @file     MyProject.c
 * @version  V1.06
 * @Date     2021/07/31-20:56:23 
 * @brief    NuMicro generated code file
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/

/********************
MCU:NUC120RC1DN(LQFP64)
Base Clocks:
HIRC:22.1184MHz
HCLK:22.1184MHz
PCLK:22.1184MHz
Enabled-Module Frequencies:
EBI=Bus Clock(HCLK):22.1184MHz
I2S=Bus Clock(PCLK):22.1184MHz/Engine Clock:22.1184MHz
ISP=Bus Clock(HCLK):22.1184MHz/Engine Clock:22.1184MHz
SYSTICK=Bus Clock(HCLK):22.1184MHz/Engine Clock:11.0592MHz
********************/

#include "NUC100Series.h"

void MyProject_init_ebi(void)
{
    CLK_EnableModuleClock(EBI_MODULE);

    return;
}

void MyProject_deinit_ebi(void)
{
    CLK_DisableModuleClock(EBI_MODULE);

    return;
}

void MyProject_init_i2s(void)
{
    CLK_EnableModuleClock(I2S_MODULE);
    CLK_SetModuleClock(I2S_MODULE, CLK_CLKSEL2_I2S_S_HCLK, MODULE_NoMsk);

    return;
}

void MyProject_deinit_i2s(void)
{
    CLK_DisableModuleClock(I2S_MODULE);

    return;
}

void MyProject_init_isp(void)
{
    CLK_EnableModuleClock(ISP_MODULE);

    return;
}

void MyProject_deinit_isp(void)
{
    CLK_DisableModuleClock(ISP_MODULE);

    return;
}

void MyProject_init_systick(void)
{
    CLK_EnableSysTick(CLK_CLKSEL0_STCLK_S_HIRC_DIV2, 0);

    return;
}

void MyProject_deinit_systick(void)
{
    CLK_DisableSysTick();

    return;
}

void MyProject_init_base(void)
{
    /* If the macros do not exist in your project, please refer to the related clk.h in Header folder of the tool package */
    /* Enable clock source */
    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);

    /* Waiting for clock source ready */
    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);

    /* Set HCLK clock */
    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));

    return;
}

void MyProject_init(void)
{
    /*---------------------------------------------------------------------------------------------------------*/
    /* Init System Clock                                                                                       */
    /*---------------------------------------------------------------------------------------------------------*/
    //CLK->PWRCON   = (CLK->PWRCON   & ~(0x0000000FUL)) | 0x00000014UL;
    //CLK->PLLCON   = (CLK->PLLCON   & ~(0x000FFFFFUL)) | 0x0005C22EUL;
    //CLK->CLKDIV   = (CLK->CLKDIV   & ~(0x00FF0FFFUL)) | 0x00000000UL;
    //CLK->CLKDIV1  = (CLK->CLKDIV1  & ~(0x00FFFFFFUL)) | 0x00000000UL;
    //CLK->CLKSEL0  = (CLK->CLKSEL0  & ~(0x0000003FUL)) | 0x0000003FUL;
    //CLK->CLKSEL1  = (CLK->CLKSEL1  & ~(0xF37777FFUL)) | 0xFFFFFFFFUL;
    //CLK->CLKSEL2  = (CLK->CLKSEL2  & ~(0x00030FFFUL)) | 0x000200FEUL;
    //CLK->CLKSEL3  = (CLK->CLKSEL3  & ~(0x0000003FUL)) | 0x0000003FUL;
    //CLK->AHBCLK   = (CLK->AHBCLK   & ~(0x0000000EUL)) | 0x0000000DUL;
    //CLK->APBCLK   = (CLK->APBCLK   & ~(0xF8F7F37FUL)) | 0x20000000UL;
    //CLK->APBCLK1  = (CLK->APBCLK1  & ~(0x00000007UL)) | 0x00000000UL;
    //CLK->FRQDIV   = (CLK->FRQDIV   & ~(0x0000001FUL)) | 0x00000000UL;
    //SysTick->CTRL = (SysTick->CTRL & ~(0x00000005UL)) | 0x00000001UL;

    /* Unlock protected registers */
    SYS_UnlockReg();

    /* Enable base clock */
    MyProject_init_base();

    /* Enable module clock and set clock source */
    MyProject_init_ebi();
    MyProject_init_i2s();
    MyProject_init_isp();
    MyProject_init_systick();

    /* Update System Core Clock */
    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
    SystemCoreClockUpdate();

    /* Lock protected registers */
    SYS_LockReg();

    return;
}

/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/