diff --git a/cmos/gc0307/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf b/cmos/gc0307/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/cmos/gc0307/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/cmos/gc0307/stm32/EventRecorderStub.scvd b/cmos/gc0307/stm32/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/cmos/gc0307/stm32/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/cmos/gc0307/stm32/JLinkLog.txt b/cmos/gc0307/stm32/JLinkLog.txt new file mode 100644 index 0000000..17d2ced --- /dev/null +++ b/cmos/gc0307/stm32/JLinkLog.txt @@ -0,0 +1,1048 @@ +T2244 7827:153 SEGGER J-Link V4.90 Log File (0001ms, 47849ms total) +T2244 7827:153 DLL Compiled: Jul 28 2014 10:35:20 (0001ms, 47849ms total) +T2244 7827:153 Logging started @ 2019-12-04 23:46 (0001ms, 47849ms total) +T2244 7827:154 JLINK_SetWarnOutHandler(...) (0000ms, 47849ms total) +T2244 7827:154 JLINK_OpenEx(...) +Firmware: J-Link ARM V8 compiled Jan 31 2018 18:34:52 +Hardware: V8.00 +S/N: 20080643 +Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull returns O.K. (0264ms, 48113ms total) +T2244 7827:418 JLINK_GetEmuCaps() returns 0xB9FF7BBF (0000ms, 48113ms total) +T2244 7827:419 JLINK_TIF_GetAvailable(...) (0000ms, 48113ms total) +T2244 7827:419 JLINK_SetErrorOutHandler(...) (0000ms, 48113ms total) +T2244 7827:420 JLINK_ExecCommand("ProjectFile = "D:\project\HardwareDriver\cmos\gc0307\stm32\JLinkSettings.ini"", ...) returns 0x00 (0000ms, 48113ms total) +T2244 7827:420 JLINK_ExecCommand("Device = STM32F103RB", ...)Device "STM32F103RB" selected (128 KB flash, 20 KB RAM). returns 0x00 (0001ms, 48114ms total) +T2244 7827:421 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 48114ms total) +T2244 7827:421 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 48114ms total) +T2244 7827:421 JLINK_GetDLLVersion() returns 49000 (0000ms, 48114ms total) +T2244 7827:421 JLINK_GetFirmwareString(...) (0000ms, 48114ms total) +T2244 7827:422 JLINK_GetDLLVersion() returns 49000 (0000ms, 48114ms total) +T2244 7827:422 JLINK_GetCompileDateTime() (0000ms, 48114ms total) +T2244 7827:422 JLINK_GetFirmwareString(...) (0000ms, 48114ms total) +T2244 7827:422 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 48114ms total) +T2244 7827:423 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0002ms, 48116ms total) +T2244 7827:425 JLINK_SetSpeed(5000) (0000ms, 48116ms total) +T2244 7827:425 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> +Found Cortex-M3 r1p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE00FF010)TPIU fitted. -- CPU_ReadMem(4 bytes @ 0xE00FF014) -- CPU_ReadMem(4 bytes @ 0xE00FF018) ScanLen=9 NumDevices=2 aId[0]=0x3BA00477 aIrRead[0]=0 aScanLen[0]=0 + aScanRead[0]=0 (0029ms, 48145ms total) +T2244 7827:454 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x3BA00477 (0000ms, 48145ms total) +T2244 7827:454 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0001ms, 48146ms total) +T2244 7827:455 JLINK_JTAG_GetDeviceID(DeviceIndex = 1) returns 0x16410041 (0000ms, 48146ms total) +T2244 7827:455 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1) returns 0x00 (0000ms, 48146ms total) +T2244 7827:455 JLINK_GetDLLVersion() returns 49000 (0000ms, 48146ms total) +T2244 7827:455 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 48146ms total) +T2244 7827:456 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 48146ms total) +T2244 7827:456 JLINK_GetDebugInfo(0x101) returns 0xFFFFFFFF (0000ms, 48146ms total) +T2244 7827:456 JLINK_ReadMemEx(0xE0041FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 returns 0x10 (0001ms, 48147ms total) +T2244 7827:457 JLINK_GetDebugInfo(0x102) returns 0xFFFFFFFF (0000ms, 48147ms total) +T2244 7827:457 JLINK_GetDebugInfo(0x103) returns 0xFFFFFFFF (0000ms, 48147ms total) +T2244 7827:457 JLINK_ReadMemEx(0xE0040FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x10 (0001ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x104) returns 0xFFFFFFFF (0000ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x105) returns 0xFFFFFFFF (0000ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x106) returns 0xFFFFFFFF (0000ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x107) returns 0xFFFFFFFF (0000ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x10C) returns 0xFFFFFFFF (0000ms, 48148ms total) +T2244 7827:458 JLINK_GetDebugInfo(0x01) returns 0xFFFFFFFF (0001ms, 48149ms total) +T2244 7827:459 JLINK_GetDeviceFamily() returns 3 (0000ms, 48149ms total) +T2244 7827:459 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41 returns 0x01 (0000ms, 48149ms total) +T2244 7827:459 JLINK_GetDebugInfo(0x10F) returns 0xFFFFFFFF (0001ms, 48150ms total) +T2244 7827:460 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48150ms total) +T2244 7827:460 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> + >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0027ms, 48177ms total) +T2244 7827:487 JLINK_ReadReg(R15 (PC)) returns 0x08000188 (0000ms, 48177ms total) +T2244 7827:487 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 48177ms total) +T2244 7827:487 JLINK_Halt() returns 0x00 (0000ms, 48177ms total) +T2244 7827:487 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0000ms, 48177ms total) +T2244 7827:487 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0001ms, 48178ms total) +T2244 7827:488 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0000ms, 48178ms total) +T2244 7827:488 JLINK_GetHWStatus(...) returns 0x00 (0001ms, 48179ms total) +T2244 7827:489 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 48179ms total) +T2244 7827:489 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 48179ms total) +T2244 7827:489 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 48179ms total) +T2244 7827:489 JLINK_GetSpeed() returns 0x12C0 (0000ms, 48179ms total) +T2244 7827:489 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0001ms, 48180ms total) +T2244 7827:490 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0000ms, 48180ms total) +T2244 7827:490 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., AccessWidth = 33554436) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 48181ms total) +T2244 7827:491 JLINK_ReadReg(R15 (PC)) returns 0x08000188 (0000ms, 48181ms total) +T2244 7827:491 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 48181ms total) +T2244 7827:497 JLINK_ReadMemEx(0xE0001004, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x04 (0000ms, 48181ms total) +T2244 7827:592 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48181ms total) +T2244 7827:592 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) + -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 48209ms total) +T2244 7827:620 JLINK_ReadReg(R15 (PC)) returns 0x08000188 (0000ms, 48209ms total) +T2244 7827:620 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 48209ms total) +T2244 7827:620 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000180) -- Updating C cache (128 bytes @ 0x08000180) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0002ms, 48211ms total) +T2244 7827:622 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48 returns 0x02 (0000ms, 48211ms total) +T2244 7827:622 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0001ms, 48212ms total) +T2244 7827:623 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0000ms, 48212ms total) +T2244 7827:623 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0000ms, 48212ms total) +T2244 7827:623 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48 returns 0x02 (0000ms, 48212ms total) +T2244 7827:786 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48212ms total) +T2244 7827:787 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00 returns 0x04 (0001ms, 48213ms total) +T2244 7830:651 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0001ms, 48214ms total) +T2244 7830:652 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48 returns 0x02 (0000ms, 48214ms total) +T2244 7830:652 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0000ms, 48214ms total) +T2244 7830:652 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0000ms, 48214ms total) +T2244 7830:652 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0000ms, 48214ms total) +T2244 7830:652 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48 returns 0x02 (0000ms, 48214ms total) +T2244 7831:139 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R1) returns 0x00000003 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R2) returns 0x40022000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R13 (SP)) returns 0x20000678 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R14) returns 0xFFFFFFFF (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(R15 (PC)) returns 0x08000188 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(MSP) returns 0x20000678 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48215ms total) +T2244 7831:140 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48215ms total) +T3520 7831:250 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48 returns 0x02 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x00000001 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 48215ms total) +T3520 7831:250 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 48215ms total) +T3520 7831:250 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0004ms, 48219ms total) +T3520 7831:355 JLINK_IsHalted() returns TRUE (0003ms, 48222ms total) +T3520 7831:358 JLINK_Halt() returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_IsHalted() returns TRUE (0000ms, 48219ms total) +T3520 7831:358 JLINK_IsHalted() returns TRUE (0000ms, 48219ms total) +T3520 7831:358 JLINK_IsHalted() returns TRUE (0000ms, 48219ms total) +T3520 7831:358 JLINK_ReadReg(R15 (PC)) returns 0x080008FC (0000ms, 48219ms total) +T3520 7831:358 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 48219ms total) +T3520 7831:358 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0001ms, 48220ms total) +T3520 7831:359 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0000ms, 48220ms total) +T3520 7831:359 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0000ms, 48220ms total) +T3520 7831:359 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0001ms, 48221ms total) +T3520 7831:360 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0000ms, 48221ms total) +T3520 7831:360 JLINK_ReadReg(R0) returns 0x20000078 (0001ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R1) returns 0x20000278 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R2) returns 0x20000278 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R3) returns 0x20000278 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R12) returns 0x20000054 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R13 (SP)) returns 0x20000678 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R14) returns 0x08000177 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(R15 (PC)) returns 0x080008FC (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(MSP) returns 0x20000678 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48222ms total) +T3520 7831:361 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48222ms total) +T2244 7831:368 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 13 14 00 00 returns 0x01 (0000ms, 48222ms total) +T2244 7831:369 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48223ms total) +T2244 7831:370 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00 returns 0x04 (0000ms, 48223ms total) +T2244 7831:376 JLINK_ReadMemEx(0x080008FC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x080008C0) -- Updating C cache (128 bytes @ 0x080008C0) -- Read from C cache (60 bytes @ 0x080008FC) - Data: FF F7 E6 FE FF F7 FC FD FF F7 2E FD 00 20 FF F7 ... returns 0x3C (0001ms, 48224ms total) +T2244 7831:377 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7 returns 0x02 (0000ms, 48224ms total) +T2244 7831:377 JLINK_ReadMemEx(0x080008FE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FE) - Data: E6 FE returns 0x02 (0001ms, 48225ms total) +T3520 7835:337 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7 returns 0x02 (0001ms, 48226ms total) +T3520 7835:338 JLINK_Step() -- Read from C cache (2 bytes @ 0x080008FC) -- Read from C cache (2 bytes @ 0x080008FE) -- Simulated returns 0x00 (0001ms, 48227ms total) +T3520 7835:339 JLINK_ReadReg(R15 (PC)) returns 0x080006CC (0000ms, 48227ms total) +T3520 7835:339 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 48227ms total) +T3520 7835:339 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 48227ms total) +T3520 7835:339 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48228ms total) +T3520 7835:442 JLINK_IsHalted() returns TRUE (0003ms, 48231ms total) +T3520 7835:445 JLINK_Halt() returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_IsHalted() returns TRUE (0000ms, 48228ms total) +T3520 7835:445 JLINK_IsHalted() returns TRUE (0000ms, 48228ms total) +T3520 7835:445 JLINK_IsHalted() returns TRUE (0000ms, 48228ms total) +T3520 7835:445 JLINK_ReadReg(R15 (PC)) returns 0x08000908 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 48228ms total) +T3520 7835:445 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0001ms, 48229ms total) +T3520 7835:446 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0000ms, 48229ms total) +T3520 7835:446 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0002ms, 48231ms total) +T3520 7835:448 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R0) returns 0x00002710 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R1) returns 0xBFFF0000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R2) returns 0x04000021 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R3) returns 0x1C034000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R13 (SP)) returns 0x20000678 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R14) returns 0x080003AD (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(R15 (PC)) returns 0x08000908 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(MSP) returns 0x20000678 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48231ms total) +T3520 7835:448 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48231ms total) +T2244 7835:448 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 7A 1F 00 00 returns 0x01 (0001ms, 48232ms total) +T2244 7835:449 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48233ms total) +T2244 7835:450 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0002ms, 48235ms total) +T2244 7835:482 JLINK_ReadMemEx(0x08000908, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000900) -- Updating C cache (128 bytes @ 0x08000900) -- Read from C cache (60 bytes @ 0x08000908) - Data: 00 20 FF F7 53 FD 00 BF FE E7 00 00 34 09 00 08 ... returns 0x3C (0002ms, 48237ms total) +T2244 7835:484 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20 returns 0x02 (0000ms, 48237ms total) +T2244 7835:484 JLINK_ReadMemEx(0x0800090A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800090A) - Data: FF F7 returns 0x02 (0000ms, 48237ms total) +T3520 7835:959 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20 returns 0x02 (0000ms, 48237ms total) +T3520 7835:959 JLINK_Step() -- Read from C cache (2 bytes @ 0x08000908) -- Simulated returns 0x00 (0001ms, 48238ms total) +T3520 7835:960 JLINK_ReadReg(R15 (PC)) returns 0x0800090A (0000ms, 48238ms total) +T3520 7835:960 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 48238ms total) +T3520 7835:960 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 48238ms total) +T3520 7835:960 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48239ms total) +T3520 7836:062 JLINK_IsHalted() returns TRUE (0003ms, 48242ms total) +T3520 7836:065 JLINK_Halt() returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_IsHalted() returns TRUE (0000ms, 48239ms total) +T3520 7836:065 JLINK_IsHalted() returns TRUE (0000ms, 48239ms total) +T3520 7836:065 JLINK_IsHalted() returns TRUE (0000ms, 48239ms total) +T3520 7836:065 JLINK_ReadReg(R15 (PC)) returns 0x080003D6 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 48239ms total) +T3520 7836:065 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0001ms, 48240ms total) +T3520 7836:066 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0001ms, 48241ms total) +T3520 7836:067 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0000ms, 48241ms total) +T3520 7836:067 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0001ms, 48242ms total) +T3520 7836:068 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R1) returns 0x00030001 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R2) returns 0x40005400 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R3) returns 0x00030000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R13 (SP)) returns 0x20000670 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R14) returns 0x080003D3 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(R15 (PC)) returns 0x080003D6 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(MSP) returns 0x20000670 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48243ms total) +T3520 7836:069 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48243ms total) +T2244 7836:069 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0001ms, 48244ms total) +T2244 7836:070 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00 returns 0x04 (0000ms, 48244ms total) +T2244 7836:070 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0000ms, 48244ms total) +T2244 7836:078 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 2E 00 00 returns 0x01 (0000ms, 48244ms total) +T2244 7836:079 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48245ms total) +T2244 7836:080 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48245ms total) +T2244 7836:099 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22 returns 0x02 (0001ms, 48246ms total) +T2244 7836:100 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0002ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ... returns 0x3C (0000ms, 48248ms total) +T2244 7836:102 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0 returns 0x02 (0000ms, 48248ms total) +T3520 7836:908 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22 returns 0x02 (0002ms, 48250ms total) +T3520 7836:910 JLINK_Step() -- Read from C cache (2 bytes @ 0x080003D6) -- Simulated returns 0x00 (0000ms, 48250ms total) +T3520 7836:910 JLINK_ReadReg(R15 (PC)) returns 0x080003D8 (0000ms, 48250ms total) +T3520 7836:910 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 48250ms total) +T3520 7836:910 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 48250ms total) +T3520 7836:910 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0002ms, 48252ms total) +T3520 7837:014 JLINK_IsHalted() returns FALSE (0000ms, 48252ms total) +T3520 7837:114 JLINK_IsHalted() returns FALSE (0000ms, 48252ms total) +T3520 7837:215 JLINK_IsHalted() returns FALSE (0000ms, 48252ms total) +T3520 7837:316 JLINK_IsHalted() returns FALSE (0000ms, 48252ms total) +T3520 7837:417 JLINK_IsHalted() returns FALSE (0000ms, 48252ms total) +T3520 7837:518 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F6 9E 99 02 returns 0x01 (0000ms, 48252ms total) +T2244 7837:519 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48252ms total) +T2244 7837:519 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48253ms total) +T3520 7837:540 JLINK_IsHalted() returns FALSE (0000ms, 48253ms total) +T3520 7837:641 JLINK_IsHalted() returns FALSE (0000ms, 48253ms total) +T3520 7837:742 JLINK_IsHalted() returns FALSE (0000ms, 48253ms total) +T3520 7837:843 JLINK_IsHalted() returns FALSE (0000ms, 48253ms total) +T3520 7837:945 JLINK_IsHalted() returns FALSE (0001ms, 48254ms total) +T3520 7838:046 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 87 9A DD 04 returns 0x01 (0000ms, 48253ms total) +T2244 7838:047 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48254ms total) +T2244 7838:048 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48254ms total) +T3520 7838:052 JLINK_IsHalted() returns FALSE (0000ms, 48254ms total) +T3520 7838:153 JLINK_IsHalted() returns FALSE (0000ms, 48254ms total) +T3520 7838:254 JLINK_IsHalted() returns FALSE (0000ms, 48254ms total) +T3520 7838:355 JLINK_IsHalted() returns FALSE (0000ms, 48254ms total) +T3520 7838:456 JLINK_IsHalted() returns FALSE (0000ms, 48254ms total) +T3520 7838:557 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 51 8B 0F 07 returns 0x01 (0000ms, 48254ms total) +T2244 7838:560 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0002ms, 48256ms total) +T2244 7838:562 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48257ms total) +T3520 7838:568 JLINK_IsHalted() returns FALSE (0000ms, 48257ms total) +T3520 7838:669 JLINK_IsHalted() returns FALSE (0000ms, 48257ms total) +T3520 7838:769 JLINK_IsHalted() returns FALSE (0000ms, 48257ms total) +T3520 7838:870 JLINK_IsHalted() returns FALSE (0000ms, 48257ms total) +T3520 7838:971 JLINK_IsHalted() returns FALSE (0000ms, 48257ms total) +T3520 7839:072 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 75 A6 45 09 returns 0x01 (0000ms, 48257ms total) +T2244 7839:073 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48258ms total) +T2244 7839:074 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48258ms total) +T3520 7839:081 JLINK_IsHalted() returns FALSE (0001ms, 48259ms total) +T3520 7839:183 JLINK_IsHalted() returns FALSE (0000ms, 48258ms total) +T3520 7839:284 JLINK_IsHalted() returns FALSE (0001ms, 48259ms total) +T3520 7839:385 JLINK_IsHalted() returns FALSE (0001ms, 48259ms total) +T3520 7839:486 JLINK_IsHalted() returns FALSE (0001ms, 48259ms total) +T3520 7839:588 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: CF 04 7C 0B returns 0x01 (0000ms, 48258ms total) +T2244 7839:595 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48259ms total) +T2244 7839:596 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48260ms total) +T3520 7839:602 JLINK_IsHalted() returns FALSE (0001ms, 48261ms total) +T3520 7839:704 JLINK_IsHalted() returns FALSE (0000ms, 48260ms total) +T3520 7839:805 JLINK_IsHalted() returns FALSE (0000ms, 48260ms total) +T3520 7839:906 JLINK_IsHalted() returns FALSE (0000ms, 48260ms total) +T3520 7840:008 JLINK_IsHalted() returns FALSE (0001ms, 48261ms total) +T3520 7840:110 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: BC AB B9 0D returns 0x01 (0000ms, 48260ms total) +T2244 7840:112 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48261ms total) +T2244 7840:113 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48262ms total) +T3520 7840:120 JLINK_IsHalted() returns FALSE (0001ms, 48263ms total) +T3520 7840:221 JLINK_IsHalted() returns FALSE (0000ms, 48262ms total) +T3520 7840:322 JLINK_IsHalted() returns FALSE (0000ms, 48262ms total) +T3520 7840:423 JLINK_IsHalted() returns FALSE (0000ms, 48262ms total) +T3520 7840:525 JLINK_IsHalted() returns FALSE (0000ms, 48262ms total) +T3520 7840:626 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: E3 90 F0 0F returns 0x01 (0000ms, 48262ms total) +T2244 7840:629 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48263ms total) +T2244 7840:630 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48264ms total) +T3520 7840:638 JLINK_IsHalted() returns FALSE (0000ms, 48264ms total) +T3520 7840:739 JLINK_IsHalted() returns FALSE (0000ms, 48264ms total) +T3520 7840:840 JLINK_IsHalted() returns FALSE (0000ms, 48264ms total) +T3520 7840:941 JLINK_IsHalted() returns FALSE (0000ms, 48264ms total) +T3520 7841:042 JLINK_IsHalted() returns FALSE (0000ms, 48264ms total) +T3520 7841:144 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F0 4C 29 12 returns 0x01 (0000ms, 48264ms total) +T2244 7841:144 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48265ms total) +T2244 7841:145 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48265ms total) +T3520 7841:152 JLINK_IsHalted() returns FALSE (0001ms, 48266ms total) +T3520 7841:255 JLINK_IsHalted() returns FALSE (0000ms, 48265ms total) +T3520 7841:356 JLINK_IsHalted() returns FALSE (0000ms, 48265ms total) +T3520 7841:457 JLINK_IsHalted() returns FALSE (0000ms, 48265ms total) +T3520 7841:558 JLINK_IsHalted() returns FALSE (0000ms, 48265ms total) +T3520 7841:659 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 3F DC 5F 14 returns 0x01 (0000ms, 48265ms total) +T2244 7841:659 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48266ms total) +T2244 7841:660 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48267ms total) +T3520 7841:665 JLINK_IsHalted() returns FALSE (0001ms, 48268ms total) +T3520 7841:767 JLINK_IsHalted() returns FALSE (0000ms, 48267ms total) +T3520 7841:868 JLINK_IsHalted() returns FALSE (0000ms, 48267ms total) +T3520 7841:969 JLINK_IsHalted() returns FALSE (0001ms, 48268ms total) +T3520 7842:071 JLINK_IsHalted() returns FALSE (0001ms, 48268ms total) +T3520 7842:172 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 2C 2D 93 16 returns 0x01 (0000ms, 48267ms total) +T2244 7842:176 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0002ms, 48269ms total) +T2244 7842:178 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48269ms total) +T3520 7842:188 JLINK_IsHalted() returns FALSE (0001ms, 48270ms total) +T3520 7842:290 JLINK_IsHalted() returns FALSE (0000ms, 48269ms total) +T3520 7842:391 JLINK_IsHalted() returns FALSE (0000ms, 48269ms total) +T3520 7842:491 JLINK_IsHalted() returns FALSE (0000ms, 48269ms total) +T3520 7842:592 JLINK_IsHalted() returns FALSE (0000ms, 48269ms total) +T3520 7842:693 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 23 80 CF 18 returns 0x01 (0000ms, 48269ms total) +T2244 7842:693 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48270ms total) +T2244 7842:694 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48271ms total) +T3520 7842:698 JLINK_IsHalted() returns FALSE (0001ms, 48272ms total) +T3520 7842:800 JLINK_IsHalted() returns FALSE (0000ms, 48271ms total) +T3520 7842:900 JLINK_IsHalted() returns FALSE (0000ms, 48271ms total) +T3520 7843:001 JLINK_IsHalted() returns FALSE (0000ms, 48271ms total) +T3520 7843:102 JLINK_IsHalted() returns FALSE (0001ms, 48272ms total) +T3520 7843:204 JLINK_IsHalted() returns FALSE (0000ms, 48271ms total) +T3520 7843:305 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 1E 9A 6F 1B returns 0x01 (0000ms, 48271ms total) +T2244 7843:305 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48272ms total) +T2244 7843:306 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48272ms total) +T3520 7843:310 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:411 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:513 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:613 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:714 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:816 JLINK_IsHalted() returns FALSE (0000ms, 48272ms total) +T3520 7843:917 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: DD D1 10 1E returns 0x01 (0001ms, 48273ms total) +T2244 7843:920 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48274ms total) +T2244 7843:921 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48275ms total) +T3520 7843:930 JLINK_IsHalted() returns FALSE (0000ms, 48275ms total) +T3520 7844:031 JLINK_Halt() returns 0x00 (0003ms, 48278ms total) +T3520 7844:034 JLINK_IsHalted() returns TRUE (0000ms, 48278ms total) +T3520 7844:034 JLINK_IsHalted() returns TRUE (0000ms, 48278ms total) +T3520 7844:034 JLINK_IsHalted() returns TRUE (0000ms, 48278ms total) +T3520 7844:034 JLINK_ReadReg(R15 (PC)) returns 0x0800048A (0000ms, 48278ms total) +T3520 7844:034 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 48278ms total) +T3520 7844:034 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 01 00 00 00 returns 0x01 (0001ms, 48279ms total) +T3520 7844:035 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0001ms, 48280ms total) +T3520 7844:036 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0000ms, 48280ms total) +T3520 7844:036 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0001ms, 48281ms total) +T3520 7844:037 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R0) returns 0x40005400 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R1) returns 0x00070082 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R2) returns 0x40005400 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R3) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R13 (SP)) returns 0x20000660 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R14) returns 0x080003EB (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(R15 (PC)) returns 0x0800048A (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(MSP) returns 0x20000660 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48282ms total) +T3520 7844:038 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48282ms total) +T2244 7844:039 JLINK_ReadMemEx(0x2000066C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x2000066C) - Data: EB 03 00 08 returns 0x04 (0000ms, 48282ms total) +T2244 7844:039 JLINK_ReadMemEx(0x20000660, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000660, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000660, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000660) - Data: 00 00 00 00 returns 0x04 (0001ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x20000664, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000664, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000664, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000664) - Data: 14 00 00 20 returns 0x04 (0000ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x20000668, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000668, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000668, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000668) - Data: 00 00 00 00 returns 0x04 (0000ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x2000066C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x2000066C) - Data: EB 03 00 08 returns 0x04 (0000ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0000ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00 returns 0x04 (0000ms, 48283ms total) +T2244 7844:040 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0000ms, 48283ms total) +T2244 7844:054 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: AA 5D 8D 1E returns 0x01 (0000ms, 48283ms total) +T2244 7844:055 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48284ms total) +T2244 7844:056 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48284ms total) +T2244 7844:593 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48284ms total) +T2244 7844:593 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) + -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R15 (PC)) returns 0x08000188 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R0) returns 0x40005400 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R1) returns 0x00070082 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R2) returns 0x40005400 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R3) returns 0x00000000 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48312ms total) +T2244 7844:621 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 04 65 8D 1E returns 0x01 (0001ms, 48313ms total) +T2244 7844:624 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000180) -- Updating C cache (128 bytes @ 0x08000180) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0001ms, 48314ms total) +T2244 7844:625 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48 returns 0x02 (0001ms, 48315ms total) +T2244 7844:626 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0000ms, 48315ms total) +T2244 7844:626 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47 returns 0x02 (0000ms, 48315ms total) +T2244 7844:626 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... returns 0x3C (0000ms, 48315ms total) +T2244 7844:626 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48 returns 0x02 (0000ms, 48315ms total) +T3520 7845:320 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48 returns 0x02 (0001ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 48316ms total) +T3520 7845:321 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 48316ms total) +T3520 7845:321 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0003ms, 48319ms total) +T3520 7845:425 JLINK_IsHalted() returns TRUE (0003ms, 48322ms total) +T3520 7845:428 JLINK_Halt() returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_IsHalted() returns TRUE (0000ms, 48319ms total) +T3520 7845:428 JLINK_IsHalted() returns TRUE (0000ms, 48319ms total) +T3520 7845:428 JLINK_IsHalted() returns TRUE (0000ms, 48319ms total) +T3520 7845:428 JLINK_ReadReg(R15 (PC)) returns 0x080008FC (0000ms, 48319ms total) +T3520 7845:428 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 48319ms total) +T3520 7845:428 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0001ms, 48320ms total) +T3520 7845:429 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0001ms, 48321ms total) +T3520 7845:430 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0000ms, 48321ms total) +T3520 7845:430 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0001ms, 48322ms total) +T3520 7845:431 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R0) returns 0x20000078 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R1) returns 0x20000278 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R2) returns 0x20000278 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R3) returns 0x20000278 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R12) returns 0x20000054 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R13 (SP)) returns 0x20000678 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R14) returns 0x08000177 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(R15 (PC)) returns 0x080008FC (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(MSP) returns 0x20000678 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48323ms total) +T3520 7845:432 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48323ms total) +T2244 7845:441 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 29 14 00 00 returns 0x01 (0001ms, 48324ms total) +T2244 7845:442 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48325ms total) +T2244 7845:443 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00 returns 0x04 (0001ms, 48326ms total) +T2244 7845:488 JLINK_ReadMemEx(0x080008FC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x080008C0) -- Updating C cache (128 bytes @ 0x080008C0) -- Read from C cache (60 bytes @ 0x080008FC) - Data: FF F7 E6 FE FF F7 FC FD FF F7 2E FD 00 20 FF F7 ... returns 0x3C (0002ms, 48328ms total) +T2244 7845:490 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7 returns 0x02 (0000ms, 48328ms total) +T2244 7845:490 JLINK_ReadMemEx(0x080008FE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FE) - Data: E6 FE returns 0x02 (0000ms, 48328ms total) +T3520 7846:208 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7 returns 0x02 (0001ms, 48329ms total) +T3520 7846:209 JLINK_Step() -- Read from C cache (2 bytes @ 0x080008FC) -- Read from C cache (2 bytes @ 0x080008FE) -- Simulated returns 0x00 (0001ms, 48330ms total) +T3520 7846:210 JLINK_ReadReg(R15 (PC)) returns 0x080006CC (0000ms, 48330ms total) +T3520 7846:210 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x00000021 (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 48330ms total) +T3520 7846:210 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 48330ms total) +T3520 7846:210 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0000ms, 48330ms total) +T3520 7846:312 JLINK_IsHalted() returns TRUE (0003ms, 48333ms total) +T3520 7846:315 JLINK_Halt() returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_IsHalted() returns TRUE (0000ms, 48330ms total) +T3520 7846:315 JLINK_IsHalted() returns TRUE (0000ms, 48330ms total) +T3520 7846:315 JLINK_IsHalted() returns TRUE (0000ms, 48330ms total) +T3520 7846:315 JLINK_ReadReg(R15 (PC)) returns 0x08000908 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 48330ms total) +T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0001ms, 48331ms total) +T3520 7846:316 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0000ms, 48331ms total) +T3520 7846:316 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0001ms, 48332ms total) +T3520 7846:317 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0000ms, 48332ms total) +T3520 7846:317 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0001ms, 48333ms total) +T3520 7846:318 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R0) returns 0x00002710 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R1) returns 0xBFFF0000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R2) returns 0x04000021 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R3) returns 0x1C034000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R13 (SP)) returns 0x20000678 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R14) returns 0x080003AD (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(R15 (PC)) returns 0x08000908 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(MSP) returns 0x20000678 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48334ms total) +T3520 7846:319 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48334ms total) +T2244 7846:319 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 90 1F 00 00 returns 0x01 (0001ms, 48335ms total) +T2244 7846:320 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48336ms total) +T2244 7846:321 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48337ms total) +T2244 7846:353 JLINK_ReadMemEx(0x08000908, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000900) -- Updating C cache (128 bytes @ 0x08000900) -- Read from C cache (60 bytes @ 0x08000908) - Data: 00 20 FF F7 53 FD 00 BF FE E7 00 00 34 09 00 08 ... returns 0x3C (0002ms, 48339ms total) +T2244 7846:355 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20 returns 0x02 (0000ms, 48339ms total) +T2244 7846:355 JLINK_ReadMemEx(0x0800090A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800090A) - Data: FF F7 returns 0x02 (0000ms, 48339ms total) +T3520 7846:976 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20 returns 0x02 (0000ms, 48339ms total) +T3520 7846:976 JLINK_Step() -- Read from C cache (2 bytes @ 0x08000908) -- Simulated returns 0x00 (0001ms, 48340ms total) +T3520 7846:977 JLINK_ReadReg(R15 (PC)) returns 0x0800090A (0000ms, 48340ms total) +T3520 7846:977 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x00000026 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 48340ms total) +T3520 7846:977 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x0000002A (0000ms, 48340ms total) +T3520 7846:977 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0002ms, 48342ms total) +T3520 7847:079 JLINK_IsHalted() returns TRUE (0003ms, 48345ms total) +T3520 7847:082 JLINK_Halt() returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_IsHalted() returns TRUE (0000ms, 48342ms total) +T3520 7847:082 JLINK_IsHalted() returns TRUE (0000ms, 48342ms total) +T3520 7847:082 JLINK_IsHalted() returns TRUE (0000ms, 48342ms total) +T3520 7847:082 JLINK_ReadReg(R15 (PC)) returns 0x080003D6 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 48342ms total) +T3520 7847:082 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0001ms, 48343ms total) +T3520 7847:083 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0001ms, 48344ms total) +T3520 7847:084 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0001ms, 48345ms total) +T3520 7847:085 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0000ms, 48345ms total) +T3520 7847:085 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R1) returns 0x00030001 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R2) returns 0x40005400 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R3) returns 0x00030000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R13 (SP)) returns 0x20000670 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R14) returns 0x080003D3 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(R15 (PC)) returns 0x080003D6 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(MSP) returns 0x20000670 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48346ms total) +T3520 7847:086 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48346ms total) +T2244 7847:087 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0002ms, 48348ms total) +T2244 7847:089 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00 returns 0x04 (0000ms, 48348ms total) +T2244 7847:089 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0000ms, 48348ms total) +T2244 7847:097 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 16 2E 00 00 returns 0x01 (0001ms, 48349ms total) +T2244 7847:098 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48350ms total) +T2244 7847:099 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48351ms total) +T2244 7847:119 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22 returns 0x02 (0002ms, 48353ms total) +T2244 7847:121 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0001ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ... returns 0x3C (0000ms, 48354ms total) +T2244 7847:122 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0 returns 0x02 (0000ms, 48354ms total) +T3520 7852:025 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22 returns 0x02 (0001ms, 48355ms total) +T3520 7852:026 JLINK_Step() -- Read from C cache (2 bytes @ 0x080003D6) -- Simulated returns 0x00 (0000ms, 48355ms total) +T3520 7852:027 JLINK_ReadReg(R15 (PC)) returns 0x080003D8 (0000ms, 48356ms total) +T3520 7852:027 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2) returns 0x0000002C (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2) returns 0x0000002D (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2) returns 0x0000002E (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2) returns 0x0000002F (0000ms, 48356ms total) +T3520 7852:027 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2) returns 0x00000030 (0000ms, 48356ms total) +T3520 7852:027 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48357ms total) +T3520 7852:129 JLINK_IsHalted() returns FALSE (0000ms, 48357ms total) +T3520 7852:231 JLINK_IsHalted() returns FALSE (0000ms, 48357ms total) +T3520 7852:332 JLINK_IsHalted() returns FALSE (0000ms, 48357ms total) +T3520 7852:433 JLINK_IsHalted() returns FALSE (0000ms, 48357ms total) +T3520 7852:534 JLINK_IsHalted() returns FALSE (0000ms, 48357ms total) +T3520 7852:636 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: EF 6B 9B 02 returns 0x01 (0000ms, 48357ms total) +T2244 7852:637 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48357ms total) +T2244 7852:637 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48358ms total) +T3520 7852:655 JLINK_IsHalted() returns FALSE (0000ms, 48358ms total) +T3520 7852:756 JLINK_IsHalted() returns FALSE (0000ms, 48358ms total) +T3520 7852:858 JLINK_IsHalted() returns FALSE (0000ms, 48358ms total) +T3520 7852:959 JLINK_IsHalted() returns FALSE (0000ms, 48358ms total) +T3520 7853:060 JLINK_IsHalted() returns FALSE (0000ms, 48358ms total) +T3520 7853:162 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9E 69 DD 04 returns 0x01 (0000ms, 48358ms total) +T2244 7853:162 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48358ms total) +T2244 7853:162 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48359ms total) +T3520 7853:168 JLINK_IsHalted() returns FALSE (0001ms, 48360ms total) +T3520 7853:269 JLINK_IsHalted() returns FALSE (0000ms, 48359ms total) +T3520 7853:370 JLINK_IsHalted() returns FALSE (0000ms, 48359ms total) +T3520 7853:471 JLINK_IsHalted() returns FALSE (0000ms, 48359ms total) +T3520 7853:571 JLINK_IsHalted() returns FALSE (0000ms, 48359ms total) +T3520 7853:673 JLINK_IsHalted() returns FALSE (0000ms, 48359ms total) +T3520 7853:774 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: C1 08 7E 07 returns 0x01 (0000ms, 48359ms total) +T2244 7853:776 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48360ms total) +T2244 7853:777 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48360ms total) +T3520 7853:786 JLINK_IsHalted() returns FALSE (0000ms, 48360ms total) +T3520 7853:888 JLINK_IsHalted() returns FALSE (0000ms, 48360ms total) +T3520 7853:989 JLINK_IsHalted() returns FALSE (0000ms, 48360ms total) +T3520 7854:090 JLINK_IsHalted() returns FALSE (0000ms, 48360ms total) +T3520 7854:191 JLINK_IsHalted() returns FALSE (0000ms, 48360ms total) +T3520 7854:291 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: DE A0 B6 09 returns 0x01 (0000ms, 48360ms total) +T2244 7854:294 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48361ms total) +T2244 7854:295 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48362ms total) +T3520 7854:301 JLINK_IsHalted() returns FALSE (0001ms, 48363ms total) +T3520 7854:403 JLINK_IsHalted() returns FALSE (0000ms, 48362ms total) +T3520 7854:504 JLINK_IsHalted() returns FALSE (0000ms, 48362ms total) +T3520 7854:605 JLINK_IsHalted() returns FALSE (0000ms, 48362ms total) +T3520 7854:706 JLINK_IsHalted() returns FALSE (0000ms, 48362ms total) +T3520 7854:807 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 35 71 ED 0B returns 0x01 (0000ms, 48362ms total) +T2244 7854:810 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48363ms total) +T2244 7854:811 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48364ms total) +T3520 7854:816 JLINK_IsHalted() returns FALSE (0000ms, 48364ms total) +T3520 7854:917 JLINK_IsHalted() returns FALSE (0000ms, 48364ms total) +T3520 7855:018 JLINK_IsHalted() returns FALSE (0000ms, 48364ms total) +T3520 7855:120 JLINK_IsHalted() returns FALSE (0000ms, 48364ms total) +T3520 7855:221 JLINK_IsHalted() returns FALSE (0000ms, 48364ms total) +T3520 7855:322 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 76 CF 22 0E returns 0x01 (0001ms, 48365ms total) +T2244 7855:323 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48366ms total) +T2244 7855:324 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48366ms total) +T3520 7855:328 JLINK_IsHalted() returns FALSE (0001ms, 48367ms total) +T3520 7855:429 JLINK_IsHalted() returns FALSE (0000ms, 48366ms total) +T3520 7855:530 JLINK_IsHalted() returns FALSE (0000ms, 48366ms total) +T2244 7855:576 JLINK_ReadMemEx(0x080003E0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E0) - Data: 00 BF returns 0x02 (0000ms, 48366ms total) +T2244 7855:576 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E2) - Data: 20 49 returns 0x02 (0001ms, 48367ms total) +T2244 7855:577 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E2) - Data: 20 49 returns 0x02 (0000ms, 48367ms total) +T2244 7855:577 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E4) - Data: 1D 48 returns 0x02 (0001ms, 48368ms total) +T2244 7855:578 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E4) - Data: 1D 48 returns 0x02 (0001ms, 48369ms total) +T2244 7855:579 JLINK_ReadMemEx(0x080003E6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E6) - Data: 00 F0 returns 0x02 (0000ms, 48369ms total) +T3520 7855:631 JLINK_IsHalted() returns FALSE (0000ms, 48369ms total) +T3520 7855:732 JLINK_IsHalted() returns FALSE (0000ms, 48369ms total) +T3520 7855:834 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 3E 36 55 10 returns 0x01 (0000ms, 48369ms total) +T2244 7855:835 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48369ms total) +T2244 7855:835 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48370ms total) +T3520 7855:842 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7855:943 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7856:044 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7856:146 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7856:247 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7856:348 JLINK_IsHalted() returns FALSE (0000ms, 48370ms total) +T3520 7856:449 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 73 B0 F8 12 returns 0x01 (0000ms, 48370ms total) +T2244 7856:449 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48371ms total) +T2244 7856:450 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48372ms total) +T3520 7856:455 JLINK_IsHalted() returns FALSE (0001ms, 48373ms total) +T3520 7856:556 JLINK_IsHalted() returns FALSE (0000ms, 48372ms total) +T3520 7856:657 JLINK_IsHalted() returns FALSE (0000ms, 48372ms total) +T3520 7856:758 JLINK_IsHalted() returns FALSE (0000ms, 48372ms total) +T3520 7856:860 JLINK_IsHalted() returns FALSE (0000ms, 48372ms total) +T3520 7856:962 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 42 64 2C 15 returns 0x01 (0000ms, 48372ms total) +T2244 7856:972 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48373ms total) +T2244 7856:973 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48374ms total) +T3520 7856:980 JLINK_IsHalted() returns FALSE (0000ms, 48374ms total) +T3520 7857:081 JLINK_IsHalted() returns FALSE (0000ms, 48374ms total) +T3520 7857:182 JLINK_IsHalted() returns FALSE (0000ms, 48374ms total) +T3520 7857:283 JLINK_IsHalted() returns FALSE (0000ms, 48374ms total) +T3520 7857:383 JLINK_IsHalted() returns FALSE (0000ms, 48374ms total) +T3520 7857:484 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 16 A1 6A 17 returns 0x01 (0001ms, 48375ms total) +T2244 7857:495 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48376ms total) +T2244 7857:496 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48377ms total) +T3520 7857:502 JLINK_IsHalted() returns FALSE (0000ms, 48377ms total) +T3520 7857:603 JLINK_IsHalted() returns FALSE (0000ms, 48377ms total) +T3520 7857:704 JLINK_IsHalted() returns FALSE (0000ms, 48377ms total) +T3520 7857:806 JLINK_IsHalted() returns FALSE (0000ms, 48377ms total) +T3520 7857:907 JLINK_IsHalted() returns FALSE (0000ms, 48377ms total) +T3520 7858:008 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: C8 DC A9 19 returns 0x01 (0001ms, 48378ms total) +T2244 7858:009 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48379ms total) +T2244 7858:010 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48379ms total) +T3520 7858:015 JLINK_IsHalted() returns FALSE (0001ms, 48380ms total) +T3520 7858:117 JLINK_IsHalted() returns FALSE (0000ms, 48379ms total) +T3520 7858:219 JLINK_IsHalted() returns FALSE (0000ms, 48379ms total) +T3520 7858:320 JLINK_IsHalted() returns FALSE (0000ms, 48379ms total) +T3520 7858:421 JLINK_IsHalted() returns FALSE (0000ms, 48379ms total) +T3520 7858:523 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: CA 54 DF 1B returns 0x01 (0000ms, 48379ms total) +T2244 7858:524 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48379ms total) +T2244 7858:524 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48380ms total) +T3520 7858:532 JLINK_IsHalted() returns FALSE (0000ms, 48380ms total) +T3520 7858:633 JLINK_IsHalted() returns FALSE (0000ms, 48380ms total) +T3520 7858:733 JLINK_IsHalted() returns FALSE (0000ms, 48380ms total) +T3520 7858:835 JLINK_IsHalted() returns FALSE (0000ms, 48380ms total) +T3520 7858:937 JLINK_IsHalted() returns FALSE (0000ms, 48380ms total) +T3520 7859:037 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F8 18 15 1E returns 0x01 (0000ms, 48380ms total) +T2244 7859:038 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48381ms total) +T2244 7859:039 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48382ms total) +T3520 7859:044 JLINK_IsHalted() returns FALSE (0001ms, 48383ms total) +T3520 7859:145 JLINK_IsHalted() returns FALSE (0000ms, 48382ms total) +T3520 7859:247 JLINK_IsHalted() returns FALSE (0000ms, 48382ms total) +T3520 7859:348 JLINK_IsHalted() returns FALSE (0000ms, 48382ms total) +T3520 7859:449 JLINK_IsHalted() returns FALSE (0000ms, 48382ms total) +T3520 7859:550 JLINK_IsHalted() returns FALSE (0000ms, 48382ms total) +T3520 7859:652 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 52 10 B8 20 returns 0x01 (0000ms, 48382ms total) +T2244 7859:655 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48383ms total) +T2244 7859:656 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48384ms total) +T3520 7859:661 JLINK_IsHalted() returns FALSE (0000ms, 48384ms total) +T3520 7859:762 JLINK_IsHalted() returns FALSE (0000ms, 48384ms total) +T3520 7859:863 JLINK_IsHalted() returns FALSE (0000ms, 48384ms total) +T3520 7859:963 JLINK_IsHalted() returns FALSE (0000ms, 48384ms total) +T3520 7860:065 JLINK_IsHalted() returns FALSE (0000ms, 48384ms total) +T3520 7860:166 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9C A2 EC 22 returns 0x01 (0000ms, 48384ms total) +T2244 7860:166 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48384ms total) +T2244 7860:166 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48385ms total) +T3520 7860:171 JLINK_IsHalted() returns FALSE (0000ms, 48385ms total) +T3520 7860:273 JLINK_IsHalted() returns FALSE (0000ms, 48385ms total) +T3520 7860:374 JLINK_IsHalted() returns FALSE (0000ms, 48385ms total) +T3520 7860:475 JLINK_IsHalted() returns FALSE (0001ms, 48386ms total) +T3520 7860:577 JLINK_IsHalted() returns FALSE (0000ms, 48385ms total) +T3520 7860:678 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 75 7E 1F 25 returns 0x01 (0000ms, 48385ms total) +T2244 7860:679 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48386ms total) +T2244 7860:680 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48386ms total) +T3520 7860:688 JLINK_IsHalted() returns FALSE (0000ms, 48386ms total) +T3520 7860:790 JLINK_IsHalted() returns FALSE (0000ms, 48386ms total) +T3520 7860:891 JLINK_IsHalted() returns FALSE (0000ms, 48386ms total) +T3520 7860:992 JLINK_IsHalted() returns FALSE (0000ms, 48386ms total) +T3520 7861:093 JLINK_IsHalted() returns FALSE (0000ms, 48386ms total) +T3520 7861:194 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9F 0B 56 27 returns 0x01 (0000ms, 48386ms total) +T2244 7861:195 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48387ms total) +T2244 7861:196 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48388ms total) +T3520 7861:201 JLINK_IsHalted() returns FALSE (0001ms, 48389ms total) +T3520 7861:302 JLINK_IsHalted() returns FALSE (0000ms, 48388ms total) +T3520 7861:403 JLINK_IsHalted() returns FALSE (0000ms, 48388ms total) +T3520 7861:505 JLINK_IsHalted() returns FALSE (0000ms, 48388ms total) +T3520 7861:606 JLINK_IsHalted() returns FALSE (0000ms, 48388ms total) +T3520 7861:707 JLINK_IsHalted() returns FALSE (0000ms, 48388ms total) +T3520 7861:809 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 2E 9A F9 29 returns 0x01 (0000ms, 48388ms total) +T2244 7861:809 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48389ms total) +T2244 7861:810 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48390ms total) +T3520 7861:815 JLINK_IsHalted() returns FALSE (0000ms, 48390ms total) +T3520 7861:916 JLINK_IsHalted() returns FALSE (0000ms, 48390ms total) +T3520 7862:017 JLINK_IsHalted() returns FALSE (0000ms, 48390ms total) +T3520 7862:118 JLINK_IsHalted() returns FALSE (0000ms, 48390ms total) +T3520 7862:219 JLINK_IsHalted() returns FALSE (0000ms, 48390ms total) +T3520 7862:320 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 7F D7 2B 2C returns 0x01 (0001ms, 48391ms total) +T2244 7862:321 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48392ms total) +T2244 7862:322 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48393ms total) +T3520 7862:328 JLINK_IsHalted() returns FALSE (0000ms, 48393ms total) +T3520 7862:429 JLINK_IsHalted() returns FALSE (0000ms, 48393ms total) +T3520 7862:530 JLINK_IsHalted() returns FALSE (0000ms, 48393ms total) +T3520 7862:631 JLINK_IsHalted() returns FALSE (0000ms, 48393ms total) +T3520 7862:732 JLINK_IsHalted() returns FALSE (0000ms, 48393ms total) +T3520 7862:833 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 78 B4 5F 2E returns 0x01 (0000ms, 48393ms total) +T2244 7862:834 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0000ms, 48393ms total) +T2244 7862:835 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48394ms total) +T3520 7862:841 JLINK_IsHalted() returns FALSE (0000ms, 48394ms total) +T3520 7862:941 JLINK_IsHalted() returns FALSE (0001ms, 48395ms total) +T3520 7863:042 JLINK_IsHalted() returns FALSE (0000ms, 48394ms total) +T3520 7863:143 JLINK_IsHalted() returns FALSE (0000ms, 48394ms total) +T3520 7863:244 JLINK_IsHalted() returns FALSE (0000ms, 48394ms total) +T3520 7863:345 JLINK_IsHalted() returns FALSE (0000ms, 48394ms total) +T3520 7863:445 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 13 F7 FF 30 returns 0x01 (0000ms, 48394ms total) +T2244 7863:445 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0002ms, 48396ms total) +T2244 7863:447 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48396ms total) +T3520 7863:451 JLINK_IsHalted() returns FALSE (0001ms, 48397ms total) +T3520 7863:552 JLINK_IsHalted() returns FALSE (0000ms, 48396ms total) +T3520 7863:654 JLINK_IsHalted() returns FALSE (0000ms, 48396ms total) +T3520 7863:755 JLINK_IsHalted() returns FALSE (0000ms, 48396ms total) +T3520 7863:856 JLINK_IsHalted() returns FALSE (0000ms, 48396ms total) +T3520 7863:957 JLINK_IsHalted() returns FALSE (0000ms, 48396ms total) +T3520 7864:059 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 49 CF A1 33 returns 0x01 (0000ms, 48396ms total) +T2244 7864:061 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48397ms total) +T2244 7864:062 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48398ms total) +T3520 7864:072 JLINK_IsHalted() returns FALSE (0000ms, 48398ms total) +T3520 7864:173 JLINK_IsHalted() returns FALSE (0000ms, 48398ms total) +T3520 7864:274 JLINK_IsHalted() returns FALSE (0000ms, 48398ms total) +T3520 7864:375 JLINK_IsHalted() returns FALSE (0000ms, 48398ms total) +T3520 7864:475 JLINK_IsHalted() returns FALSE (0000ms, 48398ms total) +T3520 7864:576 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: EC A0 DA 35 returns 0x01 (0000ms, 48398ms total) +T2244 7864:577 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48399ms total) +T2244 7864:578 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48399ms total) +T3520 7864:582 JLINK_IsHalted() returns FALSE (0001ms, 48400ms total) +T3520 7864:684 JLINK_IsHalted() returns FALSE (0000ms, 48399ms total) +T3520 7864:785 JLINK_IsHalted() returns FALSE (0000ms, 48399ms total) +T3520 7864:887 JLINK_IsHalted() returns FALSE (0000ms, 48399ms total) +T3520 7864:988 JLINK_IsHalted() returns FALSE (0000ms, 48399ms total) +T3520 7865:089 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 57 7F 0D 38 returns 0x01 (0000ms, 48399ms total) +T2244 7865:091 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48400ms total) +T2244 7865:092 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0001ms, 48401ms total) +T3520 7865:098 JLINK_IsHalted() returns FALSE (0000ms, 48401ms total) +T3520 7865:199 JLINK_IsHalted() returns FALSE (0000ms, 48401ms total) +T3520 7865:300 JLINK_IsHalted() returns FALSE (0000ms, 48401ms total) +T3520 7865:400 JLINK_IsHalted() returns FALSE (0000ms, 48401ms total) +T3520 7865:502 JLINK_IsHalted() returns FALSE (0000ms, 48401ms total) +T3520 7865:603 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 66 F3 42 3A returns 0x01 (0000ms, 48401ms total) +T2244 7865:604 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48402ms total) +T2244 7865:605 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48402ms total) +T3520 7865:610 JLINK_IsHalted() returns FALSE (0000ms, 48402ms total) +T3520 7865:711 JLINK_Halt() returns 0x00 (0003ms, 48405ms total) +T3520 7865:714 JLINK_IsHalted() returns TRUE (0000ms, 48405ms total) +T3520 7865:714 JLINK_IsHalted() returns TRUE (0000ms, 48405ms total) +T3520 7865:714 JLINK_IsHalted() returns TRUE (0000ms, 48405ms total) +T3520 7865:714 JLINK_ReadReg(R15 (PC)) returns 0x080003EA (0000ms, 48405ms total) +T3520 7865:714 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002C) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002D) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002E) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002F) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x00000030) returns 0x00 (0000ms, 48405ms total) +T3520 7865:714 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 01 00 00 00 returns 0x01 (0001ms, 48406ms total) +T3520 7865:715 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0000ms, 48406ms total) +T3520 7865:715 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0001ms, 48407ms total) +T3520 7865:716 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0000ms, 48407ms total) +T3520 7865:716 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R1) returns 0x00070082 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R2) returns 0x40005400 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R3) returns 0x00030000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R5) returns 0x20000014 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R9) returns 0x20000160 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R10) returns 0x08000934 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R12) returns 0x000000C0 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R13 (SP)) returns 0x20000670 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R14) returns 0x080003EB (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(R15 (PC)) returns 0x080003EA (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(MSP) returns 0x20000670 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(PSP) returns 0x20001000 (0000ms, 48408ms total) +T3520 7865:717 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 48408ms total) +T2244 7865:719 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0001ms, 48409ms total) +T2244 7865:720 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00 returns 0x04 (0000ms, 48409ms total) +T2244 7865:721 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08 returns 0x04 (0000ms, 48409ms total) +T2244 7865:721 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: E2 A0 B9 3A returns 0x01 (0001ms, 48410ms total) +T2244 7865:722 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ... returns 0x20 (0001ms, 48411ms total) +T2244 7865:723 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00 returns 0x04 (0000ms, 48411ms total) +T2244 7865:730 JLINK_ReadMemEx(0x080003EA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003EA) - Data: 00 28 returns 0x02 (0001ms, 48412ms total) +T2244 7865:731 JLINK_ReadMemEx(0x080003EC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003EC) - Data: F9 D0 21 46 1A 48 00 F0 34 F9 00 BF 01 21 18 48 ... returns 0x3C (0001ms, 48413ms total) +T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EC) - Data: F9 D0 returns 0x02 (0000ms, 48413ms total) +T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003EC) - Data: F9 D0 21 46 1A 48 00 F0 34 F9 00 BF 01 21 18 48 ... returns 0x3C (0000ms, 48413ms total) +T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EC) - Data: F9 D0 returns 0x02 (0001ms, 48414ms total) +T2244 7865:733 JLINK_ReadMemEx(0x080003EE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EE) - Data: 21 46 returns 0x02 (0000ms, 48414ms total) +T2244 7865:733 JLINK_ReadMemEx(0x080003EE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EE) - Data: 21 46 returns 0x02 (0000ms, 48414ms total) +T2244 7865:733 JLINK_ReadMemEx(0x080003F0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F0) - Data: 1A 48 00 F0 34 F9 00 BF 01 21 18 48 00 F0 40 F8 ... returns 0x3C (0000ms, 48414ms total) +T2244 7865:733 JLINK_ReadMemEx(0x080003F0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F0) - Data: 1A 48 returns 0x02 (0000ms, 48414ms total) +T2244 7873:597 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22 returns 0x02 (0001ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ... returns 0x3C (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21 returns 0x02 (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48 returns 0x02 (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ... returns 0x3C (0000ms, 48415ms total) +T2244 7873:598 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0 returns 0x02 (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F0) - Data: 1A 48 00 F0 34 F9 00 BF 01 21 18 48 00 F0 40 F8 ... returns 0x3C (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F0) - Data: 1A 48 returns 0x02 (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F2) - Data: 00 F0 returns 0x02 (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F2) - Data: 00 F0 returns 0x02 (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F4, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F4) - Data: 34 F9 00 BF 01 21 18 48 00 F0 40 F8 00 28 F9 D0 ... returns 0x3C (0000ms, 48415ms total) +T2244 7874:221 JLINK_ReadMemEx(0x080003F4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F4, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003F4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F4) - Data: 34 F9 returns 0x02 (0000ms, 48415ms total) +T2244 7875:805 JLINK_ReadMemEx(0x080003E0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E0) - Data: 00 BF 20 49 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 ... returns 0x3C (0000ms, 48415ms total) +T2244 7875:805 JLINK_ReadMemEx(0x080003E0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E0) - Data: 00 BF returns 0x02 (0000ms, 48415ms total) +T2244 7875:805 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E2) - Data: 20 49 returns 0x02 (0001ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E2) - Data: 20 49 returns 0x02 (0000ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E4) - Data: 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 1A 48 00 F0 ... returns 0x3C (0000ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E4) - Data: 1D 48 returns 0x02 (0000ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E4) - Data: 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 1A 48 00 F0 ... returns 0x3C (0000ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E4) - Data: 1D 48 returns 0x02 (0000ms, 48416ms total) +T2244 7875:806 JLINK_ReadMemEx(0x080003E6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) + ***** Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E6) - Data: 00 F0 returns 0x02 (0000ms, 48416ms total) +T2244 7899:053 JLINK_Close() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) >0x80 JTAG> >0x08 JTAG> (0007ms, 48423ms total) +T2244 7899:053 (0007ms, 48423ms total) +T2244 7899:053 Closed (0007ms, 48423ms total) diff --git a/cmos/gc0307/stm32/Listings/gc0307.map b/cmos/gc0307/stm32/Listings/gc0307.map new file mode 100644 index 0000000..3d4a992 --- /dev/null +++ b/cmos/gc0307/stm32/Listings/gc0307.map @@ -0,0 +1,882 @@ +Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + +============================================================================== + +Section Cross References + + main.o(i.I2C1_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + main.o(i.I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_DeInit) for I2C_DeInit + main.o(i.I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_Init) for I2C_Init + main.o(i.I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_Cmd) for I2C_Cmd + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) for I2C_AcknowledgeConfig + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + main.o(i.I2C1_Read) refers to stm32f10x_i2c.o(i.I2C_ReceiveData) for I2C_ReceiveData + main.o(i.I2C_GPIO_Config) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + main.o(i.I2C_GPIO_Config) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + main.o(i.RCC_Configuration) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration + main.o(i.main) refers to main.o(i.I2C_GPIO_Config) for I2C_GPIO_Config + main.o(i.main) refers to main.o(i.I2C1_Init) for I2C1_Init + main.o(i.main) refers to main.o(i.I2C1_Read) for I2C1_Read + i2c_ee.o(i.GPIO_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + i2c_ee.o(i.I2C_Configuration) refers to stm32f10x_i2c.o(i.I2C_Cmd) for I2C_Cmd + i2c_ee.o(i.I2C_Configuration) refers to stm32f10x_i2c.o(i.I2C_Init) for I2C_Init + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_GetFlagStatus) for I2C_GetFlagStatus + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_Cmd) for I2C_Cmd + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) for I2C_AcknowledgeConfig + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c_ee.o(i.I2C_EE_BufferRead) refers to stm32f10x_i2c.o(i.I2C_ReceiveData) for I2C_ReceiveData + i2c_ee.o(i.I2C_EE_BufferWrite) refers to i2c_ee.o(i.I2C_EE_PageWrite) for I2C_EE_PageWrite + i2c_ee.o(i.I2C_EE_BufferWrite) refers to i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) for I2C_EE_WaitEepromStandbyState + i2c_ee.o(i.I2C_EE_ByteWrite) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c_ee.o(i.I2C_EE_ByteWrite) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + i2c_ee.o(i.I2C_EE_ByteWrite) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c_ee.o(i.I2C_EE_ByteWrite) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + i2c_ee.o(i.I2C_EE_ByteWrite) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c_ee.o(i.I2C_EE_ByteWrite) refers to i2c_ee.o(.data) for EEPROM_ADDRESS + i2c_ee.o(i.I2C_EE_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + i2c_ee.o(i.I2C_EE_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + i2c_ee.o(i.I2C_EE_Init) refers to i2c_ee.o(i.GPIO_Configuration) for GPIO_Configuration + i2c_ee.o(i.I2C_EE_Init) refers to i2c_ee.o(i.I2C_Configuration) for I2C_Configuration + i2c_ee.o(i.I2C_EE_Init) refers to i2c_ee.o(.data) for EEPROM_ADDRESS + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_GetFlagStatus) for I2C_GetFlagStatus + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + i2c_ee.o(i.I2C_EE_PageWrite) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c_ee.o(i.I2C_EE_PageWrite) refers to i2c_ee.o(.data) for EEPROM_ADDRESS + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_ReadRegister) for I2C_ReadRegister + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_ClearFlag) for I2C_ClearFlag + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to i2c_ee.o(.data) for EEPROM_ADDRESS + stm32f10x_i2c.o(i.I2C_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_i2c.o(i.I2C_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable + stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp + startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler + startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler + startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem + startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem + system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_GetPortClockState) for GPIO_GetPortClockState + gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_PortClock) for GPIO_PortClock + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing stm32f10x_it.o(.rev16_text), (4 bytes). + Removing stm32f10x_it.o(.revsh_text), (4 bytes). + Removing stm32f10x_it.o(.rrx_text), (6 bytes). + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing main.o(.rrx_text), (6 bytes). + Removing main.o(i.Buffercmp), (36 bytes). + Removing main.o(.bss), (44 bytes). + Removing main.o(.data), (48 bytes). + Removing i2c_ee.o(.rev16_text), (4 bytes). + Removing i2c_ee.o(.revsh_text), (4 bytes). + Removing i2c_ee.o(.rrx_text), (6 bytes). + Removing i2c_ee.o(i.GPIO_Configuration), (36 bytes). + Removing i2c_ee.o(i.I2C_Configuration), (64 bytes). + Removing i2c_ee.o(i.I2C_EE_BufferRead), (224 bytes). + Removing i2c_ee.o(i.I2C_EE_BufferWrite), (336 bytes). + Removing i2c_ee.o(i.I2C_EE_ByteWrite), (128 bytes). + Removing i2c_ee.o(i.I2C_EE_Init), (40 bytes). + Removing i2c_ee.o(i.I2C_EE_PageWrite), (160 bytes). + Removing i2c_ee.o(i.I2C_EE_WaitEepromStandbyState), (84 bytes). + Removing i2c_ee.o(.data), (2 bytes). + Removing misc.o(.rev16_text), (4 bytes). + Removing misc.o(.revsh_text), (4 bytes). + Removing misc.o(.rrx_text), (6 bytes). + Removing misc.o(i.NVIC_Init), (112 bytes). + Removing misc.o(i.NVIC_PriorityGroupConfig), (20 bytes). + Removing misc.o(i.NVIC_SetVectorTable), (20 bytes). + Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes). + Removing misc.o(i.SysTick_CLKSourceConfig), (40 bytes). + Removing stm32f10x_dbgmcu.o(.rev16_text), (4 bytes). + Removing stm32f10x_dbgmcu.o(.revsh_text), (4 bytes). + Removing stm32f10x_dbgmcu.o(.rrx_text), (6 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_Config), (32 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetDEVID), (16 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetREVID), (12 bytes). + Removing stm32f10x_i2c.o(.rev16_text), (4 bytes). + Removing stm32f10x_i2c.o(.revsh_text), (4 bytes). + Removing stm32f10x_i2c.o(.rrx_text), (6 bytes). + Removing stm32f10x_i2c.o(i.I2C_ARPCmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_CalculatePEC), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_ClearFlag), (12 bytes). + Removing stm32f10x_i2c.o(i.I2C_ClearITPendingBit), (12 bytes). + Removing stm32f10x_i2c.o(i.I2C_DMACmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_DMALastTransferCmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_DualAddressCmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_FastModeDutyCycleConfig), (28 bytes). + Removing stm32f10x_i2c.o(i.I2C_GeneralCallCmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetFlagStatus), (58 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetITStatus), (38 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetLastEvent), (26 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetPEC), (8 bytes). + Removing stm32f10x_i2c.o(i.I2C_ITConfig), (18 bytes). + Removing stm32f10x_i2c.o(i.I2C_NACKPositionConfig), (28 bytes). + Removing stm32f10x_i2c.o(i.I2C_OwnAddress2Config), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_PECPositionConfig), (28 bytes). + Removing stm32f10x_i2c.o(i.I2C_ReadRegister), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_SMBusAlertConfig), (28 bytes). + Removing stm32f10x_i2c.o(i.I2C_SoftwareResetCmd), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_StretchClockCmd), (24 bytes). + Removing stm32f10x_i2c.o(i.I2C_StructInit), (30 bytes). + Removing stm32f10x_i2c.o(i.I2C_TransmitPEC), (24 bytes). + Removing stm32f10x_rcc.o(.rev16_text), (4 bytes). + Removing stm32f10x_rcc.o(.revsh_text), (4 bytes). + Removing stm32f10x_rcc.o(.rrx_text), (6 bytes). + Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_DeInit), (76 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetFlagStatus), (60 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (76 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (28 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (56 bytes). + Removing system_stm32f10x.o(.rev16_text), (4 bytes). + Removing system_stm32f10x.o(.revsh_text), (4 bytes). + Removing system_stm32f10x.o(.rrx_text), (6 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + Removing stm32f10x_gpio.o(.rev16_text), (4 bytes). + Removing stm32f10x_gpio.o(.revsh_text), (4 bytes). + Removing stm32f10x_gpio.o(.rrx_text), (6 bytes). + Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes). + Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ResetBits), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_SetBits), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes). + Removing gpio_stm32f10x.o(.rev16_text), (4 bytes). + Removing gpio_stm32f10x.o(.revsh_text), (4 bytes). + Removing gpio_stm32f10x.o(.rrx_text), (6 bytes). + Removing gpio_stm32f10x.o(i.GPIO_AFConfigure), (156 bytes). + Removing gpio_stm32f10x.o(i.GPIO_GetPortClockState), (152 bytes). + Removing gpio_stm32f10x.o(i.GPIO_PinConfigure), (120 bytes). + Removing gpio_stm32f10x.o(i.GPIO_PortClock), (316 bytes). + +124 unused section(s) (total 4490 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_dbgmcu.c 0x00000000 Number 0 stm32f10x_dbgmcu.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_i2c.c 0x00000000 Number 0 stm32f10x_i2c.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\RTE_Driver\\GPIO_STM32F10x.c 0x00000000 Number 0 gpio_stm32f10x.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_dbgmcu.c 0x00000000 Number 0 stm32f10x_dbgmcu.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_i2c.c 0x00000000 Number 0 stm32f10x_i2c.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.c 0x00000000 Number 0 gpio_stm32f10x.o ABSOLUTE + RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE + RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + src\\i2c_ee.c 0x00000000 Number 0 i2c_ee.o ABSOLUTE + src\\main.c 0x00000000 Number 0 main.o ABSOLUTE + src\\stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + src\i2c_ee.c 0x00000000 Number 0 i2c_ee.o ABSOLUTE + src\main.c 0x00000000 Number 0 main.o ABSOLUTE + src\stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET) + !!!main 0x080000ec Section 8 __main.o(!!!main) + !!!scatter 0x080000f4 Section 52 __scatter.o(!!!scatter) + !!handler_copy 0x08000128 Section 26 __scatter_copy.o(!!handler_copy) + !!handler_zi 0x08000144 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$libinit$$00000000 0x08000160 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000002 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + .ARM.Collect$$libinit$$00000004 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x08000162 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x08000164 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x08000166 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x08000168 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x08000168 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x08000168 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0800016e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0800016e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x08000172 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x08000172 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x0800017a Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x0800017c Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x0800017c Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x08000180 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x08000188 Section 64 startup_stm32f10x_md.o(.text) + .text 0x080001c8 Section 0 heapauxi.o(.text) + .text 0x080001ce Section 74 sys_stackheap_outer.o(.text) + .text 0x08000218 Section 0 exit.o(.text) + .text 0x0800022c Section 8 libspace.o(.text) + .text 0x08000234 Section 0 sys_exit.o(.text) + .text 0x08000240 Section 2 use_no_semi.o(.text) + .text 0x08000242 Section 0 indicate_semi.o(.text) + i.BusFault_Handler 0x08000242 Section 0 stm32f10x_it.o(i.BusFault_Handler) + i.DebugMon_Handler 0x08000246 Section 0 stm32f10x_it.o(i.DebugMon_Handler) + i.GPIO_Init 0x08000248 Section 0 stm32f10x_gpio.o(i.GPIO_Init) + i.HardFault_Handler 0x0800035e Section 0 stm32f10x_it.o(i.HardFault_Handler) + i.I2C1_Init 0x08000364 Section 0 main.o(i.I2C1_Init) + i.I2C1_Read 0x080003b4 Section 0 main.o(i.I2C1_Read) + i.I2C_AcknowledgeConfig 0x08000468 Section 0 stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) + i.I2C_CheckEvent 0x08000480 Section 0 stm32f10x_i2c.o(i.I2C_CheckEvent) + i.I2C_Cmd 0x080004aa Section 0 stm32f10x_i2c.o(i.I2C_Cmd) + i.I2C_DeInit 0x080004c4 Section 0 stm32f10x_i2c.o(i.I2C_DeInit) + i.I2C_GPIO_Config 0x080004fc Section 0 main.o(i.I2C_GPIO_Config) + i.I2C_GenerateSTART 0x08000528 Section 0 stm32f10x_i2c.o(i.I2C_GenerateSTART) + i.I2C_GenerateSTOP 0x08000540 Section 0 stm32f10x_i2c.o(i.I2C_GenerateSTOP) + i.I2C_Init 0x08000558 Section 0 stm32f10x_i2c.o(i.I2C_Init) + i.I2C_ReceiveData 0x08000644 Section 0 stm32f10x_i2c.o(i.I2C_ReceiveData) + i.I2C_Send7bitAddress 0x0800064c Section 0 stm32f10x_i2c.o(i.I2C_Send7bitAddress) + i.I2C_SendData 0x0800065e Section 0 stm32f10x_i2c.o(i.I2C_SendData) + i.MemManage_Handler 0x08000662 Section 0 stm32f10x_it.o(i.MemManage_Handler) + i.NMI_Handler 0x08000666 Section 0 stm32f10x_it.o(i.NMI_Handler) + i.PendSV_Handler 0x08000668 Section 0 stm32f10x_it.o(i.PendSV_Handler) + i.RCC_APB1PeriphClockCmd 0x0800066c Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + i.RCC_APB1PeriphResetCmd 0x0800068c Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) + i.RCC_APB2PeriphClockCmd 0x080006ac Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + i.RCC_Configuration 0x080006cc Section 0 main.o(i.RCC_Configuration) + i.RCC_GetClocksFreq 0x080006d4 Section 0 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + i.SVC_Handler 0x080007a8 Section 0 stm32f10x_it.o(i.SVC_Handler) + i.SetSysClock 0x080007aa Section 0 system_stm32f10x.o(i.SetSysClock) + SetSysClock 0x080007ab Thumb Code 8 system_stm32f10x.o(i.SetSysClock) + i.SetSysClockTo72 0x080007b4 Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x080007b5 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) + i.SysTick_Handler 0x08000894 Section 0 stm32f10x_it.o(i.SysTick_Handler) + i.SystemInit 0x08000898 Section 0 system_stm32f10x.o(i.SystemInit) + i.UsageFault_Handler 0x080008f8 Section 0 stm32f10x_it.o(i.UsageFault_Handler) + i.main 0x080008fc Section 0 main.o(i.main) + .data 0x20000000 Section 20 stm32f10x_rcc.o(.data) + APBAHBPrescTable 0x20000000 Data 16 stm32f10x_rcc.o(.data) + ADCPrescTable 0x20000010 Data 4 stm32f10x_rcc.o(.data) + .bss 0x20000014 Section 96 libspace.o(.bss) + HEAP 0x20000078 Section 512 startup_stm32f10x_md.o(HEAP) + Heap_Mem 0x20000078 Data 512 startup_stm32f10x_md.o(HEAP) + STACK 0x20000278 Section 1024 startup_stm32f10x_md.o(STACK) + Stack_Mem 0x20000278 Data 1024 startup_stm32f10x_md.o(STACK) + __initial_sp 0x20000678 Data 0 startup_stm32f10x_md.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET) + __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET) + __main 0x080000ed Thumb Code 8 __main.o(!!!main) + __scatterload 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x080000f5 Thumb Code 44 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x08000103 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_copy 0x08000129 Thumb Code 26 __scatter_copy.o(!!handler_copy) + __scatterload_zeroinit 0x08000145 Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x08000161 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_alloca_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_argv_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_atexit_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_clock_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_cpp_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_exceptions_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_fp_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + __rt_lib_init_fp_trap_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_getenv_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_heap_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_init_lc_collate_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_ctype_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_monetary_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_numeric_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_time_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_preinit_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_rand_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_init_return 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033) + __rt_lib_init_signal_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_stdio_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_init_user_alloc_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_shutdown 0x08000165 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x08000169 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x08000169 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x08000169 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x0800016f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x0800016f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x08000173 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x08000173 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x0800017b Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x0800017d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x0800017d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x08000181 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x08000189 Thumb Code 8 startup_stm32f10x_md.o(.text) + ADC1_2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_RX1_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_SCE_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel1_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel3_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel4_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel5_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel6_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel7_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI0_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI15_10_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI1_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI3_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI4_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI9_5_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + FLASH_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_ER_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_EV_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_ER_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_EV_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + PVD_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RCC_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RTCAlarm_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + RTC_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI1_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TAMPER_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_BRK_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_CC_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_TRG_COM_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_UP_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM3_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM4_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART1_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART2_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USART3_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USBWakeUp_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + WWDG_IRQHandler 0x080001a3 Thumb Code 0 startup_stm32f10x_md.o(.text) + __user_initial_stackheap 0x080001a5 Thumb Code 0 startup_stm32f10x_md.o(.text) + __use_two_region_memory 0x080001c9 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x080001cb Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x080001cd Thumb Code 2 heapauxi.o(.text) + __user_setup_stackheap 0x080001cf Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x08000219 Thumb Code 18 exit.o(.text) + __user_libspace 0x0800022d Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x0800022d Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x0800022d Thumb Code 0 libspace.o(.text) + _sys_exit 0x08000235 Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x08000241 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x08000241 Thumb Code 2 use_no_semi.o(.text) + BusFault_Handler 0x08000243 Thumb Code 4 stm32f10x_it.o(i.BusFault_Handler) + __semihosting_library_function 0x08000243 Thumb Code 0 indicate_semi.o(.text) + DebugMon_Handler 0x08000247 Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler) + GPIO_Init 0x08000249 Thumb Code 278 stm32f10x_gpio.o(i.GPIO_Init) + HardFault_Handler 0x0800035f Thumb Code 4 stm32f10x_it.o(i.HardFault_Handler) + I2C1_Init 0x08000365 Thumb Code 74 main.o(i.I2C1_Init) + I2C1_Read 0x080003b5 Thumb Code 168 main.o(i.I2C1_Read) + I2C_AcknowledgeConfig 0x08000469 Thumb Code 24 stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) + I2C_CheckEvent 0x08000481 Thumb Code 42 stm32f10x_i2c.o(i.I2C_CheckEvent) + I2C_Cmd 0x080004ab Thumb Code 24 stm32f10x_i2c.o(i.I2C_Cmd) + I2C_DeInit 0x080004c5 Thumb Code 50 stm32f10x_i2c.o(i.I2C_DeInit) + I2C_GPIO_Config 0x080004fd Thumb Code 38 main.o(i.I2C_GPIO_Config) + I2C_GenerateSTART 0x08000529 Thumb Code 24 stm32f10x_i2c.o(i.I2C_GenerateSTART) + I2C_GenerateSTOP 0x08000541 Thumb Code 24 stm32f10x_i2c.o(i.I2C_GenerateSTOP) + I2C_Init 0x08000559 Thumb Code 222 stm32f10x_i2c.o(i.I2C_Init) + I2C_ReceiveData 0x08000645 Thumb Code 8 stm32f10x_i2c.o(i.I2C_ReceiveData) + I2C_Send7bitAddress 0x0800064d Thumb Code 18 stm32f10x_i2c.o(i.I2C_Send7bitAddress) + I2C_SendData 0x0800065f Thumb Code 4 stm32f10x_i2c.o(i.I2C_SendData) + MemManage_Handler 0x08000663 Thumb Code 4 stm32f10x_it.o(i.MemManage_Handler) + NMI_Handler 0x08000667 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler) + PendSV_Handler 0x08000669 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler) + RCC_APB1PeriphClockCmd 0x0800066d Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + RCC_APB1PeriphResetCmd 0x0800068d Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) + RCC_APB2PeriphClockCmd 0x080006ad Thumb Code 26 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + RCC_Configuration 0x080006cd Thumb Code 8 main.o(i.RCC_Configuration) + RCC_GetClocksFreq 0x080006d5 Thumb Code 192 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + SVC_Handler 0x080007a9 Thumb Code 2 stm32f10x_it.o(i.SVC_Handler) + SysTick_Handler 0x08000895 Thumb Code 2 stm32f10x_it.o(i.SysTick_Handler) + SystemInit 0x08000899 Thumb Code 78 system_stm32f10x.o(i.SystemInit) + UsageFault_Handler 0x080008f9 Thumb Code 4 stm32f10x_it.o(i.UsageFault_Handler) + main 0x080008fd Thumb Code 22 main.o(i.main) + Region$$Table$$Base 0x08000914 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08000934 Number 0 anon$$obj.o(Region$$Table) + __libspace_start 0x20000014 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x20000074 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000189 + + Load Region LR_1 (Base: 0x08000000, Size: 0x00000948, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000934, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000000ec Data RO 767 RESET startup_stm32f10x_md.o + 0x080000ec 0x080000ec 0x00000008 Code RO 996 * !!!main c_w.l(__main.o) + 0x080000f4 0x080000f4 0x00000034 Code RO 1153 !!!scatter c_w.l(__scatter.o) + 0x08000128 0x08000128 0x0000001a Code RO 1155 !!handler_copy c_w.l(__scatter_copy.o) + 0x08000142 0x08000142 0x00000002 PAD + 0x08000144 0x08000144 0x0000001c Code RO 1157 !!handler_zi c_w.l(__scatter_zi.o) + 0x08000160 0x08000160 0x00000002 Code RO 1023 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x08000162 0x08000162 0x00000000 Code RO 1030 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1032 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1035 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1037 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1039 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1042 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1044 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1046 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1048 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1050 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1052 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1054 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1056 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1058 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1060 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1062 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1066 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1068 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1070 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000000 Code RO 1072 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x08000162 0x08000162 0x00000002 Code RO 1073 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x08000164 0x08000164 0x00000002 Code RO 1093 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x08000166 0x08000166 0x00000000 Code RO 1106 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000000 Code RO 1108 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000000 Code RO 1111 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000000 Code RO 1114 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000000 Code RO 1116 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000000 Code RO 1119 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x08000166 0x08000166 0x00000002 Code RO 1120 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x08000168 0x08000168 0x00000000 Code RO 998 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x08000168 0x08000168 0x00000000 Code RO 1000 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x08000168 0x08000168 0x00000006 Code RO 1012 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0800016e 0x0800016e 0x00000000 Code RO 1002 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0800016e 0x0800016e 0x00000004 Code RO 1003 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x08000172 0x08000172 0x00000000 Code RO 1005 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x08000172 0x08000172 0x00000008 Code RO 1006 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x0800017a 0x0800017a 0x00000002 Code RO 1027 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x0800017c 0x0800017c 0x00000000 Code RO 1075 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x0800017c 0x0800017c 0x00000004 Code RO 1076 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x08000180 0x08000180 0x00000006 Code RO 1077 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x08000186 0x08000186 0x00000002 PAD + 0x08000188 0x08000188 0x00000040 Code RO 768 * .text startup_stm32f10x_md.o + 0x080001c8 0x080001c8 0x00000006 Code RO 994 .text c_w.l(heapauxi.o) + 0x080001ce 0x080001ce 0x0000004a Code RO 1014 .text c_w.l(sys_stackheap_outer.o) + 0x08000218 0x08000218 0x00000012 Code RO 1016 .text c_w.l(exit.o) + 0x0800022a 0x0800022a 0x00000002 PAD + 0x0800022c 0x0800022c 0x00000008 Code RO 1024 .text c_w.l(libspace.o) + 0x08000234 0x08000234 0x0000000c Code RO 1085 .text c_w.l(sys_exit.o) + 0x08000240 0x08000240 0x00000002 Code RO 1096 .text c_w.l(use_no_semi.o) + 0x08000242 0x08000242 0x00000000 Code RO 1098 .text c_w.l(indicate_semi.o) + 0x08000242 0x08000242 0x00000004 Code RO 4 i.BusFault_Handler stm32f10x_it.o + 0x08000246 0x08000246 0x00000002 Code RO 5 i.DebugMon_Handler stm32f10x_it.o + 0x08000248 0x08000248 0x00000116 Code RO 827 i.GPIO_Init stm32f10x_gpio.o + 0x0800035e 0x0800035e 0x00000004 Code RO 6 i.HardFault_Handler stm32f10x_it.o + 0x08000362 0x08000362 0x00000002 PAD + 0x08000364 0x08000364 0x00000050 Code RO 127 i.I2C1_Init main.o + 0x080003b4 0x080003b4 0x000000b4 Code RO 128 i.I2C1_Read main.o + 0x08000468 0x08000468 0x00000018 Code RO 341 i.I2C_AcknowledgeConfig stm32f10x_i2c.o + 0x08000480 0x08000480 0x0000002a Code RO 343 i.I2C_CheckEvent stm32f10x_i2c.o + 0x080004aa 0x080004aa 0x00000018 Code RO 346 i.I2C_Cmd stm32f10x_i2c.o + 0x080004c2 0x080004c2 0x00000002 PAD + 0x080004c4 0x080004c4 0x00000038 Code RO 349 i.I2C_DeInit stm32f10x_i2c.o + 0x080004fc 0x080004fc 0x0000002c Code RO 129 i.I2C_GPIO_Config main.o + 0x08000528 0x08000528 0x00000018 Code RO 353 i.I2C_GenerateSTART stm32f10x_i2c.o + 0x08000540 0x08000540 0x00000018 Code RO 354 i.I2C_GenerateSTOP stm32f10x_i2c.o + 0x08000558 0x08000558 0x000000ec Code RO 360 i.I2C_Init stm32f10x_i2c.o + 0x08000644 0x08000644 0x00000008 Code RO 365 i.I2C_ReceiveData stm32f10x_i2c.o + 0x0800064c 0x0800064c 0x00000012 Code RO 367 i.I2C_Send7bitAddress stm32f10x_i2c.o + 0x0800065e 0x0800065e 0x00000004 Code RO 368 i.I2C_SendData stm32f10x_i2c.o + 0x08000662 0x08000662 0x00000004 Code RO 7 i.MemManage_Handler stm32f10x_it.o + 0x08000666 0x08000666 0x00000002 Code RO 8 i.NMI_Handler stm32f10x_it.o + 0x08000668 0x08000668 0x00000002 Code RO 9 i.PendSV_Handler stm32f10x_it.o + 0x0800066a 0x0800066a 0x00000002 PAD + 0x0800066c 0x0800066c 0x00000020 Code RO 558 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o + 0x0800068c 0x0800068c 0x00000020 Code RO 559 i.RCC_APB1PeriphResetCmd stm32f10x_rcc.o + 0x080006ac 0x080006ac 0x00000020 Code RO 560 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x080006cc 0x080006cc 0x00000008 Code RO 130 i.RCC_Configuration main.o + 0x080006d4 0x080006d4 0x000000d4 Code RO 568 i.RCC_GetClocksFreq stm32f10x_rcc.o + 0x080007a8 0x080007a8 0x00000002 Code RO 10 i.SVC_Handler stm32f10x_it.o + 0x080007aa 0x080007aa 0x00000008 Code RO 775 i.SetSysClock system_stm32f10x.o + 0x080007b2 0x080007b2 0x00000002 PAD + 0x080007b4 0x080007b4 0x000000e0 Code RO 776 i.SetSysClockTo72 system_stm32f10x.o + 0x08000894 0x08000894 0x00000002 Code RO 11 i.SysTick_Handler stm32f10x_it.o + 0x08000896 0x08000896 0x00000002 PAD + 0x08000898 0x08000898 0x00000060 Code RO 778 i.SystemInit system_stm32f10x.o + 0x080008f8 0x080008f8 0x00000004 Code RO 12 i.UsageFault_Handler stm32f10x_it.o + 0x080008fc 0x080008fc 0x00000016 Code RO 131 i.main main.o + 0x08000912 0x08000912 0x00000002 PAD + 0x08000914 0x08000914 0x00000020 Data RO 1151 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000934, Size: 0x00000014, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x08000934 0x00000014 Data RW 588 .data stm32f10x_rcc.o + + + Execution Region ER_ZI (Exec base: 0x20000014, Load base: 0x08000948, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000014 - 0x00000060 Zero RW 1025 .bss c_w.l(libspace.o) + 0x20000074 0x08000948 0x00000004 PAD + 0x20000078 - 0x00000200 Zero RW 766 HEAP startup_stm32f10x_md.o + 0x20000278 - 0x00000400 Zero RW 765 STACK startup_stm32f10x_md.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 334 24 0 0 0 2313 main.o + 64 26 236 0 1536 812 startup_stm32f10x_md.o + 278 0 0 0 0 2184 stm32f10x_gpio.o + 460 20 0 0 0 8037 stm32f10x_i2c.o + 26 0 0 0 0 235306 stm32f10x_it.o + 308 38 0 20 0 5303 stm32f10x_rcc.o + 328 28 0 0 0 2077 system_stm32f10x.o + + ---------------------------------------------------------------------- + 1810 136 268 20 1536 256032 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 12 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 2 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + + ---------------------------------------------------------------------- + 278 16 0 0 100 584 Library Totals + 6 0 0 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 272 16 0 0 96 584 c_w.l + + ---------------------------------------------------------------------- + 278 16 0 0 100 584 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 2088 152 268 20 1636 254948 Grand Totals + 2088 152 268 20 1636 254948 ELF Image Totals + 2088 152 268 20 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 2356 ( 2.30kB) + Total RW Size (RW Data + ZI Data) 1656 ( 1.62kB) + Total ROM Size (Code + RO Data + RW Data) 2376 ( 2.32kB) + +============================================================================== + diff --git a/cmos/gc0307/stm32/Objects/gc0307.axf b/cmos/gc0307/stm32/Objects/gc0307.axf new file mode 100644 index 0000000..8442423 Binary files /dev/null and b/cmos/gc0307/stm32/Objects/gc0307.axf differ diff --git a/cmos/gc0307/stm32/Objects/gc0307.lnp b/cmos/gc0307/stm32/Objects/gc0307.lnp new file mode 100644 index 0000000..17a875b --- /dev/null +++ b/cmos/gc0307/stm32/Objects/gc0307.lnp @@ -0,0 +1,15 @@ +--cpu Cortex-M3 +".\objects\stm32f10x_it.o" +".\objects\main.o" +".\objects\i2c_ee.o" +".\objects\misc.o" +".\objects\stm32f10x_dbgmcu.o" +".\objects\stm32f10x_i2c.o" +".\objects\stm32f10x_rcc.o" +".\objects\startup_stm32f10x_md.o" +".\objects\system_stm32f10x.o" +".\objects\stm32f10x_gpio.o" +".\objects\gpio_stm32f10x.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\gc0307.map" -o .\Objects\gc0307.axf \ No newline at end of file diff --git a/cmos/gc0307/stm32/RTE/Device/STM32F103RB/RTE_Device.h b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/RTE_Device.h new file mode 100644 index 0000000..d53b023 --- /dev/null +++ b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1811 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2016 ARM Limited. All rights reserved. + * + * $Date: 29. August 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/cmos/gc0307/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..74da96c --- /dev/null +++ b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,307 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/cmos/gc0307/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h new file mode 100644 index 0000000..e49e560 --- /dev/null +++ b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.5.0 + * @date 08-April-2011 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Run Time Environment will set specific #define for each selected module below */ +#include "RTE_Components.h" + +#ifdef RTE_DEVICE_STDPERIPH_ADC +#include "stm32f10x_adc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_BKP +#include "stm32f10x_bkp.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CAN +#include "stm32f10x_can.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CEC +#include "stm32f10x_cec.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_CRC +#include "stm32f10x_crc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DAC +#include "stm32f10x_dac.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DBGMCU +#include "stm32f10x_dbgmcu.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_DMA +#include "stm32f10x_dma.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_EXTI +#include "stm32f10x_exti.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FLASH +#include "stm32f10x_flash.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FSMC +#include "stm32f10x_fsmc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_GPIO +#include "stm32f10x_gpio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_I2C +#include "stm32f10x_i2c.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_IWDG +#include "stm32f10x_iwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_PWR +#include "stm32f10x_pwr.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RCC +#include "stm32f10x_rcc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_RTC +#include "stm32f10x_rtc.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SDIO +#include "stm32f10x_sdio.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_SPI +#include "stm32f10x_spi.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_TIM +#include "stm32f10x_tim.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_USART +#include "stm32f10x_usart.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_WWDG +#include "stm32f10x_wwdg.h" +#endif +#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..71efc85 --- /dev/null +++ b/cmos/gc0307/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/RTE/_Target_1/RTE_Components.h b/cmos/gc0307/stm32/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..081124b --- /dev/null +++ b/cmos/gc0307/stm32/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,31 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'gc0307' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + +/* Keil::Device:StdPeriph Drivers:DBGMCU:3.5.0 */ +#define RTE_DEVICE_STDPERIPH_DBGMCU +/* Keil::Device:StdPeriph Drivers:Framework:3.5.1 */ +#define RTE_DEVICE_STDPERIPH_FRAMEWORK +/* Keil::Device:StdPeriph Drivers:GPIO:3.5.0 */ +#define RTE_DEVICE_STDPERIPH_GPIO +/* Keil::Device:StdPeriph Drivers:I2C:3.5.0 */ +#define RTE_DEVICE_STDPERIPH_I2C +/* Keil::Device:StdPeriph Drivers:RCC:3.5.0 */ +#define RTE_DEVICE_STDPERIPH_RCC + + +#endif /* RTE_COMPONENTS_H */ diff --git a/cmos/gc0307/stm32/gc0307.uvoptx b/cmos/gc0307/stm32/gc0307.uvoptx new file mode 100644 index 0000000..c867587 --- /dev/null +++ b/cmos/gc0307/stm32/gc0307.uvoptx @@ -0,0 +1,399 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + d + + + 0 + JL2CM3 + -U20080643 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("ST TMC") -D01(16410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + + + + + 0 + 0 + 120 + 1 +
134220050
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\120 + + + 1 + 0 + 117 + 1 +
134220044
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\117 + + + 2 + 0 + 112 + 1 +
134220032
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\112 + + + 3 + 0 + 94 + 1 +
134218758
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\94 + + + 4 + 0 + 91 + 1 +
134218734
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\91 + + + 5 + 0 + 89 + 1 +
134218710
+ 0 + 0 + 0 + 0 + 0 + 1 + .\src\main.c + + \\gc0307\src/main.c\89 + + + 6 + 0 + 212 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + .\src\i2c_ee.c + + + + + 7 + 0 + 218 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + .\src\i2c_ee.c + + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\I2C1 + 35905 + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\src\stm32f10x_it.c + stm32f10x_it.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\src\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\src\i2c_ee.c + i2c_ee.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/cmos/gc0307/stm32/gc0307.uvprojx b/cmos/gc0307/stm32/gc0307.uvprojx new file mode 100644 index 0000000..0f4a4eb --- /dev/null +++ b/cmos/gc0307/stm32/gc0307.uvprojx @@ -0,0 +1,500 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F103RB + STMicroelectronics + Keil.STM32F1xx_DFP.2.2.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 0 + $$Device:STM32F103RB$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RB$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + gc0307 + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + stm32f10x_it.c + 1 + .\src\stm32f10x_it.c + + + main.c + 1 + .\src\main.c + + + i2c_ee.c + 1 + .\src\i2c_ee.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F103RB\RTE_Device.h + + + + + + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + + + + + RTE\Device\STM32F103RB\stm32f10x_conf.h + + + + + + + + RTE\Device\STM32F103RB\system_stm32f10x.c + + + + + + + + + + diff --git a/cmos/gc0307/stm32/src/i2c_ee.c b/cmos/gc0307/stm32/src/i2c_ee.c new file mode 100644 index 0000000..f844ed0 --- /dev/null +++ b/cmos/gc0307/stm32/src/i2c_ee.c @@ -0,0 +1,484 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/i2c_ee.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides a set of functions needed to manage the + * communication between I2C peripheral and I2C M24CXX EEPROM. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "i2c_ee.h" + +/** @addtogroup STM32F10x_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_EEPROM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define I2C_Speed 200000 +#define I2C_SLAVE_ADDRESS7 0x42 + +#if defined (EE_M24C08) + #define I2C_FLASH_PAGESIZE 16 +#elif defined (EE_M24C64_32) + #define I2C_FLASH_PAGESIZE 32 +#endif + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t EEPROM_ADDRESS; + +/* Private function prototypes -----------------------------------------------*/ +void GPIO_Configuration(void); +void I2C_Configuration(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Configure the used I/O ports pin + * @param None + * @retval None + */ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure I2C_EE pins: SCL and SDA */ + GPIO_InitStructure.GPIO_Pin = I2C_EE_SCL | I2C_EE_SDA; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; + GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure); +} + +/** + * @brief I2C Configuration + * @param None + * @retval None + */ +void I2C_Configuration(void) +{ + I2C_InitTypeDef I2C_InitStructure; + + /* I2C configuration */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = 10000; + + /* I2C Peripheral Enable */ + I2C_Cmd(I2C_EE, ENABLE); + /* Apply I2C configuration after enabling it */ + I2C_Init(I2C_EE, &I2C_InitStructure); +} + +/** + * @brief Initializes peripherals used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void I2C_EE_Init() +{ + /* I2C Periph clock enable */ + RCC_APB1PeriphClockCmd(I2C_EE_CLK, ENABLE); + + /* GPIO Periph clock enable */ + RCC_APB2PeriphClockCmd(I2C_EE_GPIO_CLK, ENABLE); + + /* GPIO configuration */ + GPIO_Configuration(); + + /* I2C configuration */ + I2C_Configuration(); + +#if defined (EE_M24C64_32) + /* Select the EEPROM address according to the state of E0, E1, E2 pins */ + EEPROM_ADDRESS = EEPROM_HW_ADDRESS; +#elif defined (EE_M24C08) + /* depending on the EEPROM Address selected in the i2c_ee.h file */ + #ifdef EEPROM_Block0_ADDRESS + /* Select the EEPROM Block0 to write on */ + EEPROM_ADDRESS = EEPROM_Block0_ADDRESS; + #endif + + #ifdef EEPROM_Block1_ADDRESS + /* Select the EEPROM Block1 to write on */ + EEPROM_ADDRESS = EEPROM_Block1_ADDRESS; + #endif + + #ifdef EEPROM_Block2_ADDRESS + /* Select the EEPROM Block2 to write on */ + EEPROM_ADDRESS = EEPROM_Block2_ADDRESS; + #endif + + #ifdef EEPROM_Block3_ADDRESS + /* Select the EEPROM Block3 to write on */ + EEPROM_ADDRESS = EEPROM_Block3_ADDRESS; + #endif +#endif /* EE_M24C64_32 */ + +} + +/** + * @brief Writes one byte to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @retval None + */ +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr) +{ + /* Send STRAT condition */ + I2C_GenerateSTART(I2C_EE, ENABLE); + + /* Test on EV5 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_MODE_SELECT)); + + /* Send EEPROM address for write */ + I2C_Send7bitAddress(I2C_EE, EEPROM_ADDRESS, I2C_Direction_Transmitter); + + /* Test on EV6 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); + +#ifdef EE_M24C08 + + /* Send the EEPROM's internal address to write to : only one byte Address */ + I2C_SendData(I2C_EE, WriteAddr); + +#elif defined(EE_M24C64_32) + + /* Send the EEPROM's internal address to write to : MSB of the address first */ + I2C_SendData(I2C_EE, (uint8_t)((WriteAddr & 0xFF00) >> 8)); + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send the EEPROM's internal address to write to : LSB of the address */ + I2C_SendData(I2C_EE, (uint8_t)(WriteAddr & 0x00FF)); + +#endif /* EE_M24C08 */ + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send the byte to be written */ + I2C_SendData(I2C_EE, *pBuffer); + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send STOP condition */ + I2C_GenerateSTOP(I2C_EE, ENABLE); +} + +/** + * @brief Reads a block of data from the EEPROM. + * @param pBuffer : pointer to the buffer that receives the data read + * from the EEPROM. + * @param ReadAddr : EEPROM's internal address to read from. + * @param NumByteToRead : number of bytes to read from the EEPROM. + * @retval None + */ +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) +{ + /* While the bus is busy */ + while(I2C_GetFlagStatus(I2C_EE, I2C_FLAG_BUSY)); + + /* Send START condition */ + I2C_GenerateSTART(I2C_EE, ENABLE); + + /* Test on EV5 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_MODE_SELECT)); + + /* Send EEPROM address for write */ + I2C_Send7bitAddress(I2C_EE, 0x42, I2C_Direction_Transmitter); + + /* Test on EV6 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); + + /* Clear EV6 by setting again the PE bit */ + I2C_Cmd(I2C_EE, ENABLE); + +#ifdef EE_M24C08 + + /* Send the EEPROM's internal address to read from: Only one byte address */ + I2C_SendData(I2C_EE, ReadAddr); + +#elif defined (EE_M24C64_32) + + /* Send the EEPROM's internal address to read from: MSB of the address first */ + I2C_SendData(I2C_EE, (uint8_t)((ReadAddr & 0xFF00) >> 8)); + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send the EEPROM's internal address to read from: LSB of the address */ + I2C_SendData(I2C_EE, (uint8_t)(ReadAddr & 0x00FF)); + +#endif /* EE_M24C08 */ + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send STRAT condition a second time */ + I2C_GenerateSTART(I2C_EE, ENABLE); + + /* Test on EV5 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_MODE_SELECT)); + + /* Send EEPROM address for read */ + I2C_Send7bitAddress(I2C_EE, 0x42, I2C_Direction_Receiver); + + /* Test on EV6 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)); + + /* While there is data to be read */ + while(NumByteToRead) + { + if(NumByteToRead == 1) + { + /* Disable Acknowledgement */ + I2C_AcknowledgeConfig(I2C_EE, DISABLE); + + /* Send STOP Condition */ + I2C_GenerateSTOP(I2C_EE, ENABLE); + } + + /* Test on EV7 and clear it */ + if(I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_RECEIVED)) + { + /* Read a byte from the EEPROM */ + *pBuffer = I2C_ReceiveData(I2C_EE); + + /* Point to the next location where the byte read will be saved */ + pBuffer++; + + /* Decrement the read bytes counter */ + NumByteToRead--; + } + } + + /* Enable Acknowledgement to be ready for another reception */ + I2C_AcknowledgeConfig(I2C_EE, ENABLE); +} + +/** + * @brief Writes buffer of data to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; + uint16_t Addr = 0; + + Addr = WriteAddr % I2C_FLASH_PAGESIZE; + count = I2C_FLASH_PAGESIZE - Addr; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + /* If WriteAddr is I2C_FLASH_PAGESIZE aligned */ + if(Addr == 0) + { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if(NumOfPage == 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else + { + while(NumOfPage--) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + + if(NumOfSingle!=0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } + /* If WriteAddr is not I2C_FLASH_PAGESIZE aligned */ + else + { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if(NumOfPage== 0) + { + /* If the number of data to be written is more than the remaining space + in the current page: */ + if (NumByteToWrite > count) + { + /* Write the data conained in same page */ + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + + /* Write the remaining data in the following page */ + I2C_EE_PageWrite((uint8_t*)(pBuffer + count), (WriteAddr + count), (NumByteToWrite - count)); + I2C_EE_WaitEepromStandbyState(); + } + else + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + if(count != 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += count; + pBuffer += count; + } + + while(NumOfPage--) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + if(NumOfSingle != 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } +} + +/** + * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. + * @note The number of byte can't exceed the EEPROM page size. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) +{ + /* While the bus is busy */ + while(I2C_GetFlagStatus(I2C_EE, I2C_FLAG_BUSY)); + + /* Send START condition */ + I2C_GenerateSTART(I2C_EE, ENABLE); + + /* Test on EV5 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_MODE_SELECT)); + + /* Send EEPROM address for write */ + I2C_Send7bitAddress(I2C_EE, EEPROM_ADDRESS, I2C_Direction_Transmitter); + + /* Test on EV6 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); + +#ifdef EE_M24C08 + + /* Send the EEPROM's internal address to write to : only one byte Address */ + I2C_SendData(I2C_EE, WriteAddr); + +#elif defined(EE_M24C64_32) + + /* Send the EEPROM's internal address to write to : MSB of the address first */ + I2C_SendData(I2C_EE, (uint8_t)((WriteAddr & 0xFF00) >> 8)); + + /* Test on EV8 and clear it */ + while(!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* Send the EEPROM's internal address to write to : LSB of the address */ + I2C_SendData(I2C_EE, (uint8_t)(WriteAddr & 0x00FF)); + +#endif /* EE_M24C08 */ + + /* Test on EV8 and clear it */ + while(! I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + + /* While there is data to be written */ + while(NumByteToWrite--) + { + /* Send the current byte */ + I2C_SendData(I2C_EE, *pBuffer); + + /* Point to the next byte to be written */ + pBuffer++; + + /* Test on EV8 and clear it */ + while (!I2C_CheckEvent(I2C_EE, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); + } + + /* Send STOP condition */ + I2C_GenerateSTOP(I2C_EE, ENABLE); +} + +/** + * @brief Wait for EEPROM Standby state + * @param None + * @retval None + */ +void I2C_EE_WaitEepromStandbyState(void) +{ + __IO uint16_t SR1_Tmp = 0; + + do + { + /* Send START condition */ + I2C_GenerateSTART(I2C_EE, ENABLE); + + /* Read I2C_EE SR1 register to clear pending flags */ + SR1_Tmp = I2C_ReadRegister(I2C_EE, I2C_Register_SR1); + + /* Send EEPROM address for write */ + I2C_Send7bitAddress(I2C_EE, EEPROM_ADDRESS, I2C_Direction_Transmitter); + + }while(!(I2C_ReadRegister(I2C_EE, I2C_Register_SR1) & 0x0002)); + + /* Clear AF flag */ + I2C_ClearFlag(I2C_EE, I2C_FLAG_AF); + + /* STOP condition */ + I2C_GenerateSTOP(I2C_EE, ENABLE); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/src/i2c_ee.h b/cmos/gc0307/stm32/src/i2c_ee.h new file mode 100644 index 0000000..87daf05 --- /dev/null +++ b/cmos/gc0307/stm32/src/i2c_ee.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/i2c_ee.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Header for i2c_ee.c module + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __I2C_EE_H +#define __I2C_EE_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Use the defines below the choose the EEPROM type */ +//#define EE_M24C08 /* Support the device: M24C08. */ +/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and + HW address are correctly defined*/ +#define EE_M24C08 /* Support the devices: M24C32 and M24C64 */ + +/* Defines for the GPIO pins used for the I2C communication */ +#define I2C_EE I2C1 +#define I2C_EE_CLK RCC_APB1Periph_I2C1 +#define I2C_EE_GPIO GPIOB +#define I2C_EE_GPIO_CLK RCC_APB2Periph_GPIOB +#define I2C_EE_SCL GPIO_Pin_6 +#define I2C_EE_SDA GPIO_Pin_7 + +#ifdef EE_M24C64_32 +/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device + address selection (ne need for additional address lines). According to the + Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */ + + #define EEPROM_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ + +#elif defined (EE_M24C08) +/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 + EEPROM Addresses defines */ + #define EEPROM_Block0_ADDRESS 0xA0 /* E2 = 0 */ + //#define EEPROM_Block1_ADDRESS 0xA2 /* E2 = 0 */ + //#define EEPROM_Block2_ADDRESS 0xA4 /* E2 = 0 */ + //#define EEPROM_Block3_ADDRESS 0xA6 /* E2 = 0 */ + +#endif /* EE_M24C64_32 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_EE_Init(void); +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr); +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead); +void I2C_EE_WaitEepromStandbyState(void); + +#endif /* __I2C_EE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ + + diff --git a/cmos/gc0307/stm32/src/main.c b/cmos/gc0307/stm32/src/main.c new file mode 100644 index 0000000..fe3523e --- /dev/null +++ b/cmos/gc0307/stm32/src/main.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/main.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Main program body + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "i2c_ee.h" + +/** @addtogroup STM32F10x_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_EEPROM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define EEPROM_WriteAddress1 0x4 +#define EEPROM_ReadAddress1 0x00 +#define BufferSize1 (countof(Tx1_Buffer)-1) +#define BufferSize2 (countof(Tx2_Buffer)-1) +#define EEPROM_WriteAddress2 (EEPROM_WriteAddress1 + BufferSize1) +#define EEPROM_ReadAddress2 (EEPROM_ReadAddress1 + BufferSize1) + +/* Private macro -------------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +uint8_t Tx1_Buffer[] = "/* STM32F10x I2C Firmware "; +uint8_t Tx2_Buffer[] = "Library Example */"; +uint8_t Rx1_Buffer[BufferSize1], Rx2_Buffer[BufferSize2]; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; + +/* Private functions ---------------------------------------------------------*/ +void RCC_Configuration(void); +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + + + + +void I2C_GPIO_Config() +{ +GPIO_InitTypeDef GPIO_InitStructure; +RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); +GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; +GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; +GPIO_Init(GPIOB, &GPIO_InitStructure); +} + +void I2C1_Init() +{ +I2C_InitTypeDef I2C_InitStructure; +RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); +I2C_DeInit(I2C1); +I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; +I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; +I2C_InitStructure.I2C_OwnAddress1 = 0x21; +I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; +I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +I2C_InitStructure.I2C_ClockSpeed = 10000; +I2C_Init(I2C1, &I2C_InitStructure); +I2C_Cmd(I2C1, ENABLE); +} + +u8 I2C1_Read(u8 nAddr) +{ + I2C_AcknowledgeConfig(I2C1,ENABLE); //???? + I2C_GenerateSTART(I2C1,ENABLE); //??????? + while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_MODE_SELECT)){;} //??EV5 + I2C_Send7bitAddress(I2C1,0x21,I2C_Direction_Receiver); //???????? + while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)){;}//??EV6 + I2C_SendData(I2C1,nAddr);//????? + while(!I2C_CheckEvent(I2C1,I2C_Direction_Receiver)){;} //??EV8 + + I2C_GenerateSTART(I2C1,ENABLE); //??????? + while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_MODE_SELECT)){;} //??EV5 + I2C_Send7bitAddress(I2C1,0x21,I2C_Direction_Transmitter); //??????? + while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)){;} //??EV6 + I2C_AcknowledgeConfig(I2C1,DISABLE); //?????? + I2C_GenerateSTOP(I2C1,ENABLE); //??????? + while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_BYTE_RECEIVED)){;} //??EV7 + return I2C_ReceiveData(I2C1); //??????? +} + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /* System clocks configuration ---------------------------------------------*/ + RCC_Configuration(); + I2C_GPIO_Config(); + /* Initialize the I2C EEPROM driver ----------------------------------------*/ + I2C1_Init(); + + uint8_t buf = I2C1_Read(0x00); + + + while (1) + { + } +} + +/** + * @brief Configures the different system clocks. + * @param None + * @retval None + */ +void RCC_Configuration(void) +{ + /* Setup the microcontroller system. Initialize the Embedded Flash Interface, + initialize the PLL and update the SystemFrequency variable. */ + SystemInit(); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while(BufferLength--) + { + if(*pBuffer1 != *pBuffer2) + { + return FAILED; + } + + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/src/readme.txt b/cmos/gc0307/stm32/src/readme.txt new file mode 100644 index 0000000..d92087b --- /dev/null +++ b/cmos/gc0307/stm32/src/readme.txt @@ -0,0 +1,123 @@ +/** + @page I2C_EEPROM I2C_EEPROM + + @verbatim + ******************** (C) COPYRIGHT 2009 STMicroelectronics ******************* + * @file I2C/M24C08_EEPROM/readme.txt + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Description of the I2C and M24C08 EEPROM communication example. + ****************************************************************************** + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a basic example of how to use the I2C software library and +an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the +example is interfacing with M24CXX EEPROMs where XX={01, 02, 04, 08, 16, 32, 64}. + +I2C peripheral is configured in Master transmitter during write operation and in +Master receiver during read operation from I2C EEPROM. + +The peripheral used is I2C1 but can be configured by modifying the defines values +in i2c_ee.h file. The speed is set to 200kHz. + +For E24C02 to E24C16 devices, one I2C EEPROM Block address where the program will +write the buffer have to be selected from the four address available and defined +in the i2c_ee.h file. + +For E24C32 and E24C64 devices all the memory is accessible through the two-bytes +addressing mode and need to define block addresses. In this case, only the physical +address has to be defined (according to the address pins (E0,E1 and E2) connection). +This address is defined in i2c_ee.h (default is 0xA0: E0, E1 and E2 tied to ground). +The EEPROM addresses where the program start the write and the read operations +is defined in the main.c file. + +First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the +written data are read. The written and the read buffers data are then compared. +Following the read operation, the program wait that the EEPROM reverts to its +Standby state. A second write operation is, then, performed and this time, Tx2_Buffer +is written to EEPROM_WriteAddress2, which represents the address just after the last +written one in the first write. After completion of the second write operation, the +written data are read. The contents of the written and the read buffers are compared. + + +@par Directory contents + + - I2C/EEPROM/stm32f10x_conf.h Library Configuration file + - I2C/EEPROM/stm32f10x_it.c Interrupt handlers + - I2C/EEPROM/stm32f10x_it.h Interrupt handlers header file + - I2C/EEPROM/main.c Main program + - I2C/EEPROM/i2c_ee.c I2C EEPROM driver + - I2C/EEPROM/i2c_ee.h Header for the i2c_ee.c file + +@par Hardware and Software environment + + - This example runs on STM32F10x High-Density, STM32F10x Medium-Density, + STM32F10x Low-Density and STM32F10x Connectivity-Line devices. + + - This example has been tested with STM3210C-EVAL (STM32F10x Connectivity-Line) + evaluation board (implemented EEPROM is E24C64) with no additional hardware. + This example has also been tested with STMicroelectronics STM3210E-EVAL + (STM32F10x High-Density) and STM3210B-EVAL (STM32F10x Medium-Density) evaluation + boards with addition of the hardware connection listed below, and can be easily + tailored to any other supported device and development board. + + - STM3210C-EVAL Set-up + - Make sure the Jumper JP9 "I2C_SCK" is connected on the board. + - For write operations, make sure the jumper JP17 "ROM_WP" is connected on the + board (If this jumper is not connected, the EEPROM will be write-protected). + - No additional Hardware connections are needed. + + - STM3210E-EVAL, STM3210B-EVAL or any other platform Set-up + - Connect I2C1 SCL pin (PB.06) to I2C EEPROM SCL (pin6) + - Connect I2C1 SDA pin (PB.07) to I2C EEPROM SDA (pin5) + - Check that a pull-up resistor (4.7K) is connected on one I2C SDA pin + - Check that a pull-up resistor (4.7K) is connected on one I2C SCL pin + - Connect I2C EEPROM Vcc (pin8) to Vdd + - Connect I2C EEPROM Vss (pin4) to Vss + - For E24C08: Connect I2C EEPROM E2 (pin1) to Vss for E24C08 + - For E24C64/E24C32: Connect I2C EEPROM E0, E1 and E2 (pin1, pin2 and pin3) to Vss + + @note The pull-up resitors are already implemented on the STM3210B-EVAL and + STM3210E-EVAL evaluation boards. + + +@par How to use it ? + +In order to make the program work, you must do the following : +- Create a project and setup all project configuration +- Add the required Library files : + - stm32f10x_i2c.c + - stm32f10x_rcc.c + - stm32f10x_gpio.c + - system_stm32f10x.c (under Libraries\CMSIS\Core\CM3) + +- Edit stm32f10x.h file to select the device you are working on. + +@b Tip: You can tailor the provided project template to run this example, for + more details please refer to "stm32f10x_stdperiph_lib_um.chm" user + manual; select "Peripheral Examples" then follow the instructions + provided in "How to proceed" section. +- Link all compiled files and load your image into target memory +- Run the example + +@note + - Low-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 32 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - Connectivity-Line devices are STM32F105xx and STM32F107xx microcontrollers. + + *

© COPYRIGHT 2009 STMicroelectronics

+ */ diff --git a/cmos/gc0307/stm32/src/stm32f10x_conf.h b/cmos/gc0307/stm32/src/stm32f10x_conf.h new file mode 100644 index 0000000..318c889 --- /dev/null +++ b/cmos/gc0307/stm32/src/stm32f10x_conf.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32f10x_adc.h" */ +/* #include "stm32f10x_bkp.h" */ +/* #include "stm32f10x_can.h" */ +/* #include "stm32f10x_crc.h" */ +/* #include "stm32f10x_dac.h" */ +/* #include "stm32f10x_dbgmcu.h" */ +/* #include "stm32f10x_dma.h" */ +/* #include "stm32f10x_exti.h" */ +/* #include "stm32f10x_flash.h" */ +/* #include "stm32f10x_fsmc.h" */ +#include "stm32f10x_gpio.h" +#include "stm32f10x_i2c.h" +/* #include "stm32f10x_iwdg.h" */ +/* #include "stm32f10x_pwr.h" */ +#include "stm32f10x_rcc.h" +/* #include "stm32f10x_rtc.h" */ +/* #include "stm32f10x_sdio.h" */ +/* #include "stm32f10x_spi.h" */ +/* #include "stm32f10x_tim.h" */ +/* #include "stm32f10x_usart.h" */ +/* #include "stm32f10x_wwdg.h" */ +/* #include "misc.h" */ /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/src/stm32f10x_it.c b/cmos/gc0307/stm32/src/stm32f10x_it.c new file mode 100644 index 0000000..62e08e0 --- /dev/null +++ b/cmos/gc0307/stm32/src/stm32f10x_it.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f10x_it.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" + +/** @addtogroup STM32F10x_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_EEPROM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F10x Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f10x_xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cmos/gc0307/stm32/src/stm32f10x_it.h b/cmos/gc0307/stm32/src/stm32f10x_it.h new file mode 100644 index 0000000..001facc --- /dev/null +++ b/cmos/gc0307/stm32/src/stm32f10x_it.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f10x_it.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/nandflash/stm32/st_nand.uvoptx b/nandflash/stm32/st_nand.uvoptx index 3e8b3e1..9620eda 100644 --- a/nandflash/stm32/st_nand.uvoptx +++ b/nandflash/stm32/st_nand.uvoptx @@ -125,7 +125,7 @@ 0 DLGTARM - (1010=868,138,1318,695,1)(1007=105,177,292,452,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + (1010=868,138,1318,695,0)(1007=105,177,292,452,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) 0 @@ -152,9 +152,9 @@ 0 0 - 115 + 119 1 -
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+
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0 0 0 @@ -163,14 +163,14 @@ 1 .\std\main.c - \\st_nand\std/main.c\115 + \\st_nand\std/main.c\119 1 0 - 110 + 118 1 -
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+
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0 0 0 @@ -179,14 +179,14 @@ 1 .\std\main.c - \\st_nand\std/main.c\110 + \\st_nand\std/main.c\118 2 0 - 99 + 113 1 -
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+
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0 0 0 @@ -195,14 +195,62 @@ 1 .\std\main.c - \\st_nand\std/main.c\99 + \\st_nand\std/main.c\113 3 0 + 102 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + .\std\main.c + + \\st_nand\std/main.c\102 + + + 4 + 0 + 100 + 1 +
134221428
+ 0 + 0 + 0 + 0 + 0 + 1 + .\std\main.c + + \\st_nand\std/main.c\100 + + + 5 + 0 + 98 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + .\std\main.c + + \\st_nand\std/main.c\98 + + + 6 + 0 97 1 -
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+
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0 0 0 @@ -213,54 +261,6 @@ \\st_nand\std/main.c\97 - - 4 - 0 - 95 - 1 -
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- 0 - 0 - 0 - 0 - 0 - 1 - .\std\main.c - - \\st_nand\std/main.c\95 - - - 5 - 0 - 94 - 1 -
134221202
- 0 - 0 - 0 - 0 - 0 - 1 - .\std\main.c - - \\st_nand\std/main.c\94 - - - 6 - 0 - 116 - 1 -
134221362
- 0 - 0 - 0 - 0 - 0 - 1 - .\std\main.c - - \\st_nand\std/main.c\116 - 7 0 @@ -277,102 +277,6 @@ - - 8 - 0 - 98 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - - - 9 - 0 - 100 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - - - 10 - 0 - 102 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - - - 11 - 0 - 113 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - - - 12 - 0 - 118 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - - - 13 - 0 - 119 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - .\std\main.c - - - @@ -380,6 +284,11 @@ 1 RxBuffer + + 1 + 1 + get_rcc_clock + 0