From 75249c701e8c991eb875099989120bdcc98eee4d Mon Sep 17 00:00:00 2001 From: "DESKTOP-4RNDQIC\\29019" <290198252@qq.com> Date: Sat, 30 Mar 2019 20:14:46 +0800 Subject: [PATCH] =?UTF-8?q?=E6=B7=BB=E5=8A=A09g=E8=88=B5=E6=9C=BA=E4=BB=A3?= =?UTF-8?q?=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 13 +++ 9G/PWM_DeadZone/main.c | 199 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 212 insertions(+) create mode 100644 .gitignore create mode 100644 9G/PWM_DeadZone/main.c diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ac34fff --- /dev/null +++ b/.gitignore @@ -0,0 +1,13 @@ +*.i +*.uvproj +*.eww +*.ewp +*.ewd +*.d +*.29019 +*.ini +*.icf +*.lst +*.uvopt +*.htm +*.dep diff --git a/9G/PWM_DeadZone/main.c b/9G/PWM_DeadZone/main.c new file mode 100644 index 0000000..aa08179 --- /dev/null +++ b/9G/PWM_DeadZone/main.c @@ -0,0 +1,199 @@ +/**************************************************************************//** + * @file main.c + * @version V1.00 + * $Revision: 8 $ + * $Date: 15/09/02 10:04a $ + * @brief Demonstrate how to use PWM Dead Zone function. + * @note + * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#include +#include "M451Series.h" + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PLL_CLOCK 144000000 + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @brief PWM0 IRQ Handler + * + * @param None + * + * @return None + * + * @details ISR to handle PWM0 interrupt event + */ +void PWM0P0_IRQHandler(void) +{ + static uint32_t cnt; + static uint32_t out; + + // Channel 0 frequency is 100Hz, every 1 second enter this IRQ handler 100 times. + if(++cnt == 100) + { + if(out) + PWM_EnableOutput(PWM0, PWM_CH_0_MASK | PWM_CH_1_MASK | PWM_CH_2_MASK | PWM_CH_3_MASK); + else + PWM_DisableOutput(PWM0, PWM_CH_0_MASK | PWM_CH_1_MASK | PWM_CH_2_MASK | PWM_CH_3_MASK); + out ^= 1; + cnt = 0; + } + // Clear channel 0 period interrupt flag + PWM_ClearPeriodIntFlag(PWM0, 0); +} + +void SYS_Init(void) +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Enable HIRC clock (Internal RC 22.1184MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); + + /* Waiting for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); + + /* Enable HXT clock (external XTAL 12MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + + /* Waiting for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Set core clock as PLL_CLOCK from PLL */ + CLK_SetCoreClock(PLL_CLOCK); + + /* Waiting for PLL clock ready */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Enable PWM0 module clock */ + CLK_EnableModuleClock(PWM0_MODULE); + + /*---------------------------------------------------------------------------------------------------------*/ + /* PWM clock frequency configuration */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Select HCLK clock source as PLL and and HCLK clock divider as 2 */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2)); + + /* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */ + /* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */ + CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, NULL); + + /* case 2.PWM clock frequency is set double to HCLK: select PWM module clock source as PLL */ + //CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PLL, NULL); + /*---------------------------------------------------------------------------------------------------------*/ + + /* Enable UART module clock */ + CLK_EnableModuleClock(UART0_MODULE); + + /* Select UART module clock source as HXT and UART module clock divider as 1 */ + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); + + /* Reset PWM0 module */ + SYS_ResetModule(PWM0_RST); + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /*---------------------------------------------------------------------------------------------------------*/ + /* Init I/O Multi-function */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Set PD multi-function pins for UART0 RXD and TXD */ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); + + /* Set PC multi-function pins for PWM0 Channel0~3 */ + SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC0MFP_Msk)); + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0; + SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC1MFP_Msk)); + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC1MFP_PWM0_CH1; + SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC2MFP_Msk)); + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC2MFP_PWM0_CH2; + SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC3MFP_Msk)); + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC3MFP_PWM0_CH3; +} + +void UART0_Init() +{ + /*---------------------------------------------------------------------------------------------------------*/ + /* Init UART */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Reset UART module */ + SYS_ResetModule(UART0_RST); + + /* Configure UART0 and set UART0 baud rate */ + UART_Open(UART0, 115200); +} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Main Function */ +/*---------------------------------------------------------------------------------------------------------*/ +int32_t main(void) +{ + /* Init System, IP clock and multi-function I/O + In the end of SYS_Init() will issue SYS_LockReg() + to lock protected register. If user want to write + protected register, please issue SYS_UnlockReg() + to unlock protected register if necessary */ + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Init System, IP clock and multi-function I/O */ + SYS_Init(); + + /* Lock protected registers */ + SYS_LockReg(); + + /* Init UART to 115200-8n1 for print message */ + UART0_Init(); + + printf("\n\nCPU @ %dHz(PLL@ %dHz)\n", SystemCoreClock, PllClock); + printf("PWM0 clock is from %s\n", (CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk) ? "CPU" : "PLL"); + printf("+------------------------------------------------------------------------+\n"); + printf("| PWM Driver Sample Code |\n"); + printf("| |\n"); + printf("+------------------------------------------------------------------------+\n"); + printf(" This sample code will output PWM0 channel 0~3 with different\n"); + printf(" frequency and duty, enable dead zone function of all PWM0 pairs.\n"); + printf(" And also enable/disable PWM output every 1 second.\n"); + printf(" I/O configuration:\n"); + printf(" waveform output pin: PWM0_CH0(PC.0), PWM0_CH1(PC.1), PWM0_CH2(PC.2), PWM0_CH3(PC.3)\n"); + + /*Set Pwm mode as complementary mode*/ + PWM_ENABLE_COMPLEMENTARY_MODE(PWM0); + + // PWM0 channel 0 frequency is 100Hz, duty 30%, + PWM_ConfigOutputChannel(PWM0, 0, 100, 30); + SYS_UnlockReg(); + PWM_EnableDeadZone(PWM0, 0, 400); + SYS_LockReg(); + + // PWM0 channel 2 frequency is 300Hz, duty 50% + PWM_ConfigOutputChannel(PWM0, 2, 300, 50); + SYS_UnlockReg(); + PWM_EnableDeadZone(PWM0, 2, 200); + SYS_LockReg(); + + // Enable output of PWM0 channel 0~3 + PWM_EnableOutput(PWM0, 0xF); + + // Enable PWM0 channel 0 period interrupt, use channel 0 to measure time. + PWM_EnablePeriodInt(PWM0, 0, 0); + NVIC_EnableIRQ(PWM0P0_IRQn); + + // Start + PWM_Start(PWM0, 0xF); + + while(1); + +}