diff --git a/cmos/gc0307/stm32/JLinkLog.txt b/cmos/gc0307/stm32/JLinkLog.txt
index 17d2ced..e6cb244 100644
--- a/cmos/gc0307/stm32/JLinkLog.txt
+++ b/cmos/gc0307/stm32/JLinkLog.txt
@@ -1,1048 +1,306 @@
-T2244 7827:153 SEGGER J-Link V4.90 Log File (0001ms, 47849ms total)
-T2244 7827:153 DLL Compiled: Jul 28 2014 10:35:20 (0001ms, 47849ms total)
-T2244 7827:153 Logging started @ 2019-12-04 23:46 (0001ms, 47849ms total)
-T2244 7827:154 JLINK_SetWarnOutHandler(...) (0000ms, 47849ms total)
-T2244 7827:154 JLINK_OpenEx(...)
+T2DCC 98178:882 SEGGER J-Link V4.90 Log File (0000ms, 39505ms total)
+T2DCC 98178:882 DLL Compiled: Jul 28 2014 10:35:20 (0000ms, 39505ms total)
+T2DCC 98178:882 Logging started @ 2019-12-07 23:03 (0000ms, 39505ms total)
+T2DCC 98178:882 JLINK_SetWarnOutHandler(...) (0000ms, 39505ms total)
+T2DCC 98178:882 JLINK_OpenEx(...)
 Firmware: J-Link ARM V8 compiled Jan 31 2018 18:34:52
 Hardware: V8.00
 S/N: 20080643
-Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull  returns O.K. (0264ms, 48113ms total)
-T2244 7827:418 JLINK_GetEmuCaps()  returns 0xB9FF7BBF (0000ms, 48113ms total)
-T2244 7827:419 JLINK_TIF_GetAvailable(...) (0000ms, 48113ms total)
-T2244 7827:419 JLINK_SetErrorOutHandler(...) (0000ms, 48113ms total)
-T2244 7827:420 JLINK_ExecCommand("ProjectFile = "D:\project\HardwareDriver\cmos\gc0307\stm32\JLinkSettings.ini"", ...)  returns 0x00 (0000ms, 48113ms total)
-T2244 7827:420 JLINK_ExecCommand("Device = STM32F103RB", ...)Device "STM32F103RB" selected (128 KB flash, 20 KB RAM).  returns 0x00 (0001ms, 48114ms total)
-T2244 7827:421 JLINK_ExecCommand("DisableConnectionTimeout", ...)  returns 0x01 (0000ms, 48114ms total)
-T2244 7827:421 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 48114ms total)
-T2244 7827:421 JLINK_GetDLLVersion()  returns 49000 (0000ms, 48114ms total)
-T2244 7827:421 JLINK_GetFirmwareString(...) (0000ms, 48114ms total)
-T2244 7827:422 JLINK_GetDLLVersion()  returns 49000 (0000ms, 48114ms total)
-T2244 7827:422 JLINK_GetCompileDateTime() (0000ms, 48114ms total)
-T2244 7827:422 JLINK_GetFirmwareString(...) (0000ms, 48114ms total)
-T2244 7827:422 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 48114ms total)
-T2244 7827:423 JLINK_TIF_Select(JLINKARM_TIF_JTAG)  returns 0x00 (0002ms, 48116ms total)
-T2244 7827:425 JLINK_SetSpeed(5000) (0000ms, 48116ms total)
-T2244 7827:425 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG>
+Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull  returns O.K. (0273ms, 39778ms total)
+T2DCC 98179:155 JLINK_GetEmuCaps()  returns 0xB9FF7BBF (0001ms, 39779ms total)
+T2DCC 98179:156 JLINK_TIF_GetAvailable(...) (0001ms, 39780ms total)
+T2DCC 98179:157 JLINK_SetErrorOutHandler(...) (0000ms, 39780ms total)
+T2DCC 98179:157 JLINK_ExecCommand("ProjectFile = "D:\project\HardwareDriver\cmos\gc0307\stm32\JLinkSettings.ini"", ...)  returns 0x00 (0001ms, 39781ms total)
+T2DCC 98179:158 JLINK_ExecCommand("Device = STM32F103RB", ...)Device "STM32F103RB" selected (128 KB flash, 20 KB RAM).  returns 0x00 (0001ms, 39782ms total)
+T2DCC 98179:159 JLINK_ExecCommand("DisableConnectionTimeout", ...)  returns 0x01 (0000ms, 39782ms total)
+T2DCC 98179:159 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 39782ms total)
+T2DCC 98179:159 JLINK_GetDLLVersion()  returns 49000 (0000ms, 39782ms total)
+T2DCC 98179:159 JLINK_GetFirmwareString(...) (0000ms, 39782ms total)
+T2DCC 98179:160 JLINK_GetDLLVersion()  returns 49000 (0000ms, 39782ms total)
+T2DCC 98179:160 JLINK_GetCompileDateTime() (0000ms, 39782ms total)
+T2DCC 98179:161 JLINK_GetFirmwareString(...) (0000ms, 39782ms total)
+T2DCC 98179:161 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 39782ms total)
+T2DCC 98179:162 JLINK_TIF_Select(JLINKARM_TIF_JTAG)  returns 0x00 (0003ms, 39785ms total)
+T2DCC 98179:165 JLINK_SetSpeed(5000) (0000ms, 39785ms total)
+T2DCC 98179:165 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG>
 Found Cortex-M3 r1p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE00FF010)TPIU fitted. -- CPU_ReadMem(4 bytes @ 0xE00FF014) -- CPU_ReadMem(4 bytes @ 0xE00FF018) ScanLen=9 NumDevices=2 aId[0]=0x3BA00477 aIrRead[0]=0 aScanLen[0]=0
- aScanRead[0]=0 (0029ms, 48145ms total)
-T2244 7827:454 JLINK_JTAG_GetDeviceID(DeviceIndex = 0)  returns 0x3BA00477 (0000ms, 48145ms total)
-T2244 7827:454 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0)  returns 0x00 (0001ms, 48146ms total)
-T2244 7827:455 JLINK_JTAG_GetDeviceID(DeviceIndex = 1)  returns 0x16410041 (0000ms, 48146ms total)
-T2244 7827:455 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1)  returns 0x00 (0000ms, 48146ms total)
-T2244 7827:455 JLINK_GetDLLVersion()  returns 49000 (0000ms, 48146ms total)
-T2244 7827:455 JLINK_CORE_GetFound()  returns 0x30000FF (0000ms, 48146ms total)
-T2244 7827:456 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003  returns 0x00 (0000ms, 48146ms total)
-T2244 7827:456 JLINK_GetDebugInfo(0x101)  returns 0xFFFFFFFF (0000ms, 48146ms total)
-T2244 7827:456 JLINK_ReadMemEx(0xE0041FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  returns 0x10 (0001ms, 48147ms total)
-T2244 7827:457 JLINK_GetDebugInfo(0x102)  returns 0xFFFFFFFF (0000ms, 48147ms total)
-T2244 7827:457 JLINK_GetDebugInfo(0x103)  returns 0xFFFFFFFF (0000ms, 48147ms total)
-T2244 7827:457 JLINK_ReadMemEx(0xE0040FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00  returns 0x10 (0001ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x104)  returns 0xFFFFFFFF (0000ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x105)  returns 0xFFFFFFFF (0000ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x106)  returns 0xFFFFFFFF (0000ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x107)  returns 0xFFFFFFFF (0000ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x10C)  returns 0xFFFFFFFF (0000ms, 48148ms total)
-T2244 7827:458 JLINK_GetDebugInfo(0x01)  returns 0xFFFFFFFF (0001ms, 48149ms total)
-T2244 7827:459 JLINK_GetDeviceFamily()  returns 3 (0000ms, 48149ms total)
-T2244 7827:459 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41  returns 0x01 (0000ms, 48149ms total)
-T2244 7827:459 JLINK_GetDebugInfo(0x10F)  returns 0xFFFFFFFF (0001ms, 48150ms total)
-T2244 7827:460 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48150ms total)
-T2244 7827:460 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG>
- >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0027ms, 48177ms total)
-T2244 7827:487 JLINK_ReadReg(R15 (PC))  returns 0x08000188 (0000ms, 48177ms total)
-T2244 7827:487 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 48177ms total)
-T2244 7827:487 JLINK_Halt()  returns 0x00 (0000ms, 48177ms total)
-T2244 7827:487 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00  returns 0x01 (0000ms, 48177ms total)
-T2244 7827:487 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0)  returns 0x00 (0001ms, 48178ms total)
-T2244 7827:488 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)  returns 0x00 (0000ms, 48178ms total)
-T2244 7827:488 JLINK_GetHWStatus(...)  returns 0x00 (0001ms, 48179ms total)
-T2244 7827:489 JLINK_GetNumBPUnits(Type = 0xFFFFFF00)  returns 0x06 (0000ms, 48179ms total)
-T2244 7827:489 JLINK_GetNumBPUnits(Type = 0xF0)  returns 0x2000 (0000ms, 48179ms total)
-T2244 7827:489 JLINK_GetNumWPUnits()  returns 0x04 (0000ms, 48179ms total)
-T2244 7827:489 JLINK_GetSpeed()  returns 0x12C0 (0000ms, 48179ms total)
-T2244 7827:489 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0001ms, 48180ms total)
-T2244 7827:490 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0000ms, 48180ms total)
-T2244 7827:490 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., AccessWidth = 33554436) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000)  returns 0x1C (0001ms, 48181ms total)
-T2244 7827:491 JLINK_ReadReg(R15 (PC))  returns 0x08000188 (0000ms, 48181ms total)
-T2244 7827:491 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 48181ms total)
-T2244 7827:497 JLINK_ReadMemEx(0xE0001004, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00  returns 0x04 (0000ms, 48181ms total)
-T2244 7827:592 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48181ms total)
-T2244 7827:592 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028)
- -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 48209ms total)
-T2244 7827:620 JLINK_ReadReg(R15 (PC))  returns 0x08000188 (0000ms, 48209ms total)
-T2244 7827:620 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 48209ms total)
-T2244 7827:620 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000180) -- Updating C cache (128 bytes @ 0x08000180) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0002ms, 48211ms total)
-T2244 7827:622 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48  returns 0x02 (0000ms, 48211ms total)
-T2244 7827:622 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0001ms, 48212ms total)
-T2244 7827:623 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0000ms, 48212ms total)
-T2244 7827:623 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0000ms, 48212ms total)
-T2244 7827:623 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48  returns 0x02 (0000ms, 48212ms total)
-T2244 7827:786 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48212ms total)
-T2244 7827:787 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0001ms, 48213ms total)
-T2244 7830:651 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0001ms, 48214ms total)
-T2244 7830:652 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48  returns 0x02 (0000ms, 48214ms total)
-T2244 7830:652 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0000ms, 48214ms total)
-T2244 7830:652 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0000ms, 48214ms total)
-T2244 7830:652 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0000ms, 48214ms total)
-T2244 7830:652 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48  returns 0x02 (0000ms, 48214ms total)
-T2244 7831:139 JLINK_ReadReg(R0)  returns 0x00000000 (0001ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R1)  returns 0x00000003 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R2)  returns 0x40022000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R3)  returns 0x04C11DB7 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R5)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R10)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R12)  returns 0x00000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R13 (SP))  returns 0x20000678 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R14)  returns 0xFFFFFFFF (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(R15 (PC))  returns 0x08000188 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(MSP)  returns 0x20000678 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48215ms total)
-T2244 7831:140 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48  returns 0x02 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x00000001 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x00000002 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x00000003 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x00000004 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x00000005 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x00000006 (0000ms, 48215ms total)
-T3520 7831:250 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0004ms, 48219ms total)
-T3520 7831:355 JLINK_IsHalted()  returns TRUE (0003ms, 48222ms total)
-T3520 7831:358 JLINK_Halt()  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_IsHalted()  returns TRUE (0000ms, 48219ms total)
-T3520 7831:358 JLINK_IsHalted()  returns TRUE (0000ms, 48219ms total)
-T3520 7831:358 JLINK_IsHalted()  returns TRUE (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ReadReg(R15 (PC))  returns 0x080008FC (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000001)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000002)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000003)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000004)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000005)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ClrBPEx(BPHandle = 0x00000006)  returns 0x00 (0000ms, 48219ms total)
-T3520 7831:358 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 48220ms total)
-T3520 7831:359 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 48220ms total)
-T3520 7831:359 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0000ms, 48220ms total)
-T3520 7831:359 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 48221ms total)
-T3520 7831:360 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0000ms, 48221ms total)
-T3520 7831:360 JLINK_ReadReg(R0)  returns 0x20000078 (0001ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R1)  returns 0x20000278 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R2)  returns 0x20000278 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R3)  returns 0x20000278 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R12)  returns 0x20000054 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R13 (SP))  returns 0x20000678 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R14)  returns 0x08000177 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(R15 (PC))  returns 0x080008FC (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(MSP)  returns 0x20000678 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48222ms total)
-T3520 7831:361 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48222ms total)
-T2244 7831:368 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 13 14 00 00  returns 0x01 (0000ms, 48222ms total)
-T2244 7831:369 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48223ms total)
-T2244 7831:370 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0000ms, 48223ms total)
-T2244 7831:376 JLINK_ReadMemEx(0x080008FC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x080008C0) -- Updating C cache (128 bytes @ 0x080008C0) -- Read from C cache (60 bytes @ 0x080008FC) - Data: FF F7 E6 FE FF F7 FC FD FF F7 2E FD 00 20 FF F7 ...  returns 0x3C (0001ms, 48224ms total)
-T2244 7831:377 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7  returns 0x02 (0000ms, 48224ms total)
-T2244 7831:377 JLINK_ReadMemEx(0x080008FE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FE) - Data: E6 FE  returns 0x02 (0001ms, 48225ms total)
-T3520 7835:337 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7  returns 0x02 (0001ms, 48226ms total)
-T3520 7835:338 JLINK_Step() -- Read from C cache (2 bytes @ 0x080008FC) -- Read from C cache (2 bytes @ 0x080008FE) -- Simulated  returns 0x00 (0001ms, 48227ms total)
-T3520 7835:339 JLINK_ReadReg(R15 (PC))  returns 0x080006CC (0000ms, 48227ms total)
-T3520 7835:339 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x00000007 (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x00000008 (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x00000009 (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x0000000A (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x0000000B (0000ms, 48227ms total)
-T3520 7835:339 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x0000000C (0000ms, 48227ms total)
-T3520 7835:339 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48228ms total)
-T3520 7835:442 JLINK_IsHalted()  returns TRUE (0003ms, 48231ms total)
-T3520 7835:445 JLINK_Halt()  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_IsHalted()  returns TRUE (0000ms, 48228ms total)
-T3520 7835:445 JLINK_IsHalted()  returns TRUE (0000ms, 48228ms total)
-T3520 7835:445 JLINK_IsHalted()  returns TRUE (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ReadReg(R15 (PC))  returns 0x08000908 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000007)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000008)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x00000009)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000A)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000B)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ClrBPEx(BPHandle = 0x0000000C)  returns 0x00 (0000ms, 48228ms total)
-T3520 7835:445 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 48229ms total)
-T3520 7835:446 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 48229ms total)
-T3520 7835:446 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0002ms, 48231ms total)
-T3520 7835:448 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R0)  returns 0x00002710 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R1)  returns 0xBFFF0000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R2)  returns 0x04000021 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R3)  returns 0x1C034000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R13 (SP))  returns 0x20000678 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R14)  returns 0x080003AD (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(R15 (PC))  returns 0x08000908 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(MSP)  returns 0x20000678 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48231ms total)
-T3520 7835:448 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48231ms total)
-T2244 7835:448 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 7A 1F 00 00  returns 0x01 (0001ms, 48232ms total)
-T2244 7835:449 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48233ms total)
-T2244 7835:450 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0002ms, 48235ms total)
-T2244 7835:482 JLINK_ReadMemEx(0x08000908, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000900) -- Updating C cache (128 bytes @ 0x08000900) -- Read from C cache (60 bytes @ 0x08000908) - Data: 00 20 FF F7 53 FD 00 BF FE E7 00 00 34 09 00 08 ...  returns 0x3C (0002ms, 48237ms total)
-T2244 7835:484 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20  returns 0x02 (0000ms, 48237ms total)
-T2244 7835:484 JLINK_ReadMemEx(0x0800090A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800090A) - Data: FF F7  returns 0x02 (0000ms, 48237ms total)
-T3520 7835:959 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20  returns 0x02 (0000ms, 48237ms total)
-T3520 7835:959 JLINK_Step() -- Read from C cache (2 bytes @ 0x08000908) -- Simulated  returns 0x00 (0001ms, 48238ms total)
-T3520 7835:960 JLINK_ReadReg(R15 (PC))  returns 0x0800090A (0000ms, 48238ms total)
-T3520 7835:960 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x0000000D (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x0000000E (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x0000000F (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x00000010 (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x00000011 (0000ms, 48238ms total)
-T3520 7835:960 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x00000012 (0000ms, 48238ms total)
-T3520 7835:960 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48239ms total)
-T3520 7836:062 JLINK_IsHalted()  returns TRUE (0003ms, 48242ms total)
-T3520 7836:065 JLINK_Halt()  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_IsHalted()  returns TRUE (0000ms, 48239ms total)
-T3520 7836:065 JLINK_IsHalted()  returns TRUE (0000ms, 48239ms total)
-T3520 7836:065 JLINK_IsHalted()  returns TRUE (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ReadReg(R15 (PC))  returns 0x080003D6 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000D)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000E)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x0000000F)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000010)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000011)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ClrBPEx(BPHandle = 0x00000012)  returns 0x00 (0000ms, 48239ms total)
-T3520 7836:065 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 48240ms total)
-T3520 7836:066 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0001ms, 48241ms total)
-T3520 7836:067 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0000ms, 48241ms total)
-T3520 7836:067 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 48242ms total)
-T3520 7836:068 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R0)  returns 0x00000001 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R1)  returns 0x00030001 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R2)  returns 0x40005400 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R3)  returns 0x00030000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R13 (SP))  returns 0x20000670 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R14)  returns 0x080003D3 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(R15 (PC))  returns 0x080003D6 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(MSP)  returns 0x20000670 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48243ms total)
-T3520 7836:069 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48243ms total)
-T2244 7836:069 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0001ms, 48244ms total)
-T2244 7836:070 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00  returns 0x04 (0000ms, 48244ms total)
-T2244 7836:070 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0000ms, 48244ms total)
-T2244 7836:078 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 2E 00 00  returns 0x01 (0000ms, 48244ms total)
-T2244 7836:079 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48245ms total)
-T2244 7836:080 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48245ms total)
-T2244 7836:099 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22  returns 0x02 (0001ms, 48246ms total)
-T2244 7836:100 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0002ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ...  returns 0x3C (0000ms, 48248ms total)
-T2244 7836:102 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0  returns 0x02 (0000ms, 48248ms total)
-T3520 7836:908 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22  returns 0x02 (0002ms, 48250ms total)
-T3520 7836:910 JLINK_Step() -- Read from C cache (2 bytes @ 0x080003D6) -- Simulated  returns 0x00 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_ReadReg(R15 (PC))  returns 0x080003D8 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x00000013 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x00000014 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x00000015 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x00000016 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x00000017 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x00000018 (0000ms, 48250ms total)
-T3520 7836:910 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0002ms, 48252ms total)
-T3520 7837:014 JLINK_IsHalted()  returns FALSE (0000ms, 48252ms total)
-T3520 7837:114 JLINK_IsHalted()  returns FALSE (0000ms, 48252ms total)
-T3520 7837:215 JLINK_IsHalted()  returns FALSE (0000ms, 48252ms total)
-T3520 7837:316 JLINK_IsHalted()  returns FALSE (0000ms, 48252ms total)
-T3520 7837:417 JLINK_IsHalted()  returns FALSE (0000ms, 48252ms total)
-T3520 7837:518 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F6 9E 99 02  returns 0x01 (0000ms, 48252ms total)
-T2244 7837:519 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48252ms total)
-T2244 7837:519 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48253ms total)
-T3520 7837:540 JLINK_IsHalted()  returns FALSE (0000ms, 48253ms total)
-T3520 7837:641 JLINK_IsHalted()  returns FALSE (0000ms, 48253ms total)
-T3520 7837:742 JLINK_IsHalted()  returns FALSE (0000ms, 48253ms total)
-T3520 7837:843 JLINK_IsHalted()  returns FALSE (0000ms, 48253ms total)
-T3520 7837:945 JLINK_IsHalted()  returns FALSE (0001ms, 48254ms total)
-T3520 7838:046 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 87 9A DD 04  returns 0x01 (0000ms, 48253ms total)
-T2244 7838:047 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48254ms total)
-T2244 7838:048 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48254ms total)
-T3520 7838:052 JLINK_IsHalted()  returns FALSE (0000ms, 48254ms total)
-T3520 7838:153 JLINK_IsHalted()  returns FALSE (0000ms, 48254ms total)
-T3520 7838:254 JLINK_IsHalted()  returns FALSE (0000ms, 48254ms total)
-T3520 7838:355 JLINK_IsHalted()  returns FALSE (0000ms, 48254ms total)
-T3520 7838:456 JLINK_IsHalted()  returns FALSE (0000ms, 48254ms total)
-T3520 7838:557 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 51 8B 0F 07  returns 0x01 (0000ms, 48254ms total)
-T2244 7838:560 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0002ms, 48256ms total)
-T2244 7838:562 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48257ms total)
-T3520 7838:568 JLINK_IsHalted()  returns FALSE (0000ms, 48257ms total)
-T3520 7838:669 JLINK_IsHalted()  returns FALSE (0000ms, 48257ms total)
-T3520 7838:769 JLINK_IsHalted()  returns FALSE (0000ms, 48257ms total)
-T3520 7838:870 JLINK_IsHalted()  returns FALSE (0000ms, 48257ms total)
-T3520 7838:971 JLINK_IsHalted()  returns FALSE (0000ms, 48257ms total)
-T3520 7839:072 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 75 A6 45 09  returns 0x01 (0000ms, 48257ms total)
-T2244 7839:073 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48258ms total)
-T2244 7839:074 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48258ms total)
-T3520 7839:081 JLINK_IsHalted()  returns FALSE (0001ms, 48259ms total)
-T3520 7839:183 JLINK_IsHalted()  returns FALSE (0000ms, 48258ms total)
-T3520 7839:284 JLINK_IsHalted()  returns FALSE (0001ms, 48259ms total)
-T3520 7839:385 JLINK_IsHalted()  returns FALSE (0001ms, 48259ms total)
-T3520 7839:486 JLINK_IsHalted()  returns FALSE (0001ms, 48259ms total)
-T3520 7839:588 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: CF 04 7C 0B  returns 0x01 (0000ms, 48258ms total)
-T2244 7839:595 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48259ms total)
-T2244 7839:596 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48260ms total)
-T3520 7839:602 JLINK_IsHalted()  returns FALSE (0001ms, 48261ms total)
-T3520 7839:704 JLINK_IsHalted()  returns FALSE (0000ms, 48260ms total)
-T3520 7839:805 JLINK_IsHalted()  returns FALSE (0000ms, 48260ms total)
-T3520 7839:906 JLINK_IsHalted()  returns FALSE (0000ms, 48260ms total)
-T3520 7840:008 JLINK_IsHalted()  returns FALSE (0001ms, 48261ms total)
-T3520 7840:110 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: BC AB B9 0D  returns 0x01 (0000ms, 48260ms total)
-T2244 7840:112 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48261ms total)
-T2244 7840:113 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48262ms total)
-T3520 7840:120 JLINK_IsHalted()  returns FALSE (0001ms, 48263ms total)
-T3520 7840:221 JLINK_IsHalted()  returns FALSE (0000ms, 48262ms total)
-T3520 7840:322 JLINK_IsHalted()  returns FALSE (0000ms, 48262ms total)
-T3520 7840:423 JLINK_IsHalted()  returns FALSE (0000ms, 48262ms total)
-T3520 7840:525 JLINK_IsHalted()  returns FALSE (0000ms, 48262ms total)
-T3520 7840:626 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: E3 90 F0 0F  returns 0x01 (0000ms, 48262ms total)
-T2244 7840:629 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48263ms total)
-T2244 7840:630 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48264ms total)
-T3520 7840:638 JLINK_IsHalted()  returns FALSE (0000ms, 48264ms total)
-T3520 7840:739 JLINK_IsHalted()  returns FALSE (0000ms, 48264ms total)
-T3520 7840:840 JLINK_IsHalted()  returns FALSE (0000ms, 48264ms total)
-T3520 7840:941 JLINK_IsHalted()  returns FALSE (0000ms, 48264ms total)
-T3520 7841:042 JLINK_IsHalted()  returns FALSE (0000ms, 48264ms total)
-T3520 7841:144 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F0 4C 29 12  returns 0x01 (0000ms, 48264ms total)
-T2244 7841:144 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48265ms total)
-T2244 7841:145 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48265ms total)
-T3520 7841:152 JLINK_IsHalted()  returns FALSE (0001ms, 48266ms total)
-T3520 7841:255 JLINK_IsHalted()  returns FALSE (0000ms, 48265ms total)
-T3520 7841:356 JLINK_IsHalted()  returns FALSE (0000ms, 48265ms total)
-T3520 7841:457 JLINK_IsHalted()  returns FALSE (0000ms, 48265ms total)
-T3520 7841:558 JLINK_IsHalted()  returns FALSE (0000ms, 48265ms total)
-T3520 7841:659 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 3F DC 5F 14  returns 0x01 (0000ms, 48265ms total)
-T2244 7841:659 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48266ms total)
-T2244 7841:660 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48267ms total)
-T3520 7841:665 JLINK_IsHalted()  returns FALSE (0001ms, 48268ms total)
-T3520 7841:767 JLINK_IsHalted()  returns FALSE (0000ms, 48267ms total)
-T3520 7841:868 JLINK_IsHalted()  returns FALSE (0000ms, 48267ms total)
-T3520 7841:969 JLINK_IsHalted()  returns FALSE (0001ms, 48268ms total)
-T3520 7842:071 JLINK_IsHalted()  returns FALSE (0001ms, 48268ms total)
-T3520 7842:172 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 2C 2D 93 16  returns 0x01 (0000ms, 48267ms total)
-T2244 7842:176 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0002ms, 48269ms total)
-T2244 7842:178 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48269ms total)
-T3520 7842:188 JLINK_IsHalted()  returns FALSE (0001ms, 48270ms total)
-T3520 7842:290 JLINK_IsHalted()  returns FALSE (0000ms, 48269ms total)
-T3520 7842:391 JLINK_IsHalted()  returns FALSE (0000ms, 48269ms total)
-T3520 7842:491 JLINK_IsHalted()  returns FALSE (0000ms, 48269ms total)
-T3520 7842:592 JLINK_IsHalted()  returns FALSE (0000ms, 48269ms total)
-T3520 7842:693 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 23 80 CF 18  returns 0x01 (0000ms, 48269ms total)
-T2244 7842:693 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48270ms total)
-T2244 7842:694 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48271ms total)
-T3520 7842:698 JLINK_IsHalted()  returns FALSE (0001ms, 48272ms total)
-T3520 7842:800 JLINK_IsHalted()  returns FALSE (0000ms, 48271ms total)
-T3520 7842:900 JLINK_IsHalted()  returns FALSE (0000ms, 48271ms total)
-T3520 7843:001 JLINK_IsHalted()  returns FALSE (0000ms, 48271ms total)
-T3520 7843:102 JLINK_IsHalted()  returns FALSE (0001ms, 48272ms total)
-T3520 7843:204 JLINK_IsHalted()  returns FALSE (0000ms, 48271ms total)
-T3520 7843:305 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 1E 9A 6F 1B  returns 0x01 (0000ms, 48271ms total)
-T2244 7843:305 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48272ms total)
-T2244 7843:306 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48272ms total)
-T3520 7843:310 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:411 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:513 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:613 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:714 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:816 JLINK_IsHalted()  returns FALSE (0000ms, 48272ms total)
-T3520 7843:917 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: DD D1 10 1E  returns 0x01 (0001ms, 48273ms total)
-T2244 7843:920 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48274ms total)
-T2244 7843:921 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48275ms total)
-T3520 7843:930 JLINK_IsHalted()  returns FALSE (0000ms, 48275ms total)
-T3520 7844:031 JLINK_Halt()  returns 0x00 (0003ms, 48278ms total)
-T3520 7844:034 JLINK_IsHalted()  returns TRUE (0000ms, 48278ms total)
-T3520 7844:034 JLINK_IsHalted()  returns TRUE (0000ms, 48278ms total)
-T3520 7844:034 JLINK_IsHalted()  returns TRUE (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ReadReg(R15 (PC))  returns 0x0800048A (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000013)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000014)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000015)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000016)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000017)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ClrBPEx(BPHandle = 0x00000018)  returns 0x00 (0000ms, 48278ms total)
-T3520 7844:034 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 01 00 00 00  returns 0x01 (0001ms, 48279ms total)
-T3520 7844:035 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0001ms, 48280ms total)
-T3520 7844:036 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0000ms, 48280ms total)
-T3520 7844:036 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 48281ms total)
-T3520 7844:037 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R0)  returns 0x40005400 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R1)  returns 0x00070082 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R2)  returns 0x40005400 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R3)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R5)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R13 (SP))  returns 0x20000660 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R14)  returns 0x080003EB (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(R15 (PC))  returns 0x0800048A (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(MSP)  returns 0x20000660 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48282ms total)
-T3520 7844:038 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48282ms total)
-T2244 7844:039 JLINK_ReadMemEx(0x2000066C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x2000066C) - Data: EB 03 00 08  returns 0x04 (0000ms, 48282ms total)
-T2244 7844:039 JLINK_ReadMemEx(0x20000660, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000660, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000660, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000660) - Data: 00 00 00 00  returns 0x04 (0001ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x20000664, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000664, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000664, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000664) - Data: 14 00 00 20  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x20000668, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000668, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000668, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000668) - Data: 00 00 00 00  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x2000066C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x2000066C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x2000066C) - Data: EB 03 00 08  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:040 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0000ms, 48283ms total)
-T2244 7844:054 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: AA 5D 8D 1E  returns 0x01 (0000ms, 48283ms total)
-T2244 7844:055 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48284ms total)
-T2244 7844:056 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48284ms total)
-T2244 7844:593 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 48284ms total)
-T2244 7844:593 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028)
- -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R15 (PC))  returns 0x08000188 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R0)  returns 0x40005400 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R1)  returns 0x00070082 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R2)  returns 0x40005400 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R3)  returns 0x00000000 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48312ms total)
-T2244 7844:621 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 04 65 8D 1E  returns 0x01 (0001ms, 48313ms total)
-T2244 7844:624 JLINK_ReadMemEx(0x08000188, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000180) -- Updating C cache (128 bytes @ 0x08000180) -- Read from C cache (60 bytes @ 0x08000188) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0001ms, 48314ms total)
-T2244 7844:625 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48  returns 0x02 (0001ms, 48315ms total)
-T2244 7844:626 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0000ms, 48315ms total)
-T2244 7844:626 JLINK_ReadMemEx(0x0800018A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018A) - Data: 80 47  returns 0x02 (0000ms, 48315ms total)
-T2244 7844:626 JLINK_ReadMemEx(0x0800018C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800018C) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0000ms, 48315ms total)
-T2244 7844:626 JLINK_ReadMemEx(0x0800018C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800018C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800018C) - Data: 09 48  returns 0x02 (0000ms, 48315ms total)
-T3520 7845:320 JLINK_ReadMemEx(0x08000188, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000188, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000188) - Data: 09 48  returns 0x02 (0001ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x00000019 (0000ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x0000001A (0000ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x0000001B (0000ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x0000001C (0000ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x0000001D (0000ms, 48316ms total)
-T3520 7845:321 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x0000001E (0000ms, 48316ms total)
-T3520 7845:321 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0003ms, 48319ms total)
-T3520 7845:425 JLINK_IsHalted()  returns TRUE (0003ms, 48322ms total)
-T3520 7845:428 JLINK_Halt()  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_IsHalted()  returns TRUE (0000ms, 48319ms total)
-T3520 7845:428 JLINK_IsHalted()  returns TRUE (0000ms, 48319ms total)
-T3520 7845:428 JLINK_IsHalted()  returns TRUE (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ReadReg(R15 (PC))  returns 0x080008FC (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x00000019)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001A)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001B)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001C)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001D)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ClrBPEx(BPHandle = 0x0000001E)  returns 0x00 (0000ms, 48319ms total)
-T3520 7845:428 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 48320ms total)
-T3520 7845:429 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0001ms, 48321ms total)
-T3520 7845:430 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0000ms, 48321ms total)
-T3520 7845:430 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 48322ms total)
-T3520 7845:431 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R0)  returns 0x20000078 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R1)  returns 0x20000278 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R2)  returns 0x20000278 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R3)  returns 0x20000278 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R12)  returns 0x20000054 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R13 (SP))  returns 0x20000678 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R14)  returns 0x08000177 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(R15 (PC))  returns 0x080008FC (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(MSP)  returns 0x20000678 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48323ms total)
-T3520 7845:432 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48323ms total)
-T2244 7845:441 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 29 14 00 00  returns 0x01 (0001ms, 48324ms total)
-T2244 7845:442 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48325ms total)
-T2244 7845:443 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0001ms, 48326ms total)
-T2244 7845:488 JLINK_ReadMemEx(0x080008FC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x080008C0) -- Updating C cache (128 bytes @ 0x080008C0) -- Read from C cache (60 bytes @ 0x080008FC) - Data: FF F7 E6 FE FF F7 FC FD FF F7 2E FD 00 20 FF F7 ...  returns 0x3C (0002ms, 48328ms total)
-T2244 7845:490 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7  returns 0x02 (0000ms, 48328ms total)
-T2244 7845:490 JLINK_ReadMemEx(0x080008FE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FE) - Data: E6 FE  returns 0x02 (0000ms, 48328ms total)
-T3520 7846:208 JLINK_ReadMemEx(0x080008FC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080008FC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080008FC) - Data: FF F7  returns 0x02 (0001ms, 48329ms total)
-T3520 7846:209 JLINK_Step() -- Read from C cache (2 bytes @ 0x080008FC) -- Read from C cache (2 bytes @ 0x080008FE) -- Simulated  returns 0x00 (0001ms, 48330ms total)
-T3520 7846:210 JLINK_ReadReg(R15 (PC))  returns 0x080006CC (0000ms, 48330ms total)
-T3520 7846:210 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x0000001F (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x00000020 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x00000021 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x00000022 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x00000023 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x00000024 (0000ms, 48330ms total)
-T3520 7846:210 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0000ms, 48330ms total)
-T3520 7846:312 JLINK_IsHalted()  returns TRUE (0003ms, 48333ms total)
-T3520 7846:315 JLINK_Halt()  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_IsHalted()  returns TRUE (0000ms, 48330ms total)
-T3520 7846:315 JLINK_IsHalted()  returns TRUE (0000ms, 48330ms total)
-T3520 7846:315 JLINK_IsHalted()  returns TRUE (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ReadReg(R15 (PC))  returns 0x08000908 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x0000001F)  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000020)  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000021)  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000022)  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000023)  returns 0x00 (0000ms, 48330ms total)
-T3520 7846:315 JLINK_ClrBPEx(BPHandle = 0x00000024)  returns 0x00 (0001ms, 48331ms total)
-T3520 7846:316 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0000ms, 48331ms total)
-T3520 7846:316 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0001ms, 48332ms total)
-T3520 7846:317 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0000ms, 48332ms total)
-T3520 7846:317 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 48333ms total)
-T3520 7846:318 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R0)  returns 0x00002710 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R1)  returns 0xBFFF0000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R2)  returns 0x04000021 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R3)  returns 0x1C034000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R13 (SP))  returns 0x20000678 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R14)  returns 0x080003AD (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(R15 (PC))  returns 0x08000908 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(MSP)  returns 0x20000678 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48334ms total)
-T3520 7846:319 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48334ms total)
-T2244 7846:319 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 90 1F 00 00  returns 0x01 (0001ms, 48335ms total)
-T2244 7846:320 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48336ms total)
-T2244 7846:321 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48337ms total)
-T2244 7846:353 JLINK_ReadMemEx(0x08000908, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000900) -- Updating C cache (128 bytes @ 0x08000900) -- Read from C cache (60 bytes @ 0x08000908) - Data: 00 20 FF F7 53 FD 00 BF FE E7 00 00 34 09 00 08 ...  returns 0x3C (0002ms, 48339ms total)
-T2244 7846:355 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20  returns 0x02 (0000ms, 48339ms total)
-T2244 7846:355 JLINK_ReadMemEx(0x0800090A, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x0800090A, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800090A) - Data: FF F7  returns 0x02 (0000ms, 48339ms total)
-T3520 7846:976 JLINK_ReadMemEx(0x08000908, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x08000908, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000908) - Data: 00 20  returns 0x02 (0000ms, 48339ms total)
-T3520 7846:976 JLINK_Step() -- Read from C cache (2 bytes @ 0x08000908) -- Simulated  returns 0x00 (0001ms, 48340ms total)
-T3520 7846:977 JLINK_ReadReg(R15 (PC))  returns 0x0800090A (0000ms, 48340ms total)
-T3520 7846:977 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x00000025 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x00000026 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x00000027 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x00000028 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x00000029 (0000ms, 48340ms total)
-T3520 7846:977 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x0000002A (0000ms, 48340ms total)
-T3520 7846:977 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0002ms, 48342ms total)
-T3520 7847:079 JLINK_IsHalted()  returns TRUE (0003ms, 48345ms total)
-T3520 7847:082 JLINK_Halt()  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_IsHalted()  returns TRUE (0000ms, 48342ms total)
-T3520 7847:082 JLINK_IsHalted()  returns TRUE (0000ms, 48342ms total)
-T3520 7847:082 JLINK_IsHalted()  returns TRUE (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ReadReg(R15 (PC))  returns 0x080003D6 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000025)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000026)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000027)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000028)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x00000029)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ClrBPEx(BPHandle = 0x0000002A)  returns 0x00 (0000ms, 48342ms total)
-T3520 7847:082 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 48343ms total)
-T3520 7847:083 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0001ms, 48344ms total)
-T3520 7847:084 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0001ms, 48345ms total)
-T3520 7847:085 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0000ms, 48345ms total)
-T3520 7847:085 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R0)  returns 0x00000001 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R1)  returns 0x00030001 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R2)  returns 0x40005400 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R3)  returns 0x00030000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R13 (SP))  returns 0x20000670 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R14)  returns 0x080003D3 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(R15 (PC))  returns 0x080003D6 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(MSP)  returns 0x20000670 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48346ms total)
-T3520 7847:086 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48346ms total)
-T2244 7847:087 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0002ms, 48348ms total)
-T2244 7847:089 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00  returns 0x04 (0000ms, 48348ms total)
-T2244 7847:089 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0000ms, 48348ms total)
-T2244 7847:097 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 16 2E 00 00  returns 0x01 (0001ms, 48349ms total)
-T2244 7847:098 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48350ms total)
-T2244 7847:099 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48351ms total)
-T2244 7847:119 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22  returns 0x02 (0002ms, 48353ms total)
-T2244 7847:121 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0001ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ...  returns 0x3C (0000ms, 48354ms total)
-T2244 7847:122 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0  returns 0x02 (0000ms, 48354ms total)
-T3520 7852:025 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22  returns 0x02 (0001ms, 48355ms total)
-T3520 7852:026 JLINK_Step() -- Read from C cache (2 bytes @ 0x080003D6) -- Simulated  returns 0x00 (0000ms, 48355ms total)
-T3520 7852:027 JLINK_ReadReg(R15 (PC))  returns 0x080003D8 (0000ms, 48356ms total)
-T3520 7852:027 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x0800090E, Type = 0xFFFFFFF2)  returns 0x0000002B (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x08000908, Type = 0xFFFFFFF2)  returns 0x0000002C (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x080008FC, Type = 0xFFFFFFF2)  returns 0x0000002D (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x08000404, Type = 0xFFFFFFF2)  returns 0x0000002E (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x080003EE, Type = 0xFFFFFFF2)  returns 0x0000002F (0000ms, 48356ms total)
-T3520 7852:027 JLINK_SetBPEx(Addr = 0x080003D6, Type = 0xFFFFFFF2)  returns 0x00000030 (0000ms, 48356ms total)
-T3520 7852:027 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0001ms, 48357ms total)
-T3520 7852:129 JLINK_IsHalted()  returns FALSE (0000ms, 48357ms total)
-T3520 7852:231 JLINK_IsHalted()  returns FALSE (0000ms, 48357ms total)
-T3520 7852:332 JLINK_IsHalted()  returns FALSE (0000ms, 48357ms total)
-T3520 7852:433 JLINK_IsHalted()  returns FALSE (0000ms, 48357ms total)
-T3520 7852:534 JLINK_IsHalted()  returns FALSE (0000ms, 48357ms total)
-T3520 7852:636 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: EF 6B 9B 02  returns 0x01 (0000ms, 48357ms total)
-T2244 7852:637 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48357ms total)
-T2244 7852:637 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48358ms total)
-T3520 7852:655 JLINK_IsHalted()  returns FALSE (0000ms, 48358ms total)
-T3520 7852:756 JLINK_IsHalted()  returns FALSE (0000ms, 48358ms total)
-T3520 7852:858 JLINK_IsHalted()  returns FALSE (0000ms, 48358ms total)
-T3520 7852:959 JLINK_IsHalted()  returns FALSE (0000ms, 48358ms total)
-T3520 7853:060 JLINK_IsHalted()  returns FALSE (0000ms, 48358ms total)
-T3520 7853:162 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9E 69 DD 04  returns 0x01 (0000ms, 48358ms total)
-T2244 7853:162 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48358ms total)
-T2244 7853:162 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48359ms total)
-T3520 7853:168 JLINK_IsHalted()  returns FALSE (0001ms, 48360ms total)
-T3520 7853:269 JLINK_IsHalted()  returns FALSE (0000ms, 48359ms total)
-T3520 7853:370 JLINK_IsHalted()  returns FALSE (0000ms, 48359ms total)
-T3520 7853:471 JLINK_IsHalted()  returns FALSE (0000ms, 48359ms total)
-T3520 7853:571 JLINK_IsHalted()  returns FALSE (0000ms, 48359ms total)
-T3520 7853:673 JLINK_IsHalted()  returns FALSE (0000ms, 48359ms total)
-T3520 7853:774 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: C1 08 7E 07  returns 0x01 (0000ms, 48359ms total)
-T2244 7853:776 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48360ms total)
-T2244 7853:777 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48360ms total)
-T3520 7853:786 JLINK_IsHalted()  returns FALSE (0000ms, 48360ms total)
-T3520 7853:888 JLINK_IsHalted()  returns FALSE (0000ms, 48360ms total)
-T3520 7853:989 JLINK_IsHalted()  returns FALSE (0000ms, 48360ms total)
-T3520 7854:090 JLINK_IsHalted()  returns FALSE (0000ms, 48360ms total)
-T3520 7854:191 JLINK_IsHalted()  returns FALSE (0000ms, 48360ms total)
-T3520 7854:291 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: DE A0 B6 09  returns 0x01 (0000ms, 48360ms total)
-T2244 7854:294 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48361ms total)
-T2244 7854:295 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48362ms total)
-T3520 7854:301 JLINK_IsHalted()  returns FALSE (0001ms, 48363ms total)
-T3520 7854:403 JLINK_IsHalted()  returns FALSE (0000ms, 48362ms total)
-T3520 7854:504 JLINK_IsHalted()  returns FALSE (0000ms, 48362ms total)
-T3520 7854:605 JLINK_IsHalted()  returns FALSE (0000ms, 48362ms total)
-T3520 7854:706 JLINK_IsHalted()  returns FALSE (0000ms, 48362ms total)
-T3520 7854:807 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 35 71 ED 0B  returns 0x01 (0000ms, 48362ms total)
-T2244 7854:810 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48363ms total)
-T2244 7854:811 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48364ms total)
-T3520 7854:816 JLINK_IsHalted()  returns FALSE (0000ms, 48364ms total)
-T3520 7854:917 JLINK_IsHalted()  returns FALSE (0000ms, 48364ms total)
-T3520 7855:018 JLINK_IsHalted()  returns FALSE (0000ms, 48364ms total)
-T3520 7855:120 JLINK_IsHalted()  returns FALSE (0000ms, 48364ms total)
-T3520 7855:221 JLINK_IsHalted()  returns FALSE (0000ms, 48364ms total)
-T3520 7855:322 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 76 CF 22 0E  returns 0x01 (0001ms, 48365ms total)
-T2244 7855:323 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48366ms total)
-T2244 7855:324 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48366ms total)
-T3520 7855:328 JLINK_IsHalted()  returns FALSE (0001ms, 48367ms total)
-T3520 7855:429 JLINK_IsHalted()  returns FALSE (0000ms, 48366ms total)
-T3520 7855:530 JLINK_IsHalted()  returns FALSE (0000ms, 48366ms total)
-T2244 7855:576 JLINK_ReadMemEx(0x080003E0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E0) - Data: 00 BF  returns 0x02 (0000ms, 48366ms total)
-T2244 7855:576 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E2) - Data: 20 49  returns 0x02 (0001ms, 48367ms total)
-T2244 7855:577 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E2) - Data: 20 49  returns 0x02 (0000ms, 48367ms total)
-T2244 7855:577 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E4) - Data: 1D 48  returns 0x02 (0001ms, 48368ms total)
-T2244 7855:578 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E4) - Data: 1D 48  returns 0x02 (0001ms, 48369ms total)
-T2244 7855:579 JLINK_ReadMemEx(0x080003E6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU is running -- CPU_ReadMem(2 bytes @ 0x080003E6) - Data: 00 F0  returns 0x02 (0000ms, 48369ms total)
-T3520 7855:631 JLINK_IsHalted()  returns FALSE (0000ms, 48369ms total)
-T3520 7855:732 JLINK_IsHalted()  returns FALSE (0000ms, 48369ms total)
-T3520 7855:834 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 3E 36 55 10  returns 0x01 (0000ms, 48369ms total)
-T2244 7855:835 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48369ms total)
-T2244 7855:835 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48370ms total)
-T3520 7855:842 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7855:943 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7856:044 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7856:146 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7856:247 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7856:348 JLINK_IsHalted()  returns FALSE (0000ms, 48370ms total)
-T3520 7856:449 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 73 B0 F8 12  returns 0x01 (0000ms, 48370ms total)
-T2244 7856:449 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48371ms total)
-T2244 7856:450 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48372ms total)
-T3520 7856:455 JLINK_IsHalted()  returns FALSE (0001ms, 48373ms total)
-T3520 7856:556 JLINK_IsHalted()  returns FALSE (0000ms, 48372ms total)
-T3520 7856:657 JLINK_IsHalted()  returns FALSE (0000ms, 48372ms total)
-T3520 7856:758 JLINK_IsHalted()  returns FALSE (0000ms, 48372ms total)
-T3520 7856:860 JLINK_IsHalted()  returns FALSE (0000ms, 48372ms total)
-T3520 7856:962 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 42 64 2C 15  returns 0x01 (0000ms, 48372ms total)
-T2244 7856:972 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48373ms total)
-T2244 7856:973 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48374ms total)
-T3520 7856:980 JLINK_IsHalted()  returns FALSE (0000ms, 48374ms total)
-T3520 7857:081 JLINK_IsHalted()  returns FALSE (0000ms, 48374ms total)
-T3520 7857:182 JLINK_IsHalted()  returns FALSE (0000ms, 48374ms total)
-T3520 7857:283 JLINK_IsHalted()  returns FALSE (0000ms, 48374ms total)
-T3520 7857:383 JLINK_IsHalted()  returns FALSE (0000ms, 48374ms total)
-T3520 7857:484 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 16 A1 6A 17  returns 0x01 (0001ms, 48375ms total)
-T2244 7857:495 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48376ms total)
-T2244 7857:496 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48377ms total)
-T3520 7857:502 JLINK_IsHalted()  returns FALSE (0000ms, 48377ms total)
-T3520 7857:603 JLINK_IsHalted()  returns FALSE (0000ms, 48377ms total)
-T3520 7857:704 JLINK_IsHalted()  returns FALSE (0000ms, 48377ms total)
-T3520 7857:806 JLINK_IsHalted()  returns FALSE (0000ms, 48377ms total)
-T3520 7857:907 JLINK_IsHalted()  returns FALSE (0000ms, 48377ms total)
-T3520 7858:008 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: C8 DC A9 19  returns 0x01 (0001ms, 48378ms total)
-T2244 7858:009 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48379ms total)
-T2244 7858:010 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48379ms total)
-T3520 7858:015 JLINK_IsHalted()  returns FALSE (0001ms, 48380ms total)
-T3520 7858:117 JLINK_IsHalted()  returns FALSE (0000ms, 48379ms total)
-T3520 7858:219 JLINK_IsHalted()  returns FALSE (0000ms, 48379ms total)
-T3520 7858:320 JLINK_IsHalted()  returns FALSE (0000ms, 48379ms total)
-T3520 7858:421 JLINK_IsHalted()  returns FALSE (0000ms, 48379ms total)
-T3520 7858:523 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: CA 54 DF 1B  returns 0x01 (0000ms, 48379ms total)
-T2244 7858:524 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48379ms total)
-T2244 7858:524 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48380ms total)
-T3520 7858:532 JLINK_IsHalted()  returns FALSE (0000ms, 48380ms total)
-T3520 7858:633 JLINK_IsHalted()  returns FALSE (0000ms, 48380ms total)
-T3520 7858:733 JLINK_IsHalted()  returns FALSE (0000ms, 48380ms total)
-T3520 7858:835 JLINK_IsHalted()  returns FALSE (0000ms, 48380ms total)
-T3520 7858:937 JLINK_IsHalted()  returns FALSE (0000ms, 48380ms total)
-T3520 7859:037 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F8 18 15 1E  returns 0x01 (0000ms, 48380ms total)
-T2244 7859:038 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48381ms total)
-T2244 7859:039 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48382ms total)
-T3520 7859:044 JLINK_IsHalted()  returns FALSE (0001ms, 48383ms total)
-T3520 7859:145 JLINK_IsHalted()  returns FALSE (0000ms, 48382ms total)
-T3520 7859:247 JLINK_IsHalted()  returns FALSE (0000ms, 48382ms total)
-T3520 7859:348 JLINK_IsHalted()  returns FALSE (0000ms, 48382ms total)
-T3520 7859:449 JLINK_IsHalted()  returns FALSE (0000ms, 48382ms total)
-T3520 7859:550 JLINK_IsHalted()  returns FALSE (0000ms, 48382ms total)
-T3520 7859:652 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 52 10 B8 20  returns 0x01 (0000ms, 48382ms total)
-T2244 7859:655 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48383ms total)
-T2244 7859:656 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48384ms total)
-T3520 7859:661 JLINK_IsHalted()  returns FALSE (0000ms, 48384ms total)
-T3520 7859:762 JLINK_IsHalted()  returns FALSE (0000ms, 48384ms total)
-T3520 7859:863 JLINK_IsHalted()  returns FALSE (0000ms, 48384ms total)
-T3520 7859:963 JLINK_IsHalted()  returns FALSE (0000ms, 48384ms total)
-T3520 7860:065 JLINK_IsHalted()  returns FALSE (0000ms, 48384ms total)
-T3520 7860:166 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9C A2 EC 22  returns 0x01 (0000ms, 48384ms total)
-T2244 7860:166 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48384ms total)
-T2244 7860:166 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48385ms total)
-T3520 7860:171 JLINK_IsHalted()  returns FALSE (0000ms, 48385ms total)
-T3520 7860:273 JLINK_IsHalted()  returns FALSE (0000ms, 48385ms total)
-T3520 7860:374 JLINK_IsHalted()  returns FALSE (0000ms, 48385ms total)
-T3520 7860:475 JLINK_IsHalted()  returns FALSE (0001ms, 48386ms total)
-T3520 7860:577 JLINK_IsHalted()  returns FALSE (0000ms, 48385ms total)
-T3520 7860:678 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 75 7E 1F 25  returns 0x01 (0000ms, 48385ms total)
-T2244 7860:679 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48386ms total)
-T2244 7860:680 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48386ms total)
-T3520 7860:688 JLINK_IsHalted()  returns FALSE (0000ms, 48386ms total)
-T3520 7860:790 JLINK_IsHalted()  returns FALSE (0000ms, 48386ms total)
-T3520 7860:891 JLINK_IsHalted()  returns FALSE (0000ms, 48386ms total)
-T3520 7860:992 JLINK_IsHalted()  returns FALSE (0000ms, 48386ms total)
-T3520 7861:093 JLINK_IsHalted()  returns FALSE (0000ms, 48386ms total)
-T3520 7861:194 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 9F 0B 56 27  returns 0x01 (0000ms, 48386ms total)
-T2244 7861:195 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48387ms total)
-T2244 7861:196 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48388ms total)
-T3520 7861:201 JLINK_IsHalted()  returns FALSE (0001ms, 48389ms total)
-T3520 7861:302 JLINK_IsHalted()  returns FALSE (0000ms, 48388ms total)
-T3520 7861:403 JLINK_IsHalted()  returns FALSE (0000ms, 48388ms total)
-T3520 7861:505 JLINK_IsHalted()  returns FALSE (0000ms, 48388ms total)
-T3520 7861:606 JLINK_IsHalted()  returns FALSE (0000ms, 48388ms total)
-T3520 7861:707 JLINK_IsHalted()  returns FALSE (0000ms, 48388ms total)
-T3520 7861:809 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 2E 9A F9 29  returns 0x01 (0000ms, 48388ms total)
-T2244 7861:809 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48389ms total)
-T2244 7861:810 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48390ms total)
-T3520 7861:815 JLINK_IsHalted()  returns FALSE (0000ms, 48390ms total)
-T3520 7861:916 JLINK_IsHalted()  returns FALSE (0000ms, 48390ms total)
-T3520 7862:017 JLINK_IsHalted()  returns FALSE (0000ms, 48390ms total)
-T3520 7862:118 JLINK_IsHalted()  returns FALSE (0000ms, 48390ms total)
-T3520 7862:219 JLINK_IsHalted()  returns FALSE (0000ms, 48390ms total)
-T3520 7862:320 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 7F D7 2B 2C  returns 0x01 (0001ms, 48391ms total)
-T2244 7862:321 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48392ms total)
-T2244 7862:322 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48393ms total)
-T3520 7862:328 JLINK_IsHalted()  returns FALSE (0000ms, 48393ms total)
-T3520 7862:429 JLINK_IsHalted()  returns FALSE (0000ms, 48393ms total)
-T3520 7862:530 JLINK_IsHalted()  returns FALSE (0000ms, 48393ms total)
-T3520 7862:631 JLINK_IsHalted()  returns FALSE (0000ms, 48393ms total)
-T3520 7862:732 JLINK_IsHalted()  returns FALSE (0000ms, 48393ms total)
-T3520 7862:833 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 78 B4 5F 2E  returns 0x01 (0000ms, 48393ms total)
-T2244 7862:834 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 48393ms total)
-T2244 7862:835 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48394ms total)
-T3520 7862:841 JLINK_IsHalted()  returns FALSE (0000ms, 48394ms total)
-T3520 7862:941 JLINK_IsHalted()  returns FALSE (0001ms, 48395ms total)
-T3520 7863:042 JLINK_IsHalted()  returns FALSE (0000ms, 48394ms total)
-T3520 7863:143 JLINK_IsHalted()  returns FALSE (0000ms, 48394ms total)
-T3520 7863:244 JLINK_IsHalted()  returns FALSE (0000ms, 48394ms total)
-T3520 7863:345 JLINK_IsHalted()  returns FALSE (0000ms, 48394ms total)
-T3520 7863:445 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 13 F7 FF 30  returns 0x01 (0000ms, 48394ms total)
-T2244 7863:445 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0002ms, 48396ms total)
-T2244 7863:447 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48396ms total)
-T3520 7863:451 JLINK_IsHalted()  returns FALSE (0001ms, 48397ms total)
-T3520 7863:552 JLINK_IsHalted()  returns FALSE (0000ms, 48396ms total)
-T3520 7863:654 JLINK_IsHalted()  returns FALSE (0000ms, 48396ms total)
-T3520 7863:755 JLINK_IsHalted()  returns FALSE (0000ms, 48396ms total)
-T3520 7863:856 JLINK_IsHalted()  returns FALSE (0000ms, 48396ms total)
-T3520 7863:957 JLINK_IsHalted()  returns FALSE (0000ms, 48396ms total)
-T3520 7864:059 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 49 CF A1 33  returns 0x01 (0000ms, 48396ms total)
-T2244 7864:061 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48397ms total)
-T2244 7864:062 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48398ms total)
-T3520 7864:072 JLINK_IsHalted()  returns FALSE (0000ms, 48398ms total)
-T3520 7864:173 JLINK_IsHalted()  returns FALSE (0000ms, 48398ms total)
-T3520 7864:274 JLINK_IsHalted()  returns FALSE (0000ms, 48398ms total)
-T3520 7864:375 JLINK_IsHalted()  returns FALSE (0000ms, 48398ms total)
-T3520 7864:475 JLINK_IsHalted()  returns FALSE (0000ms, 48398ms total)
-T3520 7864:576 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: EC A0 DA 35  returns 0x01 (0000ms, 48398ms total)
-T2244 7864:577 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48399ms total)
-T2244 7864:578 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48399ms total)
-T3520 7864:582 JLINK_IsHalted()  returns FALSE (0001ms, 48400ms total)
-T3520 7864:684 JLINK_IsHalted()  returns FALSE (0000ms, 48399ms total)
-T3520 7864:785 JLINK_IsHalted()  returns FALSE (0000ms, 48399ms total)
-T3520 7864:887 JLINK_IsHalted()  returns FALSE (0000ms, 48399ms total)
-T3520 7864:988 JLINK_IsHalted()  returns FALSE (0000ms, 48399ms total)
-T3520 7865:089 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 57 7F 0D 38  returns 0x01 (0000ms, 48399ms total)
-T2244 7865:091 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48400ms total)
-T2244 7865:092 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0001ms, 48401ms total)
-T3520 7865:098 JLINK_IsHalted()  returns FALSE (0000ms, 48401ms total)
-T3520 7865:199 JLINK_IsHalted()  returns FALSE (0000ms, 48401ms total)
-T3520 7865:300 JLINK_IsHalted()  returns FALSE (0000ms, 48401ms total)
-T3520 7865:400 JLINK_IsHalted()  returns FALSE (0000ms, 48401ms total)
-T3520 7865:502 JLINK_IsHalted()  returns FALSE (0000ms, 48401ms total)
-T3520 7865:603 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 66 F3 42 3A  returns 0x01 (0000ms, 48401ms total)
-T2244 7865:604 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48402ms total)
-T2244 7865:605 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48402ms total)
-T3520 7865:610 JLINK_IsHalted()  returns FALSE (0000ms, 48402ms total)
-T3520 7865:711 JLINK_Halt()  returns 0x00 (0003ms, 48405ms total)
-T3520 7865:714 JLINK_IsHalted()  returns TRUE (0000ms, 48405ms total)
-T3520 7865:714 JLINK_IsHalted()  returns TRUE (0000ms, 48405ms total)
-T3520 7865:714 JLINK_IsHalted()  returns TRUE (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ReadReg(R15 (PC))  returns 0x080003EA (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ReadReg(XPSR)  returns 0x41000000 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002B)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002C)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002D)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002E)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x0000002F)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ClrBPEx(BPHandle = 0x00000030)  returns 0x00 (0000ms, 48405ms total)
-T3520 7865:714 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 01 00 00 00  returns 0x01 (0001ms, 48406ms total)
-T3520 7865:715 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 48406ms total)
-T3520 7865:715 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0001ms, 48407ms total)
-T3520 7865:716 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0000ms, 48407ms total)
-T3520 7865:716 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R1)  returns 0x00070082 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R2)  returns 0x40005400 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R3)  returns 0x00030000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R5)  returns 0x20000014 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R10)  returns 0x08000934 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R12)  returns 0x000000C0 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R13 (SP))  returns 0x20000670 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R14)  returns 0x080003EB (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(R15 (PC))  returns 0x080003EA (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(XPSR)  returns 0x41000000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(MSP)  returns 0x20000670 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 48408ms total)
-T3520 7865:717 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 48408ms total)
-T2244 7865:719 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0001ms, 48409ms total)
-T2244 7865:720 JLINK_ReadMemEx(0x20000670, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000670, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000670) - Data: 00 00 00 00  returns 0x04 (0000ms, 48409ms total)
-T2244 7865:721 JLINK_ReadMemEx(0x20000674, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x20000674, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000674) - Data: 0F 09 00 08  returns 0x04 (0000ms, 48409ms total)
-T2244 7865:721 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: E2 A0 B9 3A  returns 0x01 (0001ms, 48410ms total)
-T2244 7865:722 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 01 04 00 00 24 00 00 00 21 40 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 48411ms total)
-T2244 7865:723 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 25 00 00 00  returns 0x04 (0000ms, 48411ms total)
-T2244 7865:730 JLINK_ReadMemEx(0x080003EA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080003C0) -- Updating C cache (64 bytes @ 0x080003C0) -- Read from C cache (2 bytes @ 0x080003EA) - Data: 00 28  returns 0x02 (0001ms, 48412ms total)
-T2244 7865:731 JLINK_ReadMemEx(0x080003EC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000400) -- Updating C cache (64 bytes @ 0x08000400) -- Read from C cache (60 bytes @ 0x080003EC) - Data: F9 D0 21 46 1A 48 00 F0 34 F9 00 BF 01 21 18 48 ...  returns 0x3C (0001ms, 48413ms total)
-T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EC) - Data: F9 D0  returns 0x02 (0000ms, 48413ms total)
-T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003EC) - Data: F9 D0 21 46 1A 48 00 F0 34 F9 00 BF 01 21 18 48 ...  returns 0x3C (0000ms, 48413ms total)
-T2244 7865:732 JLINK_ReadMemEx(0x080003EC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EC) - Data: F9 D0  returns 0x02 (0001ms, 48414ms total)
-T2244 7865:733 JLINK_ReadMemEx(0x080003EE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EE) - Data: 21 46  returns 0x02 (0000ms, 48414ms total)
-T2244 7865:733 JLINK_ReadMemEx(0x080003EE, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003EE, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003EE) - Data: 21 46  returns 0x02 (0000ms, 48414ms total)
-T2244 7865:733 JLINK_ReadMemEx(0x080003F0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F0) - Data: 1A 48 00 F0 34 F9 00 BF 01 21 18 48 00 F0 40 F8 ...  returns 0x3C (0000ms, 48414ms total)
-T2244 7865:733 JLINK_ReadMemEx(0x080003F0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F0) - Data: 1A 48  returns 0x02 (0000ms, 48414ms total)
-T2244 7873:597 JLINK_ReadMemEx(0x080003D6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D6) - Data: 01 22  returns 0x02 (0001ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003D8) - Data: 21 21 20 48 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003D8, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003D8, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003D8) - Data: 21 21  returns 0x02 (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003DA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DA) - Data: 20 48  returns 0x02 (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003DC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003DC) - Data: 00 F0 36 F9 00 BF 20 49 1D 48 00 F0 4B F8 00 28 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7873:598 JLINK_ReadMemEx(0x080003DC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003DC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003DC) - Data: 00 F0  returns 0x02 (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F0) - Data: 1A 48 00 F0 34 F9 00 BF 01 21 18 48 00 F0 40 F8 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F0) - Data: 1A 48  returns 0x02 (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F2) - Data: 00 F0  returns 0x02 (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F2) - Data: 00 F0  returns 0x02 (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F4, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003F4) - Data: 34 F9 00 BF 01 21 18 48 00 F0 40 F8 00 28 F9 D0 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7874:221 JLINK_ReadMemEx(0x080003F4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003F4, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003F4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003F4) - Data: 34 F9  returns 0x02 (0000ms, 48415ms total)
-T2244 7875:805 JLINK_ReadMemEx(0x080003E0, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E0) - Data: 00 BF 20 49 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 ...  returns 0x3C (0000ms, 48415ms total)
-T2244 7875:805 JLINK_ReadMemEx(0x080003E0, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E0, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E0) - Data: 00 BF  returns 0x02 (0000ms, 48415ms total)
-T2244 7875:805 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E2) - Data: 20 49  returns 0x02 (0001ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E2, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E2, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E2) - Data: 20 49  returns 0x02 (0000ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E4) - Data: 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 1A 48 00 F0 ...  returns 0x3C (0000ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E4) - Data: 1D 48  returns 0x02 (0000ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x080003E4) - Data: 1D 48 00 F0 4B F8 00 28 F9 D0 21 46 1A 48 00 F0 ...  returns 0x3C (0000ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E4, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E4, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E4) - Data: 1D 48  returns 0x02 (0000ms, 48416ms total)
-T2244 7875:806 JLINK_ReadMemEx(0x080003E6, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned)
-  ***** Mis-aligned memory read: Address: 0x080003E6, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080003E6) - Data: 00 F0  returns 0x02 (0000ms, 48416ms total)
-T2244 7899:053 JLINK_Close() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) >0x80 JTAG> >0x08 JTAG> (0007ms, 48423ms total)
-T2244 7899:053  (0007ms, 48423ms total)
-T2244 7899:053 Closed (0007ms, 48423ms total)
+ aScanRead[0]=0 (0029ms, 39814ms total)
+T2DCC 98179:194 JLINK_JTAG_GetDeviceID(DeviceIndex = 0)  returns 0x3BA00477 (0000ms, 39814ms total)
+T2DCC 98179:194 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0)  returns 0x00 (0000ms, 39814ms total)
+T2DCC 98179:194 JLINK_JTAG_GetDeviceID(DeviceIndex = 1)  returns 0x16410041 (0000ms, 39814ms total)
+T2DCC 98179:194 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1)  returns 0x00 (0001ms, 39815ms total)
+T2DCC 98179:195 JLINK_GetDLLVersion()  returns 49000 (0000ms, 39815ms total)
+T2DCC 98179:195 JLINK_CORE_GetFound()  returns 0x30000FF (0000ms, 39815ms total)
+T2DCC 98179:195 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003  returns 0x00 (0000ms, 39815ms total)
+T2DCC 98179:195 JLINK_GetDebugInfo(0x101)  returns 0xFFFFFFFF (0000ms, 39815ms total)
+T2DCC 98179:195 JLINK_ReadMemEx(0xE0041FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  returns 0x10 (0001ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x102)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x103)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_ReadMemEx(0xE0040FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00  returns 0x10 (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x104)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x105)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x106)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x107)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x10C)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDebugInfo(0x01)  returns 0xFFFFFFFF (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_GetDeviceFamily()  returns 3 (0000ms, 39816ms total)
+T2DCC 98179:196 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41  returns 0x01 (0001ms, 39817ms total)
+T2DCC 98179:197 JLINK_GetDebugInfo(0x10F)  returns 0xFFFFFFFF (0000ms, 39817ms total)
+T2DCC 98179:197 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 39817ms total)
+T2DCC 98179:197 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG>
+ >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 39845ms total)
+T2DCC 98179:225 JLINK_ReadReg(R15 (PC))  returns 0x0800016C (0000ms, 39845ms total)
+T2DCC 98179:225 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39845ms total)
+T2DCC 98179:225 JLINK_Halt()  returns 0x00 (0000ms, 39845ms total)
+T2DCC 98179:225 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00  returns 0x01 (0000ms, 39845ms total)
+T2DCC 98179:225 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0)  returns 0x00 (0001ms, 39846ms total)
+T2DCC 98179:226 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)  returns 0x00 (0000ms, 39846ms total)
+T2DCC 98179:226 JLINK_GetHWStatus(...)  returns 0x00 (0001ms, 39847ms total)
+T2DCC 98179:227 JLINK_GetNumBPUnits(Type = 0xFFFFFF00)  returns 0x06 (0000ms, 39847ms total)
+T2DCC 98179:227 JLINK_GetNumBPUnits(Type = 0xF0)  returns 0x2000 (0000ms, 39847ms total)
+T2DCC 98179:227 JLINK_GetNumWPUnits()  returns 0x04 (0000ms, 39847ms total)
+T2DCC 98179:227 JLINK_GetSpeed()  returns 0x12C0 (0000ms, 39847ms total)
+T2DCC 98179:227 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0001ms, 39848ms total)
+T2DCC 98179:228 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0001ms, 39849ms total)
+T2DCC 98179:229 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., AccessWidth = 33554436) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000)  returns 0x1C (0000ms, 39849ms total)
+T2DCC 98179:229 JLINK_ReadReg(R15 (PC))  returns 0x0800016C (0000ms, 39849ms total)
+T2DCC 98179:229 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39849ms total)
+T2DCC 98179:241 JLINK_ReadMemEx(0xE0001004, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0xE0001004, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00  returns 0x04 (0001ms, 39850ms total)
+T2DCC 98179:324 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 39850ms total)
+T2DCC 98179:324 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028)
+ -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0026ms, 39876ms total)
+T2DCC 98179:350 JLINK_ReadReg(R15 (PC))  returns 0x0800016C (0000ms, 39876ms total)
+T2DCC 98179:350 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39876ms total)
+T2DCC 98179:351 JLINK_ReadMemEx(0x0800016C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016C, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000140) -- Updating C cache (128 bytes @ 0x08000140) -- Read from C cache (60 bytes @ 0x0800016C) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0003ms, 39879ms total)
+T2DCC 98179:354 JLINK_ReadMemEx(0x0800016C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016C) - Data: 09 48  returns 0x02 (0000ms, 39879ms total)
+T2DCC 98179:354 JLINK_ReadMemEx(0x0800016E, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016E) - Data: 80 47  returns 0x02 (0000ms, 39879ms total)
+T2DCC 98179:354 JLINK_ReadMemEx(0x0800016E, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016E) - Data: 80 47  returns 0x02 (0000ms, 39879ms total)
+T2DCC 98179:354 JLINK_ReadMemEx(0x08000170, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000170, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000170, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x08000170) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0000ms, 39879ms total)
+T2DCC 98179:354 JLINK_ReadMemEx(0x08000170, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000170, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000170, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000170) - Data: 09 48  returns 0x02 (0000ms, 39879ms total)
+T2DCC 98179:563 JLINK_ReadMemEx(0x40010C00, 0x000C Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(12 bytes @ 0x40010C00) - Data: 44 44 48 44 44 44 44 44 00 00 00 00  returns 0x0C (0000ms, 39879ms total)
+T2DCC 98179:563 JLINK_ReadMemEx(0x40010C0C, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C0C) - Data: 10 00 00 00  returns 0x04 (0001ms, 39880ms total)
+T2DCC 98179:564 JLINK_ReadMemEx(0x40010C18, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C18) - Data: 00 00 00 00  returns 0x04 (0000ms, 39880ms total)
+T2DCC 98179:657 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 39880ms total)
+T2DCC 98179:657 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0001ms, 39881ms total)
+T2DCC 98182:607 JLINK_ReadMemEx(0x0800016C, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016C, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016C, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x0800016C) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0000ms, 39881ms total)
+T2DCC 98182:607 JLINK_ReadMemEx(0x0800016C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016C) - Data: 09 48  returns 0x02 (0000ms, 39881ms total)
+T2DCC 98182:607 JLINK_ReadMemEx(0x0800016E, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016E) - Data: 80 47  returns 0x02 (0000ms, 39881ms total)
+T2DCC 98182:607 JLINK_ReadMemEx(0x0800016E, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016E, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016E) - Data: 80 47  returns 0x02 (0000ms, 39881ms total)
+T2DCC 98182:607 JLINK_ReadMemEx(0x08000170, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000170, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000170, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- Read from C cache (60 bytes @ 0x08000170) - Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ...  returns 0x3C (0001ms, 39882ms total)
+T2DCC 98182:608 JLINK_ReadMemEx(0x08000170, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000170, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000170, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000170) - Data: 09 48  returns 0x02 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R1)  returns 0x00000003 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R2)  returns 0x40022000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R3)  returns 0x04C11DB7 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R5)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R10)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R12)  returns 0x00000000 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R13 (SP))  returns 0x20000660 (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R14)  returns 0xFFFFFFFF (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(R15 (PC))  returns 0x0800016C (0000ms, 39882ms total)
+T2DCC 98183:201 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39882ms total)
+T2DCC 98183:202 JLINK_ReadReg(MSP)  returns 0x20000660 (0000ms, 39883ms total)
+T2DCC 98183:202 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 39883ms total)
+T2DCC 98183:202 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 39883ms total)
+T34A4 98183:374 JLINK_ReadMemEx(0x0800016C, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x0800016C, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x0800016C) - Data: 09 48  returns 0x02 (0001ms, 39884ms total)
+T34A4 98183:375 JLINK_SetBPEx(Addr = 0x08000762, Type = 0xFFFFFFF2)  returns 0x00000001 (0000ms, 39884ms total)
+T34A4 98183:375 JLINK_SetBPEx(Addr = 0x080004BA, Type = 0xFFFFFFF2)  returns 0x00000002 (0000ms, 39884ms total)
+T34A4 98183:375 JLINK_SetBPEx(Addr = 0x08000786, Type = 0xFFFFFFF2)  returns 0x00000003 (0000ms, 39884ms total)
+T34A4 98183:375 JLINK_SetBPEx(Addr = 0x08000774, Type = 0xFFFFFFF2)  returns 0x00000004 (0000ms, 39884ms total)
+T34A4 98183:375 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0003ms, 39887ms total)
+T34A4 98183:479 JLINK_IsHalted()  returns TRUE (0003ms, 39890ms total)
+T34A4 98183:482 JLINK_Halt()  returns 0x00 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_IsHalted()  returns TRUE (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_IsHalted()  returns TRUE (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_IsHalted()  returns TRUE (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ReadReg(R15 (PC))  returns 0x08000762 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ClrBPEx(BPHandle = 0x00000001)  returns 0x00 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ClrBPEx(BPHandle = 0x00000002)  returns 0x00 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ClrBPEx(BPHandle = 0x00000003)  returns 0x00 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ClrBPEx(BPHandle = 0x00000004)  returns 0x00 (0000ms, 39887ms total)
+T34A4 98183:482 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 39888ms total)
+T34A4 98183:483 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 39888ms total)
+T34A4 98183:483 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0001ms, 39889ms total)
+T34A4 98183:484 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0000ms, 39889ms total)
+T34A4 98183:484 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0001ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R0)  returns 0x20000060 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R1)  returns 0x20000260 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R2)  returns 0x20000260 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R3)  returns 0x20000260 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R5)  returns 0x20000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R10)  returns 0x0800079C (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R12)  returns 0x20000040 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R13 (SP))  returns 0x20000660 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R14)  returns 0x0800015B (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(R15 (PC))  returns 0x08000762 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(XPSR)  returns 0x21000000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(MSP)  returns 0x20000660 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 39890ms total)
+T34A4 98183:485 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 39890ms total)
+T2DCC 98183:486 JLINK_ReadMemEx(0x20000658, 0x0001 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (1 bytes @ 0x20000658) - Data: 00  returns 0x01 (0001ms, 39891ms total)
+T2DCC 98183:489 JLINK_ReadMemEx(0x20000658, 0x0001 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned) -- Read from C cache (1 bytes @ 0x20000658) - Data: 00  returns 0x01 (0000ms, 39891ms total)
+T2DCC 98183:489 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 7D 13 00 00  returns 0x01 (0001ms, 39892ms total)
+T2DCC 98183:490 JLINK_ReadMemEx(0x40010C00, 0x000C Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(12 bytes @ 0x40010C00) - Data: 44 44 48 44 44 44 44 44 00 00 00 00  returns 0x0C (0001ms, 39893ms total)
+T2DCC 98183:491 JLINK_ReadMemEx(0x40010C0C, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C0C) - Data: 10 00 00 00  returns 0x04 (0001ms, 39894ms total)
+T2DCC 98183:492 JLINK_ReadMemEx(0x40010C18, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C18) - Data: 00 00 00 00  returns 0x04 (0000ms, 39894ms total)
+T2DCC 98183:499 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 39895ms total)
+T2DCC 98183:500 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0000ms, 39895ms total)
+T34A4 98186:599 JLINK_ReadMemEx(0x08000762, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000762, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000762, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000740) -- Updating C cache (64 bytes @ 0x08000740) -- Read from C cache (2 bytes @ 0x08000762) - Data: 08 B5  returns 0x02 (0001ms, 39896ms total)
+T34A4 98186:600 JLINK_SetBPEx(Addr = 0x080004BA, Type = 0xFFFFFFF2)  returns 0x00000005 (0000ms, 39896ms total)
+T34A4 98186:600 JLINK_SetBPEx(Addr = 0x08000786, Type = 0xFFFFFFF2)  returns 0x00000006 (0000ms, 39896ms total)
+T34A4 98186:600 JLINK_SetBPEx(Addr = 0x08000774, Type = 0xFFFFFFF2)  returns 0x00000007 (0000ms, 39896ms total)
+T34A4 98186:600 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) (0003ms, 39899ms total)
+T34A4 98186:704 JLINK_IsHalted()  returns TRUE (0003ms, 39902ms total)
+T34A4 98186:707 JLINK_Halt()  returns 0x00 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_IsHalted()  returns TRUE (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_IsHalted()  returns TRUE (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_IsHalted()  returns TRUE (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ReadReg(R15 (PC))  returns 0x08000774 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ClrBPEx(BPHandle = 0x00000005)  returns 0x00 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ClrBPEx(BPHandle = 0x00000006)  returns 0x00 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ClrBPEx(BPHandle = 0x00000007)  returns 0x00 (0000ms, 39899ms total)
+T34A4 98186:707 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 39900ms total)
+T34A4 98186:708 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 39900ms total)
+T34A4 98186:708 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0001ms, 39901ms total)
+T34A4 98186:709 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 39902ms total)
+T34A4 98186:710 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0000ms, 39902ms total)
+T34A4 98186:710 JLINK_ReadReg(R0)  returns 0x40010C00 (0000ms, 39902ms total)
+T34A4 98186:710 JLINK_ReadReg(R1)  returns 0x00000040 (0001ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R2)  returns 0x40010C00 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R3)  returns 0x10030080 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R5)  returns 0x20000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R10)  returns 0x0800079C (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R12)  returns 0x00000080 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R13 (SP))  returns 0x20000658 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R14)  returns 0x080003DB (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(R15 (PC))  returns 0x08000774 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(XPSR)  returns 0x01000000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(MSP)  returns 0x20000658 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 39903ms total)
+T34A4 98186:711 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 39903ms total)
+T2DCC 98186:711 JLINK_ReadMemEx(0x2000065C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000065C, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x2000065C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x2000065C) - Data: 5B 01 00 08  returns 0x04 (0001ms, 39904ms total)
+T2DCC 98186:712 JLINK_ReadMemEx(0x20000658, 0x0001 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned) -- Read from C cache (1 bytes @ 0x20000658) - Data: 60  returns 0x01 (0000ms, 39904ms total)
+T2DCC 98186:713 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: F1 1E 00 00  returns 0x01 (0001ms, 39905ms total)
+T2DCC 98186:714 JLINK_ReadMemEx(0x40010C00, 0x000C Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(12 bytes @ 0x40010C00) - Data: 44 44 48 33 44 44 44 44 D1 FF 00 00  returns 0x0C (0001ms, 39906ms total)
+T2DCC 98186:715 JLINK_ReadMemEx(0x40010C0C, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C0C) - Data: D0 00 00 00  returns 0x04 (0001ms, 39907ms total)
+T2DCC 98186:716 JLINK_ReadMemEx(0x40010C18, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C18) - Data: 00 00 00 00  returns 0x04 (0000ms, 39907ms total)
+T2DCC 98186:747 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0001ms, 39908ms total)
+T2DCC 98186:748 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0001ms, 39909ms total)
+T2DCC 98186:753 JLINK_ReadMemEx(0x08000774, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000774, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000774, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(128 bytes @ 0x08000740) -- Updating C cache (128 bytes @ 0x08000740) -- Read from C cache (60 bytes @ 0x08000774) - Data: 00 20 FF F7 7B FE 00 90 9D F8 00 00 40 1C C0 B2 ...  returns 0x3C (0002ms, 39911ms total)
+T2DCC 98186:755 JLINK_ReadMemEx(0x08000774, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000774, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000774, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000774) - Data: 00 20  returns 0x02 (0000ms, 39911ms total)
+T2DCC 98186:755 JLINK_ReadMemEx(0x08000776, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000776, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000776, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000776) - Data: FF F7  returns 0x02 (0000ms, 39911ms total)
+T34A4 98198:004 JLINK_ReadMemEx(0x08000774, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x08000774, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x08000774, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x08000774) - Data: 00 20  returns 0x02 (0004ms, 39915ms total)
+T34A4 98198:008 JLINK_Step() -- Read from C cache (2 bytes @ 0x08000774) -- Simulated  returns 0x00 (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_ReadReg(R15 (PC))  returns 0x08000776 (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_ReadReg(XPSR)  returns 0x41000000 (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_SetBPEx(Addr = 0x080004BA, Type = 0xFFFFFFF2)  returns 0x00000008 (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_SetBPEx(Addr = 0x08000786, Type = 0xFFFFFFF2)  returns 0x00000009 (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_SetBPEx(Addr = 0x08000774, Type = 0xFFFFFFF2)  returns 0x0000000A (0000ms, 39915ms total)
+T34A4 98198:008 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0001004) (0002ms, 39917ms total)
+T34A4 98198:111 JLINK_IsHalted()  returns TRUE (0003ms, 39920ms total)
+T34A4 98198:114 JLINK_Halt()  returns 0x00 (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_IsHalted()  returns TRUE (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_IsHalted()  returns TRUE (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_IsHalted()  returns TRUE (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ReadReg(R15 (PC))  returns 0x080004BA (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ClrBPEx(BPHandle = 0x00000008)  returns 0x00 (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ClrBPEx(BPHandle = 0x00000009)  returns 0x00 (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ClrBPEx(BPHandle = 0x0000000A)  returns 0x00 (0000ms, 39917ms total)
+T34A4 98198:114 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00  returns 0x01 (0001ms, 39918ms total)
+T34A4 98198:115 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00  returns 0x01 (0000ms, 39918ms total)
+T34A4 98198:115 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00  returns 0x01 (0001ms, 39919ms total)
+T34A4 98198:116 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00  returns 0x01 (0001ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00  returns 0x01 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R0)  returns 0x00000002 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R1)  returns 0x00000032 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R2)  returns 0x00000032 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R3)  returns 0x10030080 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R4)  returns 0x00000000 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R5)  returns 0x000000FF (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R6)  returns 0x00000000 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R7)  returns 0x00000000 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R8)  returns 0x00000000 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R9)  returns 0x20000160 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R10)  returns 0x0800079C (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R11)  returns 0x00000000 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R12)  returns 0x00000080 (0000ms, 39920ms total)
+T34A4 98198:117 JLINK_ReadReg(R13 (SP))  returns 0x20000648 (0001ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(R14)  returns 0x08000569 (0000ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(R15 (PC))  returns 0x080004BA (0000ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(XPSR)  returns 0x61000000 (0000ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(MSP)  returns 0x20000648 (0000ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(PSP)  returns 0x20001000 (0000ms, 39921ms total)
+T34A4 98198:118 JLINK_ReadReg(CFBP)  returns 0x00000000 (0000ms, 39921ms total)
+T2DCC 98198:124 JLINK_ReadMemEx(0x20000654, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000654, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000654, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x20000640) -- Updating C cache (64 bytes @ 0x20000640) -- Read from C cache (4 bytes @ 0x20000654) - Data: 7B 07 00 08  returns 0x04 (0001ms, 39922ms total)
+T2DCC 98198:125 JLINK_ReadMemEx(0x20000648, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000648, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000648, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000648) - Data: 00 00 00 00  returns 0x04 (0000ms, 39922ms total)
+T2DCC 98198:125 JLINK_ReadMemEx(0x2000064C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000064C, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x2000064C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x2000064C) - Data: 00 00 00 20  returns 0x04 (0000ms, 39922ms total)
+T2DCC 98198:125 JLINK_ReadMemEx(0x20000650, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000650, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000650, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000650) - Data: 00 00 00 00  returns 0x04 (0000ms, 39922ms total)
+T2DCC 98198:125 JLINK_ReadMemEx(0x20000654, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000654, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000654, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x20000654) - Data: 7B 07 00 08  returns 0x04 (0000ms, 39922ms total)
+T2DCC 98198:125 JLINK_ReadMemEx(0x2000065C, 0x0004 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x2000065C, NumBytes: 4, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x2000065C, NumBytes: 4, Alignment: 2 (Halfword-aligned) -- Read from C cache (4 bytes @ 0x2000065C) - Data: 5B 01 00 08  returns 0x04 (0000ms, 39922ms total)
+T2DCC 98198:134 JLINK_ReadMemEx(0x20000658, 0x0001 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x20000658, NumBytes: 1, Alignment: 2 (Halfword-aligned) -- Read from C cache (1 bytes @ 0x20000658) - Data: 60  returns 0x01 (0000ms, 39922ms total)
+T2DCC 98198:134 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 08 21 02 00  returns 0x01 (0002ms, 39924ms total)
+T2DCC 98198:136 JLINK_ReadMemEx(0x40010C00, 0x000C Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(12 bytes @ 0x40010C00) - Data: 44 44 48 33 44 44 44 44 D1 FF 00 00  returns 0x0C (0000ms, 39924ms total)
+T2DCC 98198:136 JLINK_ReadMemEx(0x40010C0C, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C0C) - Data: D0 00 00 00  returns 0x04 (0001ms, 39925ms total)
+T2DCC 98198:137 JLINK_ReadMemEx(0x40010C18, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40010C18) - Data: 00 00 00 00  returns 0x04 (0000ms, 39925ms total)
+T2DCC 98198:143 JLINK_ReadMemEx(0x40005400, 0x0020 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(32 bytes @ 0x40005400) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...  returns 0x20 (0000ms, 39925ms total)
+T2DCC 98198:143 JLINK_ReadMemEx(0x40005420, 0x0004 Bytes, ..., AccessWidth = 33554436) -- CPU_ReadMem(4 bytes @ 0x40005420) - Data: 00 00 00 00  returns 0x04 (0001ms, 39926ms total)
+T2DCC 98198:148 JLINK_ReadMemEx(0x080004BA, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080004BA, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x080004BA, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x08000480) -- Updating C cache (64 bytes @ 0x08000480) -- Read from C cache (2 bytes @ 0x080004BA) - Data: 28 46  returns 0x02 (0000ms, 39926ms total)
+T2DCC 98198:148 JLINK_ReadMemEx(0x080004BC, 0x003C Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080004BC, NumBytes: 60, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x080004BC, NumBytes: 60, Alignment: 2 (Halfword-aligned) -- CPU_ReadMem(64 bytes @ 0x080004C0) -- Updating C cache (64 bytes @ 0x080004C0) -- Read from C cache (60 bytes @ 0x080004BC) - Data: 70 BD 00 00 08 B5 80 20 AD F8 00 00 03 20 8D F8 ...  returns 0x3C (0001ms, 39927ms total)
+T2DCC 98198:149 JLINK_ReadMemEx(0x080004BC, 0x0002 Bytes, ..., AccessWidth = 33554432)Mis-aligned memory read: Address: 0x080004BC, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory read: Address: 0x080004BC, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- Read from C cache (2 bytes @ 0x080004BC) - Data: 70 BD  returns 0x02 (0001ms, 39928ms total)
+T2DCC 98303:975 JLINK_Close() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) >0x80 JTAG> >0x08 JTAG> (0006ms, 39934ms total)
+T2DCC 98303:975  (0006ms, 39934ms total)
+T2DCC 98303:975 Closed (0006ms, 39934ms total)
diff --git a/cmos/gc0307/stm32/Listings/gc0307.map b/cmos/gc0307/stm32/Listings/gc0307.map
index 3d4a992..8d65883 100644
--- a/cmos/gc0307/stm32/Listings/gc0307.map
+++ b/cmos/gc0307/stm32/Listings/gc0307.map
@@ -19,9 +19,9 @@ Section Cross References
     main.o(i.I2C_GPIO_Config) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
     main.o(i.RCC_Configuration) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
     main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration
-    main.o(i.main) refers to main.o(i.I2C_GPIO_Config) for I2C_GPIO_Config
-    main.o(i.main) refers to main.o(i.I2C1_Init) for I2C1_Init
-    main.o(i.main) refers to main.o(i.I2C1_Read) for I2C1_Read
+    main.o(i.main) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+    main.o(i.main) refers to sccb.o(i.SCCB_Init) for SCCB_Init
+    main.o(i.main) refers to sccb.o(i.SCCB_RD_Reg) for SCCB_RD_Reg
     i2c_ee.o(i.GPIO_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
     i2c_ee.o(i.I2C_Configuration) refers to stm32f10x_i2c.o(i.I2C_Cmd) for I2C_Cmd
     i2c_ee.o(i.I2C_Configuration) refers to stm32f10x_i2c.o(i.I2C_Init) for I2C_Init
@@ -60,10 +60,50 @@ Section Cross References
     i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_ClearFlag) for I2C_ClearFlag
     i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP
     i2c_ee.o(i.I2C_EE_WaitEepromStandbyState) refers to i2c_ee.o(.data) for EEPROM_ADDRESS
+    sccb.o(i.SCCB_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+    sccb.o(i.SCCB_Init) refers to sccb.o(i.SCCB_SDA_OUT) for SCCB_SDA_OUT
+    sccb.o(i.SCCB_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_No_Ack) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_No_Ack) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_No_Ack) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+    sccb.o(i.SCCB_RD_Byte) refers to sccb.o(i.SCCB_SDA_IN) for SCCB_SDA_IN
+    sccb.o(i.SCCB_RD_Byte) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_RD_Byte) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_RD_Byte) refers to stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit
+    sccb.o(i.SCCB_RD_Byte) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+    sccb.o(i.SCCB_RD_Byte) refers to sccb.o(i.SCCB_SDA_OUT) for SCCB_SDA_OUT
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.SCCB_Start) for SCCB_Start
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.SCCB_WR_Byte) for SCCB_WR_Byte
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.SCCB_Stop) for SCCB_Stop
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.SCCB_RD_Byte) for SCCB_RD_Byte
+    sccb.o(i.SCCB_RD_Reg) refers to sccb.o(i.SCCB_No_Ack) for SCCB_No_Ack
+    sccb.o(i.SCCB_SDA_IN) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+    sccb.o(i.SCCB_SDA_OUT) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+    sccb.o(i.SCCB_Start) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_Start) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_Start) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+    sccb.o(i.SCCB_Stop) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+    sccb.o(i.SCCB_Stop) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_Stop) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_WR_Byte) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+    sccb.o(i.SCCB_WR_Byte) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+    sccb.o(i.SCCB_WR_Byte) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_WR_Byte) refers to sccb.o(i.SCCB_SDA_IN) for SCCB_SDA_IN
+    sccb.o(i.SCCB_WR_Byte) refers to stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit
+    sccb.o(i.SCCB_WR_Byte) refers to sccb.o(i.SCCB_SDA_OUT) for SCCB_SDA_OUT
+    sccb.o(i.SCCB_WR_Reg) refers to sccb.o(i.SCCB_Start) for SCCB_Start
+    sccb.o(i.SCCB_WR_Reg) refers to sccb.o(i.SCCB_WR_Byte) for SCCB_WR_Byte
+    sccb.o(i.SCCB_WR_Reg) refers to sccb.o(i.delay_us) for delay_us
+    sccb.o(i.SCCB_WR_Reg) refers to sccb.o(i.SCCB_Stop) for SCCB_Stop
+    stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+    stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
     stm32f10x_i2c.o(i.I2C_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
     stm32f10x_i2c.o(i.I2C_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
     stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable
     stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
+    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_GetPortClockState) for GPIO_GetPortClockState
+    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_PortClock) for GPIO_PortClock
     startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
     startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
     startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
@@ -86,10 +126,6 @@ Section Cross References
     system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
     system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
     system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
-    stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
-    stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
-    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_GetPortClockState) for GPIO_GetPortClockState
-    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_PortClock) for GPIO_PortClock
     __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
     __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
     __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
@@ -201,6 +237,9 @@ Removing Unused input sections from the image.
     Removing main.o(.revsh_text), (4 bytes).
     Removing main.o(.rrx_text), (6 bytes).
     Removing main.o(i.Buffercmp), (36 bytes).
+    Removing main.o(i.I2C1_Init), (80 bytes).
+    Removing main.o(i.I2C1_Read), (180 bytes).
+    Removing main.o(i.I2C_GPIO_Config), (44 bytes).
     Removing main.o(.bss), (44 bytes).
     Removing main.o(.data), (48 bytes).
     Removing i2c_ee.o(.rev16_text), (4 bytes).
@@ -215,6 +254,10 @@ Removing Unused input sections from the image.
     Removing i2c_ee.o(i.I2C_EE_PageWrite), (160 bytes).
     Removing i2c_ee.o(i.I2C_EE_WaitEepromStandbyState), (84 bytes).
     Removing i2c_ee.o(.data), (2 bytes).
+    Removing sccb.o(.rev16_text), (4 bytes).
+    Removing sccb.o(.revsh_text), (4 bytes).
+    Removing sccb.o(.rrx_text), (6 bytes).
+    Removing sccb.o(i.SCCB_WR_Reg), (62 bytes).
     Removing misc.o(.rev16_text), (4 bytes).
     Removing misc.o(.revsh_text), (4 bytes).
     Removing misc.o(.rrx_text), (6 bytes).
@@ -229,28 +272,55 @@ Removing Unused input sections from the image.
     Removing stm32f10x_dbgmcu.o(i.DBGMCU_Config), (32 bytes).
     Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetDEVID), (16 bytes).
     Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetREVID), (12 bytes).
+    Removing stm32f10x_gpio.o(.rev16_text), (4 bytes).
+    Removing stm32f10x_gpio.o(.revsh_text), (4 bytes).
+    Removing stm32f10x_gpio.o(.rrx_text), (6 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes).
     Removing stm32f10x_i2c.o(.rev16_text), (4 bytes).
     Removing stm32f10x_i2c.o(.revsh_text), (4 bytes).
     Removing stm32f10x_i2c.o(.rrx_text), (6 bytes).
     Removing stm32f10x_i2c.o(i.I2C_ARPCmd), (24 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_AcknowledgeConfig), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_CalculatePEC), (24 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_CheckEvent), (42 bytes).
     Removing stm32f10x_i2c.o(i.I2C_ClearFlag), (12 bytes).
     Removing stm32f10x_i2c.o(i.I2C_ClearITPendingBit), (12 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_Cmd), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_DMACmd), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_DMALastTransferCmd), (24 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_DeInit), (56 bytes).
     Removing stm32f10x_i2c.o(i.I2C_DualAddressCmd), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_FastModeDutyCycleConfig), (28 bytes).
     Removing stm32f10x_i2c.o(i.I2C_GeneralCallCmd), (24 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_GenerateSTART), (24 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_GenerateSTOP), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_GetFlagStatus), (58 bytes).
     Removing stm32f10x_i2c.o(i.I2C_GetITStatus), (38 bytes).
     Removing stm32f10x_i2c.o(i.I2C_GetLastEvent), (26 bytes).
     Removing stm32f10x_i2c.o(i.I2C_GetPEC), (8 bytes).
     Removing stm32f10x_i2c.o(i.I2C_ITConfig), (18 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_Init), (236 bytes).
     Removing stm32f10x_i2c.o(i.I2C_NACKPositionConfig), (28 bytes).
     Removing stm32f10x_i2c.o(i.I2C_OwnAddress2Config), (22 bytes).
     Removing stm32f10x_i2c.o(i.I2C_PECPositionConfig), (28 bytes).
     Removing stm32f10x_i2c.o(i.I2C_ReadRegister), (22 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_ReceiveData), (8 bytes).
     Removing stm32f10x_i2c.o(i.I2C_SMBusAlertConfig), (28 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_Send7bitAddress), (18 bytes).
+    Removing stm32f10x_i2c.o(i.I2C_SendData), (4 bytes).
     Removing stm32f10x_i2c.o(i.I2C_SoftwareResetCmd), (22 bytes).
     Removing stm32f10x_i2c.o(i.I2C_StretchClockCmd), (24 bytes).
     Removing stm32f10x_i2c.o(i.I2C_StructInit), (30 bytes).
@@ -260,6 +330,8 @@ Removing Unused input sections from the image.
     Removing stm32f10x_rcc.o(.rrx_text), (6 bytes).
     Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes).
     Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes).
     Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes).
     Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes).
     Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes).
@@ -267,6 +339,7 @@ Removing Unused input sections from the image.
     Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes).
     Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes).
     Removing stm32f10x_rcc.o(i.RCC_DeInit), (76 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_GetClocksFreq), (212 bytes).
     Removing stm32f10x_rcc.o(i.RCC_GetFlagStatus), (60 bytes).
     Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes).
     Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes).
@@ -286,31 +359,7 @@ Removing Unused input sections from the image.
     Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (24 bytes).
     Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes).
     Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (56 bytes).
-    Removing system_stm32f10x.o(.rev16_text), (4 bytes).
-    Removing system_stm32f10x.o(.revsh_text), (4 bytes).
-    Removing system_stm32f10x.o(.rrx_text), (6 bytes).
-    Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
-    Removing system_stm32f10x.o(.data), (20 bytes).
-    Removing stm32f10x_gpio.o(.rev16_text), (4 bytes).
-    Removing stm32f10x_gpio.o(.revsh_text), (4 bytes).
-    Removing stm32f10x_gpio.o(.rrx_text), (6 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_ResetBits), (4 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_SetBits), (4 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes).
-    Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes).
+    Removing stm32f10x_rcc.o(.data), (20 bytes).
     Removing gpio_stm32f10x.o(.rev16_text), (4 bytes).
     Removing gpio_stm32f10x.o(.revsh_text), (4 bytes).
     Removing gpio_stm32f10x.o(.rrx_text), (6 bytes).
@@ -318,8 +367,13 @@ Removing Unused input sections from the image.
     Removing gpio_stm32f10x.o(i.GPIO_GetPortClockState), (152 bytes).
     Removing gpio_stm32f10x.o(i.GPIO_PinConfigure), (120 bytes).
     Removing gpio_stm32f10x.o(i.GPIO_PortClock), (316 bytes).
+    Removing system_stm32f10x.o(.rev16_text), (4 bytes).
+    Removing system_stm32f10x.o(.revsh_text), (4 bytes).
+    Removing system_stm32f10x.o(.rrx_text), (6 bytes).
+    Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
+    Removing system_stm32f10x.o(.data), (20 bytes).
 
-124 unused section(s) (total 4490 bytes) removed from the image.
+142 unused section(s) (total 5600 bytes) removed from the image.
 
 ==============================================================================
 
@@ -329,51 +383,50 @@ Image Symbol Table
 
     Symbol Name                              Value     Ov Type        Size  Object(Section)
 
-    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit3.o ABSOLUTE
     ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit2.o ABSOLUTE
-    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit1.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit3.o ABSOLUTE
     ../clib/angel/boardlib.s                 0x00000000   Number         0  boardshut.o ABSOLUTE
-    ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_copy.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit1.o ABSOLUTE
     ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_zi.o ABSOLUTE
-    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry.o ABSOLUTE
-    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit2.o ABSOLUTE
-    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry2.o ABSOLUTE
     ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry.o ABSOLUTE
     ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry4.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit2.o ABSOLUTE
     ../clib/angel/rt.s                       0x00000000   Number         0  rt_raise.o ABSOLUTE
     ../clib/angel/scatter.s                  0x00000000   Number         0  __scatter.o ABSOLUTE
     ../clib/angel/startup.s                  0x00000000   Number         0  __main.o ABSOLUTE
-    ../clib/angel/sys.s                      0x00000000   Number         0  sys_stackheap_outer.o ABSOLUTE
     ../clib/angel/sys.s                      0x00000000   Number         0  libspace.o ABSOLUTE
-    ../clib/angel/sys.s                      0x00000000   Number         0  use_no_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  sys_stackheap_outer.o ABSOLUTE
     ../clib/angel/sys.s                      0x00000000   Number         0  indicate_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  use_no_semi.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_command.o ABSOLUTE
     ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_wrch.o ABSOLUTE
     ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_exit.o ABSOLUTE
-    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_command.o ABSOLUTE
     ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
     ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
-    ../clib/armsys.c                         0x00000000   Number         0  _get_argv_nomalloc.o ABSOLUTE
     ../clib/armsys.c                         0x00000000   Number         0  no_argv.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  _get_argv_nomalloc.o ABSOLUTE
     ../clib/heapalloc.c                      0x00000000   Number         0  hrguard.o ABSOLUTE
     ../clib/heapaux.c                        0x00000000   Number         0  heapauxi.o ABSOLUTE
-    ../clib/libinit.s                        0x00000000   Number         0  libshutdown2.o ABSOLUTE
     ../clib/libinit.s                        0x00000000   Number         0  libinit.o ABSOLUTE
-    ../clib/libinit.s                        0x00000000   Number         0  libshutdown.o ABSOLUTE
     ../clib/libinit.s                        0x00000000   Number         0  libinit2.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_outer.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown2.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown.o ABSOLUTE
     ../clib/signal.c                         0x00000000   Number         0  defsig_cppl_inner.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_abrt_inner.o ABSOLUTE
     ../clib/signal.c                         0x00000000   Number         0  defsig_pvfn_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_stak_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtred_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_other.o ABSOLUTE
     ../clib/signal.c                         0x00000000   Number         0  __raise.o ABSOLUTE
     ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_inner.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_exit.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_rtred_inner.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_formal.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_segv_inner.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_other.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_stak_inner.o ABSOLUTE
-    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_inner.o ABSOLUTE
     ../clib/signal.c                         0x00000000   Number         0  defsig_general.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_outer.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_formal.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_exit.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_abrt_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_segv_inner.o ABSOLUTE
     ../clib/signal.s                         0x00000000   Number         0  defsig.o ABSOLUTE
     ../clib/stdlib.c                         0x00000000   Number         0  exit.o ABSOLUTE
     ../fplib/fpinit.s                        0x00000000   Number         0  fpinit.o ABSOLUTE
@@ -393,6 +446,8 @@ Image Symbol Table
     RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
     RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
     dc.s                                     0x00000000   Number         0  dc.o ABSOLUTE
+    sccb.c                                   0x00000000   Number         0  sccb.o ABSOLUTE
+    sccb.c                                   0x00000000   Number         0  sccb.o ABSOLUTE
     src\\i2c_ee.c                            0x00000000   Number         0  i2c_ee.o ABSOLUTE
     src\\main.c                              0x00000000   Number         0  main.o ABSOLUTE
     src\\stm32f10x_it.c                      0x00000000   Number         0  stm32f10x_it.o ABSOLUTE
@@ -402,100 +457,93 @@ Image Symbol Table
     RESET                                    0x08000000   Section      236  startup_stm32f10x_md.o(RESET)
     !!!main                                  0x080000ec   Section        8  __main.o(!!!main)
     !!!scatter                               0x080000f4   Section       52  __scatter.o(!!!scatter)
-    !!handler_copy                           0x08000128   Section       26  __scatter_copy.o(!!handler_copy)
-    !!handler_zi                             0x08000144   Section       28  __scatter_zi.o(!!handler_zi)
-    .ARM.Collect$$libinit$$00000000          0x08000160   Section        2  libinit.o(.ARM.Collect$$libinit$$00000000)
-    .ARM.Collect$$libinit$$00000002          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000002)
-    .ARM.Collect$$libinit$$00000004          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000004)
-    .ARM.Collect$$libinit$$0000000A          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
-    .ARM.Collect$$libinit$$0000000C          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
-    .ARM.Collect$$libinit$$0000000E          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
-    .ARM.Collect$$libinit$$00000011          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000011)
-    .ARM.Collect$$libinit$$00000013          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000013)
-    .ARM.Collect$$libinit$$00000015          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000015)
-    .ARM.Collect$$libinit$$00000017          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000017)
-    .ARM.Collect$$libinit$$00000019          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000019)
-    .ARM.Collect$$libinit$$0000001B          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
-    .ARM.Collect$$libinit$$0000001D          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
-    .ARM.Collect$$libinit$$0000001F          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
-    .ARM.Collect$$libinit$$00000021          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000021)
-    .ARM.Collect$$libinit$$00000023          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000023)
-    .ARM.Collect$$libinit$$00000025          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000025)
-    .ARM.Collect$$libinit$$0000002C          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
-    .ARM.Collect$$libinit$$0000002E          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
-    .ARM.Collect$$libinit$$00000030          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000030)
-    .ARM.Collect$$libinit$$00000032          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000032)
-    .ARM.Collect$$libinit$$00000033          0x08000162   Section        2  libinit2.o(.ARM.Collect$$libinit$$00000033)
-    .ARM.Collect$$libshutdown$$00000000      0x08000164   Section        2  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
-    .ARM.Collect$$libshutdown$$00000002      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
-    .ARM.Collect$$libshutdown$$00000004      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
-    .ARM.Collect$$libshutdown$$00000007      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
-    .ARM.Collect$$libshutdown$$0000000A      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
-    .ARM.Collect$$libshutdown$$0000000C      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
-    .ARM.Collect$$libshutdown$$0000000F      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
-    .ARM.Collect$$libshutdown$$00000010      0x08000166   Section        2  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
-    .ARM.Collect$$rtentry$$00000000          0x08000168   Section        0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
-    .ARM.Collect$$rtentry$$00000002          0x08000168   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
-    .ARM.Collect$$rtentry$$00000004          0x08000168   Section        6  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
-    .ARM.Collect$$rtentry$$00000009          0x0800016e   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
-    .ARM.Collect$$rtentry$$0000000A          0x0800016e   Section        4  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
-    .ARM.Collect$$rtentry$$0000000C          0x08000172   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
-    .ARM.Collect$$rtentry$$0000000D          0x08000172   Section        8  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
-    .ARM.Collect$$rtexit$$00000000           0x0800017a   Section        2  rtexit.o(.ARM.Collect$$rtexit$$00000000)
-    .ARM.Collect$$rtexit$$00000002           0x0800017c   Section        0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
-    .ARM.Collect$$rtexit$$00000003           0x0800017c   Section        4  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
-    .ARM.Collect$$rtexit$$00000004           0x08000180   Section        6  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
-    .text                                    0x08000188   Section       64  startup_stm32f10x_md.o(.text)
-    .text                                    0x080001c8   Section        0  heapauxi.o(.text)
-    .text                                    0x080001ce   Section       74  sys_stackheap_outer.o(.text)
-    .text                                    0x08000218   Section        0  exit.o(.text)
-    .text                                    0x0800022c   Section        8  libspace.o(.text)
-    .text                                    0x08000234   Section        0  sys_exit.o(.text)
-    .text                                    0x08000240   Section        2  use_no_semi.o(.text)
-    .text                                    0x08000242   Section        0  indicate_semi.o(.text)
-    i.BusFault_Handler                       0x08000242   Section        0  stm32f10x_it.o(i.BusFault_Handler)
-    i.DebugMon_Handler                       0x08000246   Section        0  stm32f10x_it.o(i.DebugMon_Handler)
-    i.GPIO_Init                              0x08000248   Section        0  stm32f10x_gpio.o(i.GPIO_Init)
-    i.HardFault_Handler                      0x0800035e   Section        0  stm32f10x_it.o(i.HardFault_Handler)
-    i.I2C1_Init                              0x08000364   Section        0  main.o(i.I2C1_Init)
-    i.I2C1_Read                              0x080003b4   Section        0  main.o(i.I2C1_Read)
-    i.I2C_AcknowledgeConfig                  0x08000468   Section        0  stm32f10x_i2c.o(i.I2C_AcknowledgeConfig)
-    i.I2C_CheckEvent                         0x08000480   Section        0  stm32f10x_i2c.o(i.I2C_CheckEvent)
-    i.I2C_Cmd                                0x080004aa   Section        0  stm32f10x_i2c.o(i.I2C_Cmd)
-    i.I2C_DeInit                             0x080004c4   Section        0  stm32f10x_i2c.o(i.I2C_DeInit)
-    i.I2C_GPIO_Config                        0x080004fc   Section        0  main.o(i.I2C_GPIO_Config)
-    i.I2C_GenerateSTART                      0x08000528   Section        0  stm32f10x_i2c.o(i.I2C_GenerateSTART)
-    i.I2C_GenerateSTOP                       0x08000540   Section        0  stm32f10x_i2c.o(i.I2C_GenerateSTOP)
-    i.I2C_Init                               0x08000558   Section        0  stm32f10x_i2c.o(i.I2C_Init)
-    i.I2C_ReceiveData                        0x08000644   Section        0  stm32f10x_i2c.o(i.I2C_ReceiveData)
-    i.I2C_Send7bitAddress                    0x0800064c   Section        0  stm32f10x_i2c.o(i.I2C_Send7bitAddress)
-    i.I2C_SendData                           0x0800065e   Section        0  stm32f10x_i2c.o(i.I2C_SendData)
-    i.MemManage_Handler                      0x08000662   Section        0  stm32f10x_it.o(i.MemManage_Handler)
-    i.NMI_Handler                            0x08000666   Section        0  stm32f10x_it.o(i.NMI_Handler)
-    i.PendSV_Handler                         0x08000668   Section        0  stm32f10x_it.o(i.PendSV_Handler)
-    i.RCC_APB1PeriphClockCmd                 0x0800066c   Section        0  stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd)
-    i.RCC_APB1PeriphResetCmd                 0x0800068c   Section        0  stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd)
-    i.RCC_APB2PeriphClockCmd                 0x080006ac   Section        0  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
-    i.RCC_Configuration                      0x080006cc   Section        0  main.o(i.RCC_Configuration)
-    i.RCC_GetClocksFreq                      0x080006d4   Section        0  stm32f10x_rcc.o(i.RCC_GetClocksFreq)
-    i.SVC_Handler                            0x080007a8   Section        0  stm32f10x_it.o(i.SVC_Handler)
-    i.SetSysClock                            0x080007aa   Section        0  system_stm32f10x.o(i.SetSysClock)
-    SetSysClock                              0x080007ab   Thumb Code     8  system_stm32f10x.o(i.SetSysClock)
-    i.SetSysClockTo72                        0x080007b4   Section        0  system_stm32f10x.o(i.SetSysClockTo72)
-    SetSysClockTo72                          0x080007b5   Thumb Code   214  system_stm32f10x.o(i.SetSysClockTo72)
-    i.SysTick_Handler                        0x08000894   Section        0  stm32f10x_it.o(i.SysTick_Handler)
-    i.SystemInit                             0x08000898   Section        0  system_stm32f10x.o(i.SystemInit)
-    i.UsageFault_Handler                     0x080008f8   Section        0  stm32f10x_it.o(i.UsageFault_Handler)
-    i.main                                   0x080008fc   Section        0  main.o(i.main)
-    .data                                    0x20000000   Section       20  stm32f10x_rcc.o(.data)
-    APBAHBPrescTable                         0x20000000   Data          16  stm32f10x_rcc.o(.data)
-    ADCPrescTable                            0x20000010   Data           4  stm32f10x_rcc.o(.data)
-    .bss                                     0x20000014   Section       96  libspace.o(.bss)
-    HEAP                                     0x20000078   Section      512  startup_stm32f10x_md.o(HEAP)
-    Heap_Mem                                 0x20000078   Data         512  startup_stm32f10x_md.o(HEAP)
-    STACK                                    0x20000278   Section     1024  startup_stm32f10x_md.o(STACK)
-    Stack_Mem                                0x20000278   Data        1024  startup_stm32f10x_md.o(STACK)
-    __initial_sp                             0x20000678   Data           0  startup_stm32f10x_md.o(STACK)
+    !!handler_zi                             0x08000128   Section       28  __scatter_zi.o(!!handler_zi)
+    .ARM.Collect$$libinit$$00000000          0x08000144   Section        2  libinit.o(.ARM.Collect$$libinit$$00000000)
+    .ARM.Collect$$libinit$$00000002          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000002)
+    .ARM.Collect$$libinit$$00000004          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000004)
+    .ARM.Collect$$libinit$$0000000A          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
+    .ARM.Collect$$libinit$$0000000C          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
+    .ARM.Collect$$libinit$$0000000E          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
+    .ARM.Collect$$libinit$$00000011          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000011)
+    .ARM.Collect$$libinit$$00000013          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000013)
+    .ARM.Collect$$libinit$$00000015          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000015)
+    .ARM.Collect$$libinit$$00000017          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000017)
+    .ARM.Collect$$libinit$$00000019          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000019)
+    .ARM.Collect$$libinit$$0000001B          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
+    .ARM.Collect$$libinit$$0000001D          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
+    .ARM.Collect$$libinit$$0000001F          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
+    .ARM.Collect$$libinit$$00000021          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000021)
+    .ARM.Collect$$libinit$$00000023          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000023)
+    .ARM.Collect$$libinit$$00000025          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000025)
+    .ARM.Collect$$libinit$$0000002C          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
+    .ARM.Collect$$libinit$$0000002E          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
+    .ARM.Collect$$libinit$$00000030          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000030)
+    .ARM.Collect$$libinit$$00000032          0x08000146   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000032)
+    .ARM.Collect$$libinit$$00000033          0x08000146   Section        2  libinit2.o(.ARM.Collect$$libinit$$00000033)
+    .ARM.Collect$$libshutdown$$00000000      0x08000148   Section        2  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+    .ARM.Collect$$libshutdown$$00000002      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+    .ARM.Collect$$libshutdown$$00000004      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+    .ARM.Collect$$libshutdown$$00000007      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+    .ARM.Collect$$libshutdown$$0000000A      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+    .ARM.Collect$$libshutdown$$0000000C      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+    .ARM.Collect$$libshutdown$$0000000F      0x0800014a   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+    .ARM.Collect$$libshutdown$$00000010      0x0800014a   Section        2  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+    .ARM.Collect$$rtentry$$00000000          0x0800014c   Section        0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+    .ARM.Collect$$rtentry$$00000002          0x0800014c   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+    .ARM.Collect$$rtentry$$00000004          0x0800014c   Section        6  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+    .ARM.Collect$$rtentry$$00000009          0x08000152   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+    .ARM.Collect$$rtentry$$0000000A          0x08000152   Section        4  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+    .ARM.Collect$$rtentry$$0000000C          0x08000156   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+    .ARM.Collect$$rtentry$$0000000D          0x08000156   Section        8  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+    .ARM.Collect$$rtexit$$00000000           0x0800015e   Section        2  rtexit.o(.ARM.Collect$$rtexit$$00000000)
+    .ARM.Collect$$rtexit$$00000002           0x08000160   Section        0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+    .ARM.Collect$$rtexit$$00000003           0x08000160   Section        4  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+    .ARM.Collect$$rtexit$$00000004           0x08000164   Section        6  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+    .text                                    0x0800016c   Section       64  startup_stm32f10x_md.o(.text)
+    .text                                    0x080001ac   Section        0  heapauxi.o(.text)
+    .text                                    0x080001b2   Section       74  sys_stackheap_outer.o(.text)
+    .text                                    0x080001fc   Section        0  exit.o(.text)
+    .text                                    0x08000210   Section        8  libspace.o(.text)
+    .text                                    0x08000218   Section        0  sys_exit.o(.text)
+    .text                                    0x08000224   Section        2  use_no_semi.o(.text)
+    .text                                    0x08000226   Section        0  indicate_semi.o(.text)
+    i.BusFault_Handler                       0x08000226   Section        0  stm32f10x_it.o(i.BusFault_Handler)
+    i.DebugMon_Handler                       0x0800022a   Section        0  stm32f10x_it.o(i.DebugMon_Handler)
+    i.GPIO_Init                              0x0800022c   Section        0  stm32f10x_gpio.o(i.GPIO_Init)
+    i.GPIO_ReadInputDataBit                  0x08000342   Section        0  stm32f10x_gpio.o(i.GPIO_ReadInputDataBit)
+    i.GPIO_ResetBits                         0x08000354   Section        0  stm32f10x_gpio.o(i.GPIO_ResetBits)
+    i.GPIO_SetBits                           0x08000358   Section        0  stm32f10x_gpio.o(i.GPIO_SetBits)
+    i.HardFault_Handler                      0x0800035c   Section        0  stm32f10x_it.o(i.HardFault_Handler)
+    i.MemManage_Handler                      0x08000360   Section        0  stm32f10x_it.o(i.MemManage_Handler)
+    i.NMI_Handler                            0x08000364   Section        0  stm32f10x_it.o(i.NMI_Handler)
+    i.PendSV_Handler                         0x08000366   Section        0  stm32f10x_it.o(i.PendSV_Handler)
+    i.RCC_APB2PeriphClockCmd                 0x08000368   Section        0  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
+    i.RCC_Configuration                      0x08000388   Section        0  main.o(i.RCC_Configuration)
+    i.SCCB_Init                              0x08000390   Section        0  sccb.o(i.SCCB_Init)
+    i.SCCB_No_Ack                            0x080003e0   Section        0  sccb.o(i.SCCB_No_Ack)
+    i.SCCB_RD_Byte                           0x08000420   Section        0  sccb.o(i.SCCB_RD_Byte)
+    i.SCCB_RD_Reg                            0x08000470   Section        0  sccb.o(i.SCCB_RD_Reg)
+    i.SCCB_SDA_IN                            0x080004c0   Section        0  sccb.o(i.SCCB_SDA_IN)
+    i.SCCB_SDA_OUT                           0x080004e4   Section        0  sccb.o(i.SCCB_SDA_OUT)
+    i.SCCB_Start                             0x08000508   Section        0  sccb.o(i.SCCB_Start)
+    i.SCCB_Stop                              0x0800053c   Section        0  sccb.o(i.SCCB_Stop)
+    i.SCCB_WR_Byte                           0x08000570   Section        0  sccb.o(i.SCCB_WR_Byte)
+    i.SVC_Handler                            0x080005f4   Section        0  stm32f10x_it.o(i.SVC_Handler)
+    i.SetSysClock                            0x080005f6   Section        0  system_stm32f10x.o(i.SetSysClock)
+    SetSysClock                              0x080005f7   Thumb Code     8  system_stm32f10x.o(i.SetSysClock)
+    i.SetSysClockTo72                        0x08000600   Section        0  system_stm32f10x.o(i.SetSysClockTo72)
+    SetSysClockTo72                          0x08000601   Thumb Code   214  system_stm32f10x.o(i.SetSysClockTo72)
+    i.SysTick_Handler                        0x080006e0   Section        0  stm32f10x_it.o(i.SysTick_Handler)
+    i.SystemInit                             0x080006e4   Section        0  system_stm32f10x.o(i.SystemInit)
+    i.UsageFault_Handler                     0x08000744   Section        0  stm32f10x_it.o(i.UsageFault_Handler)
+    i.delay_us                               0x08000748   Section        0  sccb.o(i.delay_us)
+    i.main                                   0x08000762   Section        0  main.o(i.main)
+    .bss                                     0x20000000   Section       96  libspace.o(.bss)
+    HEAP                                     0x20000060   Section      512  startup_stm32f10x_md.o(HEAP)
+    Heap_Mem                                 0x20000060   Data         512  startup_stm32f10x_md.o(HEAP)
+    STACK                                    0x20000260   Section     1024  startup_stm32f10x_md.o(STACK)
+    Stack_Mem                                0x20000260   Data        1024  startup_stm32f10x_md.o(STACK)
+    __initial_sp                             0x20000660   Data           0  startup_stm32f10x_md.o(STACK)
 
     Global Symbols
 
@@ -539,140 +587,136 @@ Image Symbol Table
     __scatterload_rt2                        0x080000f5   Thumb Code    44  __scatter.o(!!!scatter)
     __scatterload_rt2_thumb_only             0x080000f5   Thumb Code     0  __scatter.o(!!!scatter)
     __scatterload_null                       0x08000103   Thumb Code     0  __scatter.o(!!!scatter)
-    __scatterload_copy                       0x08000129   Thumb Code    26  __scatter_copy.o(!!handler_copy)
-    __scatterload_zeroinit                   0x08000145   Thumb Code    28  __scatter_zi.o(!!handler_zi)
-    __rt_lib_init                            0x08000161   Thumb Code     0  libinit.o(.ARM.Collect$$libinit$$00000000)
-    __rt_lib_init_alloca_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
-    __rt_lib_init_argv_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
-    __rt_lib_init_atexit_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
-    __rt_lib_init_clock_1                    0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000021)
-    __rt_lib_init_cpp_1                      0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000032)
-    __rt_lib_init_exceptions_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000030)
-    __rt_lib_init_fp_1                       0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000002)
-    __rt_lib_init_fp_trap_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
-    __rt_lib_init_getenv_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000023)
-    __rt_lib_init_heap_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
-    __rt_lib_init_lc_collate_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000011)
-    __rt_lib_init_lc_ctype_1                 0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000013)
-    __rt_lib_init_lc_monetary_1              0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000015)
-    __rt_lib_init_lc_numeric_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000017)
-    __rt_lib_init_lc_time_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000019)
-    __rt_lib_init_preinit_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000004)
-    __rt_lib_init_rand_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
-    __rt_lib_init_return                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000033)
-    __rt_lib_init_signal_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
-    __rt_lib_init_stdio_1                    0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000025)
-    __rt_lib_init_user_alloc_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
-    __rt_lib_shutdown                        0x08000165   Thumb Code     0  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
-    __rt_lib_shutdown_cpp_1                  0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
-    __rt_lib_shutdown_fp_trap_1              0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
-    __rt_lib_shutdown_heap_1                 0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
-    __rt_lib_shutdown_return                 0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
-    __rt_lib_shutdown_signal_1               0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
-    __rt_lib_shutdown_stdio_1                0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
-    __rt_lib_shutdown_user_alloc_1           0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
-    __rt_entry                               0x08000169   Thumb Code     0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
-    __rt_entry_presh_1                       0x08000169   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
-    __rt_entry_sh                            0x08000169   Thumb Code     0  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
-    __rt_entry_li                            0x0800016f   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
-    __rt_entry_postsh_1                      0x0800016f   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
-    __rt_entry_main                          0x08000173   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
-    __rt_entry_postli_1                      0x08000173   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
-    __rt_exit                                0x0800017b   Thumb Code     0  rtexit.o(.ARM.Collect$$rtexit$$00000000)
-    __rt_exit_ls                             0x0800017d   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
-    __rt_exit_prels_1                        0x0800017d   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
-    __rt_exit_exit                           0x08000181   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
-    Reset_Handler                            0x08000189   Thumb Code     8  startup_stm32f10x_md.o(.text)
-    ADC1_2_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    CAN1_RX1_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    CAN1_SCE_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel1_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel2_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel3_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel4_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel5_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel6_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    DMA1_Channel7_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI0_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI15_10_IRQHandler                     0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI1_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI2_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI3_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI4_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    EXTI9_5_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    FLASH_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    I2C1_ER_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    I2C1_EV_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    I2C2_ER_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    I2C2_EV_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    PVD_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    RCC_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    RTCAlarm_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    RTC_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    SPI1_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    SPI2_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TAMPER_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM1_BRK_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM1_CC_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM1_TRG_COM_IRQHandler                  0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM1_UP_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM2_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM3_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    TIM4_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USART1_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USART2_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USART3_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USBWakeUp_IRQHandler                     0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USB_HP_CAN1_TX_IRQHandler                0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    USB_LP_CAN1_RX0_IRQHandler               0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    WWDG_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    __user_initial_stackheap                 0x080001a5   Thumb Code     0  startup_stm32f10x_md.o(.text)
-    __use_two_region_memory                  0x080001c9   Thumb Code     2  heapauxi.o(.text)
-    __rt_heap_escrow$2region                 0x080001cb   Thumb Code     2  heapauxi.o(.text)
-    __rt_heap_expand$2region                 0x080001cd   Thumb Code     2  heapauxi.o(.text)
-    __user_setup_stackheap                   0x080001cf   Thumb Code    74  sys_stackheap_outer.o(.text)
-    exit                                     0x08000219   Thumb Code    18  exit.o(.text)
-    __user_libspace                          0x0800022d   Thumb Code     8  libspace.o(.text)
-    __user_perproc_libspace                  0x0800022d   Thumb Code     0  libspace.o(.text)
-    __user_perthread_libspace                0x0800022d   Thumb Code     0  libspace.o(.text)
-    _sys_exit                                0x08000235   Thumb Code     8  sys_exit.o(.text)
-    __I$use$semihosting                      0x08000241   Thumb Code     0  use_no_semi.o(.text)
-    __use_no_semihosting_swi                 0x08000241   Thumb Code     2  use_no_semi.o(.text)
-    BusFault_Handler                         0x08000243   Thumb Code     4  stm32f10x_it.o(i.BusFault_Handler)
-    __semihosting_library_function           0x08000243   Thumb Code     0  indicate_semi.o(.text)
-    DebugMon_Handler                         0x08000247   Thumb Code     2  stm32f10x_it.o(i.DebugMon_Handler)
-    GPIO_Init                                0x08000249   Thumb Code   278  stm32f10x_gpio.o(i.GPIO_Init)
-    HardFault_Handler                        0x0800035f   Thumb Code     4  stm32f10x_it.o(i.HardFault_Handler)
-    I2C1_Init                                0x08000365   Thumb Code    74  main.o(i.I2C1_Init)
-    I2C1_Read                                0x080003b5   Thumb Code   168  main.o(i.I2C1_Read)
-    I2C_AcknowledgeConfig                    0x08000469   Thumb Code    24  stm32f10x_i2c.o(i.I2C_AcknowledgeConfig)
-    I2C_CheckEvent                           0x08000481   Thumb Code    42  stm32f10x_i2c.o(i.I2C_CheckEvent)
-    I2C_Cmd                                  0x080004ab   Thumb Code    24  stm32f10x_i2c.o(i.I2C_Cmd)
-    I2C_DeInit                               0x080004c5   Thumb Code    50  stm32f10x_i2c.o(i.I2C_DeInit)
-    I2C_GPIO_Config                          0x080004fd   Thumb Code    38  main.o(i.I2C_GPIO_Config)
-    I2C_GenerateSTART                        0x08000529   Thumb Code    24  stm32f10x_i2c.o(i.I2C_GenerateSTART)
-    I2C_GenerateSTOP                         0x08000541   Thumb Code    24  stm32f10x_i2c.o(i.I2C_GenerateSTOP)
-    I2C_Init                                 0x08000559   Thumb Code   222  stm32f10x_i2c.o(i.I2C_Init)
-    I2C_ReceiveData                          0x08000645   Thumb Code     8  stm32f10x_i2c.o(i.I2C_ReceiveData)
-    I2C_Send7bitAddress                      0x0800064d   Thumb Code    18  stm32f10x_i2c.o(i.I2C_Send7bitAddress)
-    I2C_SendData                             0x0800065f   Thumb Code     4  stm32f10x_i2c.o(i.I2C_SendData)
-    MemManage_Handler                        0x08000663   Thumb Code     4  stm32f10x_it.o(i.MemManage_Handler)
-    NMI_Handler                              0x08000667   Thumb Code     2  stm32f10x_it.o(i.NMI_Handler)
-    PendSV_Handler                           0x08000669   Thumb Code     2  stm32f10x_it.o(i.PendSV_Handler)
-    RCC_APB1PeriphClockCmd                   0x0800066d   Thumb Code    26  stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd)
-    RCC_APB1PeriphResetCmd                   0x0800068d   Thumb Code    26  stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd)
-    RCC_APB2PeriphClockCmd                   0x080006ad   Thumb Code    26  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
-    RCC_Configuration                        0x080006cd   Thumb Code     8  main.o(i.RCC_Configuration)
-    RCC_GetClocksFreq                        0x080006d5   Thumb Code   192  stm32f10x_rcc.o(i.RCC_GetClocksFreq)
-    SVC_Handler                              0x080007a9   Thumb Code     2  stm32f10x_it.o(i.SVC_Handler)
-    SysTick_Handler                          0x08000895   Thumb Code     2  stm32f10x_it.o(i.SysTick_Handler)
-    SystemInit                               0x08000899   Thumb Code    78  system_stm32f10x.o(i.SystemInit)
-    UsageFault_Handler                       0x080008f9   Thumb Code     4  stm32f10x_it.o(i.UsageFault_Handler)
-    main                                     0x080008fd   Thumb Code    22  main.o(i.main)
-    Region$$Table$$Base                      0x08000914   Number         0  anon$$obj.o(Region$$Table)
-    Region$$Table$$Limit                     0x08000934   Number         0  anon$$obj.o(Region$$Table)
-    __libspace_start                         0x20000014   Data          96  libspace.o(.bss)
-    __temporary_stack_top$libspace           0x20000074   Data           0  libspace.o(.bss)
+    __scatterload_zeroinit                   0x08000129   Thumb Code    28  __scatter_zi.o(!!handler_zi)
+    __rt_lib_init                            0x08000145   Thumb Code     0  libinit.o(.ARM.Collect$$libinit$$00000000)
+    __rt_lib_init_alloca_1                   0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
+    __rt_lib_init_argv_1                     0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
+    __rt_lib_init_atexit_1                   0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
+    __rt_lib_init_clock_1                    0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000021)
+    __rt_lib_init_cpp_1                      0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000032)
+    __rt_lib_init_exceptions_1               0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000030)
+    __rt_lib_init_fp_1                       0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000002)
+    __rt_lib_init_fp_trap_1                  0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
+    __rt_lib_init_getenv_1                   0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000023)
+    __rt_lib_init_heap_1                     0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
+    __rt_lib_init_lc_collate_1               0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000011)
+    __rt_lib_init_lc_ctype_1                 0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000013)
+    __rt_lib_init_lc_monetary_1              0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000015)
+    __rt_lib_init_lc_numeric_1               0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000017)
+    __rt_lib_init_lc_time_1                  0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000019)
+    __rt_lib_init_preinit_1                  0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000004)
+    __rt_lib_init_rand_1                     0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
+    __rt_lib_init_return                     0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000033)
+    __rt_lib_init_signal_1                   0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
+    __rt_lib_init_stdio_1                    0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000025)
+    __rt_lib_init_user_alloc_1               0x08000147   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
+    __rt_lib_shutdown                        0x08000149   Thumb Code     0  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+    __rt_lib_shutdown_cpp_1                  0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+    __rt_lib_shutdown_fp_trap_1              0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+    __rt_lib_shutdown_heap_1                 0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+    __rt_lib_shutdown_return                 0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+    __rt_lib_shutdown_signal_1               0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+    __rt_lib_shutdown_stdio_1                0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+    __rt_lib_shutdown_user_alloc_1           0x0800014b   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+    __rt_entry                               0x0800014d   Thumb Code     0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+    __rt_entry_presh_1                       0x0800014d   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+    __rt_entry_sh                            0x0800014d   Thumb Code     0  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+    __rt_entry_li                            0x08000153   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+    __rt_entry_postsh_1                      0x08000153   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+    __rt_entry_main                          0x08000157   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+    __rt_entry_postli_1                      0x08000157   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+    __rt_exit                                0x0800015f   Thumb Code     0  rtexit.o(.ARM.Collect$$rtexit$$00000000)
+    __rt_exit_ls                             0x08000161   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+    __rt_exit_prels_1                        0x08000161   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+    __rt_exit_exit                           0x08000165   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+    Reset_Handler                            0x0800016d   Thumb Code     8  startup_stm32f10x_md.o(.text)
+    ADC1_2_IRQHandler                        0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    CAN1_RX1_IRQHandler                      0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    CAN1_SCE_IRQHandler                      0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel1_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel2_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel3_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel4_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel5_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel6_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel7_IRQHandler                 0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI0_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI15_10_IRQHandler                     0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI1_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI2_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI3_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI4_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI9_5_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    FLASH_IRQHandler                         0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C1_ER_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C1_EV_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C2_ER_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C2_EV_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    PVD_IRQHandler                           0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RCC_IRQHandler                           0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RTCAlarm_IRQHandler                      0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RTC_IRQHandler                           0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    SPI1_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    SPI2_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TAMPER_IRQHandler                        0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_BRK_IRQHandler                      0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_CC_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_TRG_COM_IRQHandler                  0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_UP_IRQHandler                       0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM2_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM3_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM4_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART1_IRQHandler                        0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART2_IRQHandler                        0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART3_IRQHandler                        0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USBWakeUp_IRQHandler                     0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USB_HP_CAN1_TX_IRQHandler                0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USB_LP_CAN1_RX0_IRQHandler               0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    WWDG_IRQHandler                          0x08000187   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    __user_initial_stackheap                 0x08000189   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    __use_two_region_memory                  0x080001ad   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_escrow$2region                 0x080001af   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_expand$2region                 0x080001b1   Thumb Code     2  heapauxi.o(.text)
+    __user_setup_stackheap                   0x080001b3   Thumb Code    74  sys_stackheap_outer.o(.text)
+    exit                                     0x080001fd   Thumb Code    18  exit.o(.text)
+    __user_libspace                          0x08000211   Thumb Code     8  libspace.o(.text)
+    __user_perproc_libspace                  0x08000211   Thumb Code     0  libspace.o(.text)
+    __user_perthread_libspace                0x08000211   Thumb Code     0  libspace.o(.text)
+    _sys_exit                                0x08000219   Thumb Code     8  sys_exit.o(.text)
+    __I$use$semihosting                      0x08000225   Thumb Code     0  use_no_semi.o(.text)
+    __use_no_semihosting_swi                 0x08000225   Thumb Code     2  use_no_semi.o(.text)
+    BusFault_Handler                         0x08000227   Thumb Code     4  stm32f10x_it.o(i.BusFault_Handler)
+    __semihosting_library_function           0x08000227   Thumb Code     0  indicate_semi.o(.text)
+    DebugMon_Handler                         0x0800022b   Thumb Code     2  stm32f10x_it.o(i.DebugMon_Handler)
+    GPIO_Init                                0x0800022d   Thumb Code   278  stm32f10x_gpio.o(i.GPIO_Init)
+    GPIO_ReadInputDataBit                    0x08000343   Thumb Code    18  stm32f10x_gpio.o(i.GPIO_ReadInputDataBit)
+    GPIO_ResetBits                           0x08000355   Thumb Code     4  stm32f10x_gpio.o(i.GPIO_ResetBits)
+    GPIO_SetBits                             0x08000359   Thumb Code     4  stm32f10x_gpio.o(i.GPIO_SetBits)
+    HardFault_Handler                        0x0800035d   Thumb Code     4  stm32f10x_it.o(i.HardFault_Handler)
+    MemManage_Handler                        0x08000361   Thumb Code     4  stm32f10x_it.o(i.MemManage_Handler)
+    NMI_Handler                              0x08000365   Thumb Code     2  stm32f10x_it.o(i.NMI_Handler)
+    PendSV_Handler                           0x08000367   Thumb Code     2  stm32f10x_it.o(i.PendSV_Handler)
+    RCC_APB2PeriphClockCmd                   0x08000369   Thumb Code    26  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
+    RCC_Configuration                        0x08000389   Thumb Code     8  main.o(i.RCC_Configuration)
+    SCCB_Init                                0x08000391   Thumb Code    76  sccb.o(i.SCCB_Init)
+    SCCB_No_Ack                              0x080003e1   Thumb Code    60  sccb.o(i.SCCB_No_Ack)
+    SCCB_RD_Byte                             0x08000421   Thumb Code    74  sccb.o(i.SCCB_RD_Byte)
+    SCCB_RD_Reg                              0x08000471   Thumb Code    78  sccb.o(i.SCCB_RD_Reg)
+    SCCB_SDA_IN                              0x080004c1   Thumb Code    30  sccb.o(i.SCCB_SDA_IN)
+    SCCB_SDA_OUT                             0x080004e5   Thumb Code    30  sccb.o(i.SCCB_SDA_OUT)
+    SCCB_Start                               0x08000509   Thumb Code    48  sccb.o(i.SCCB_Start)
+    SCCB_Stop                                0x0800053d   Thumb Code    46  sccb.o(i.SCCB_Stop)
+    SCCB_WR_Byte                             0x08000571   Thumb Code   128  sccb.o(i.SCCB_WR_Byte)
+    SVC_Handler                              0x080005f5   Thumb Code     2  stm32f10x_it.o(i.SVC_Handler)
+    SysTick_Handler                          0x080006e1   Thumb Code     2  stm32f10x_it.o(i.SysTick_Handler)
+    SystemInit                               0x080006e5   Thumb Code    78  system_stm32f10x.o(i.SystemInit)
+    UsageFault_Handler                       0x08000745   Thumb Code     4  stm32f10x_it.o(i.UsageFault_Handler)
+    delay_us                                 0x08000749   Thumb Code    26  sccb.o(i.delay_us)
+    main                                     0x08000763   Thumb Code    40  main.o(i.main)
+    Region$$Table$$Base                      0x0800078c   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x0800079c   Number         0  anon$$obj.o(Region$$Table)
+    __libspace_start                         0x20000000   Data          96  libspace.o(.bss)
+    __temporary_stack_top$libspace           0x20000060   Data           0  libspace.o(.bss)
 
 
 
@@ -680,127 +724,117 @@ Image Symbol Table
 
 Memory Map of the image
 
-  Image Entry point : 0x08000189
+  Image Entry point : 0x0800016d
 
-  Load Region LR_1 (Base: 0x08000000, Size: 0x00000948, Max: 0xffffffff, ABSOLUTE)
+  Load Region LR_1 (Base: 0x08000000, Size: 0x0000079c, Max: 0xffffffff, ABSOLUTE)
 
-    Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000934, Max: 0xffffffff, ABSOLUTE)
+    Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000079c, Max: 0xffffffff, ABSOLUTE)
 
     Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
 
-    0x08000000   0x08000000   0x000000ec   Data   RO          767    RESET               startup_stm32f10x_md.o
-    0x080000ec   0x080000ec   0x00000008   Code   RO          996  * !!!main             c_w.l(__main.o)
-    0x080000f4   0x080000f4   0x00000034   Code   RO         1153    !!!scatter          c_w.l(__scatter.o)
-    0x08000128   0x08000128   0x0000001a   Code   RO         1155    !!handler_copy      c_w.l(__scatter_copy.o)
-    0x08000142   0x08000142   0x00000002   PAD
-    0x08000144   0x08000144   0x0000001c   Code   RO         1157    !!handler_zi        c_w.l(__scatter_zi.o)
-    0x08000160   0x08000160   0x00000002   Code   RO         1023    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1030    .ARM.Collect$$libinit$$00000002  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1032    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1035    .ARM.Collect$$libinit$$0000000A  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1037    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1039    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1042    .ARM.Collect$$libinit$$00000011  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1044    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1046    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1048    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1050    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1052    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1054    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1056    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1058    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1060    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1062    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1066    .ARM.Collect$$libinit$$0000002C  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1068    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1070    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000000   Code   RO         1072    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
-    0x08000162   0x08000162   0x00000002   Code   RO         1073    .ARM.Collect$$libinit$$00000033  c_w.l(libinit2.o)
-    0x08000164   0x08000164   0x00000002   Code   RO         1093    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1106    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1108    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1111    .ARM.Collect$$libshutdown$$00000007  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1114    .ARM.Collect$$libshutdown$$0000000A  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1116    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000000   Code   RO         1119    .ARM.Collect$$libshutdown$$0000000F  c_w.l(libshutdown2.o)
-    0x08000166   0x08000166   0x00000002   Code   RO         1120    .ARM.Collect$$libshutdown$$00000010  c_w.l(libshutdown2.o)
-    0x08000168   0x08000168   0x00000000   Code   RO          998    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
-    0x08000168   0x08000168   0x00000000   Code   RO         1000    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
-    0x08000168   0x08000168   0x00000006   Code   RO         1012    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
-    0x0800016e   0x0800016e   0x00000000   Code   RO         1002    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
-    0x0800016e   0x0800016e   0x00000004   Code   RO         1003    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
-    0x08000172   0x08000172   0x00000000   Code   RO         1005    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
-    0x08000172   0x08000172   0x00000008   Code   RO         1006    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
-    0x0800017a   0x0800017a   0x00000002   Code   RO         1027    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
-    0x0800017c   0x0800017c   0x00000000   Code   RO         1075    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
-    0x0800017c   0x0800017c   0x00000004   Code   RO         1076    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
-    0x08000180   0x08000180   0x00000006   Code   RO         1077    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
-    0x08000186   0x08000186   0x00000002   PAD
-    0x08000188   0x08000188   0x00000040   Code   RO          768  * .text               startup_stm32f10x_md.o
-    0x080001c8   0x080001c8   0x00000006   Code   RO          994    .text               c_w.l(heapauxi.o)
-    0x080001ce   0x080001ce   0x0000004a   Code   RO         1014    .text               c_w.l(sys_stackheap_outer.o)
-    0x08000218   0x08000218   0x00000012   Code   RO         1016    .text               c_w.l(exit.o)
-    0x0800022a   0x0800022a   0x00000002   PAD
-    0x0800022c   0x0800022c   0x00000008   Code   RO         1024    .text               c_w.l(libspace.o)
-    0x08000234   0x08000234   0x0000000c   Code   RO         1085    .text               c_w.l(sys_exit.o)
-    0x08000240   0x08000240   0x00000002   Code   RO         1096    .text               c_w.l(use_no_semi.o)
-    0x08000242   0x08000242   0x00000000   Code   RO         1098    .text               c_w.l(indicate_semi.o)
-    0x08000242   0x08000242   0x00000004   Code   RO            4    i.BusFault_Handler  stm32f10x_it.o
-    0x08000246   0x08000246   0x00000002   Code   RO            5    i.DebugMon_Handler  stm32f10x_it.o
-    0x08000248   0x08000248   0x00000116   Code   RO          827    i.GPIO_Init         stm32f10x_gpio.o
-    0x0800035e   0x0800035e   0x00000004   Code   RO            6    i.HardFault_Handler  stm32f10x_it.o
-    0x08000362   0x08000362   0x00000002   PAD
-    0x08000364   0x08000364   0x00000050   Code   RO          127    i.I2C1_Init         main.o
-    0x080003b4   0x080003b4   0x000000b4   Code   RO          128    i.I2C1_Read         main.o
-    0x08000468   0x08000468   0x00000018   Code   RO          341    i.I2C_AcknowledgeConfig  stm32f10x_i2c.o
-    0x08000480   0x08000480   0x0000002a   Code   RO          343    i.I2C_CheckEvent    stm32f10x_i2c.o
-    0x080004aa   0x080004aa   0x00000018   Code   RO          346    i.I2C_Cmd           stm32f10x_i2c.o
-    0x080004c2   0x080004c2   0x00000002   PAD
-    0x080004c4   0x080004c4   0x00000038   Code   RO          349    i.I2C_DeInit        stm32f10x_i2c.o
-    0x080004fc   0x080004fc   0x0000002c   Code   RO          129    i.I2C_GPIO_Config   main.o
-    0x08000528   0x08000528   0x00000018   Code   RO          353    i.I2C_GenerateSTART  stm32f10x_i2c.o
-    0x08000540   0x08000540   0x00000018   Code   RO          354    i.I2C_GenerateSTOP  stm32f10x_i2c.o
-    0x08000558   0x08000558   0x000000ec   Code   RO          360    i.I2C_Init          stm32f10x_i2c.o
-    0x08000644   0x08000644   0x00000008   Code   RO          365    i.I2C_ReceiveData   stm32f10x_i2c.o
-    0x0800064c   0x0800064c   0x00000012   Code   RO          367    i.I2C_Send7bitAddress  stm32f10x_i2c.o
-    0x0800065e   0x0800065e   0x00000004   Code   RO          368    i.I2C_SendData      stm32f10x_i2c.o
-    0x08000662   0x08000662   0x00000004   Code   RO            7    i.MemManage_Handler  stm32f10x_it.o
-    0x08000666   0x08000666   0x00000002   Code   RO            8    i.NMI_Handler       stm32f10x_it.o
-    0x08000668   0x08000668   0x00000002   Code   RO            9    i.PendSV_Handler    stm32f10x_it.o
-    0x0800066a   0x0800066a   0x00000002   PAD
-    0x0800066c   0x0800066c   0x00000020   Code   RO          558    i.RCC_APB1PeriphClockCmd  stm32f10x_rcc.o
-    0x0800068c   0x0800068c   0x00000020   Code   RO          559    i.RCC_APB1PeriphResetCmd  stm32f10x_rcc.o
-    0x080006ac   0x080006ac   0x00000020   Code   RO          560    i.RCC_APB2PeriphClockCmd  stm32f10x_rcc.o
-    0x080006cc   0x080006cc   0x00000008   Code   RO          130    i.RCC_Configuration  main.o
-    0x080006d4   0x080006d4   0x000000d4   Code   RO          568    i.RCC_GetClocksFreq  stm32f10x_rcc.o
-    0x080007a8   0x080007a8   0x00000002   Code   RO           10    i.SVC_Handler       stm32f10x_it.o
-    0x080007aa   0x080007aa   0x00000008   Code   RO          775    i.SetSysClock       system_stm32f10x.o
-    0x080007b2   0x080007b2   0x00000002   PAD
-    0x080007b4   0x080007b4   0x000000e0   Code   RO          776    i.SetSysClockTo72   system_stm32f10x.o
-    0x08000894   0x08000894   0x00000002   Code   RO           11    i.SysTick_Handler   stm32f10x_it.o
-    0x08000896   0x08000896   0x00000002   PAD
-    0x08000898   0x08000898   0x00000060   Code   RO          778    i.SystemInit        system_stm32f10x.o
-    0x080008f8   0x080008f8   0x00000004   Code   RO           12    i.UsageFault_Handler  stm32f10x_it.o
-    0x080008fc   0x080008fc   0x00000016   Code   RO          131    i.main              main.o
-    0x08000912   0x08000912   0x00000002   PAD
-    0x08000914   0x08000914   0x00000020   Data   RO         1151    Region$$Table       anon$$obj.o
+    0x08000000   0x08000000   0x000000ec   Data   RO         1037    RESET               startup_stm32f10x_md.o
+    0x080000ec   0x080000ec   0x00000008   Code   RO         1092  * !!!main             c_w.l(__main.o)
+    0x080000f4   0x080000f4   0x00000034   Code   RO         1249    !!!scatter          c_w.l(__scatter.o)
+    0x08000128   0x08000128   0x0000001c   Code   RO         1251    !!handler_zi        c_w.l(__scatter_zi.o)
+    0x08000144   0x08000144   0x00000002   Code   RO         1119    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1126    .ARM.Collect$$libinit$$00000002  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1128    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1131    .ARM.Collect$$libinit$$0000000A  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1133    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1135    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1138    .ARM.Collect$$libinit$$00000011  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1140    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1142    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1144    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1146    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1148    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1150    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1152    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1154    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1156    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1158    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1162    .ARM.Collect$$libinit$$0000002C  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1164    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1166    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000000   Code   RO         1168    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
+    0x08000146   0x08000146   0x00000002   Code   RO         1169    .ARM.Collect$$libinit$$00000033  c_w.l(libinit2.o)
+    0x08000148   0x08000148   0x00000002   Code   RO         1189    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1202    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1204    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1207    .ARM.Collect$$libshutdown$$00000007  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1210    .ARM.Collect$$libshutdown$$0000000A  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1212    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000000   Code   RO         1215    .ARM.Collect$$libshutdown$$0000000F  c_w.l(libshutdown2.o)
+    0x0800014a   0x0800014a   0x00000002   Code   RO         1216    .ARM.Collect$$libshutdown$$00000010  c_w.l(libshutdown2.o)
+    0x0800014c   0x0800014c   0x00000000   Code   RO         1094    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
+    0x0800014c   0x0800014c   0x00000000   Code   RO         1096    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
+    0x0800014c   0x0800014c   0x00000006   Code   RO         1108    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
+    0x08000152   0x08000152   0x00000000   Code   RO         1098    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
+    0x08000152   0x08000152   0x00000004   Code   RO         1099    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
+    0x08000156   0x08000156   0x00000000   Code   RO         1101    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
+    0x08000156   0x08000156   0x00000008   Code   RO         1102    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
+    0x0800015e   0x0800015e   0x00000002   Code   RO         1123    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
+    0x08000160   0x08000160   0x00000000   Code   RO         1171    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
+    0x08000160   0x08000160   0x00000004   Code   RO         1172    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
+    0x08000164   0x08000164   0x00000006   Code   RO         1173    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
+    0x0800016a   0x0800016a   0x00000002   PAD
+    0x0800016c   0x0800016c   0x00000040   Code   RO         1038  * .text               startup_stm32f10x_md.o
+    0x080001ac   0x080001ac   0x00000006   Code   RO         1090    .text               c_w.l(heapauxi.o)
+    0x080001b2   0x080001b2   0x0000004a   Code   RO         1110    .text               c_w.l(sys_stackheap_outer.o)
+    0x080001fc   0x080001fc   0x00000012   Code   RO         1112    .text               c_w.l(exit.o)
+    0x0800020e   0x0800020e   0x00000002   PAD
+    0x08000210   0x08000210   0x00000008   Code   RO         1120    .text               c_w.l(libspace.o)
+    0x08000218   0x08000218   0x0000000c   Code   RO         1181    .text               c_w.l(sys_exit.o)
+    0x08000224   0x08000224   0x00000002   Code   RO         1192    .text               c_w.l(use_no_semi.o)
+    0x08000226   0x08000226   0x00000000   Code   RO         1194    .text               c_w.l(indicate_semi.o)
+    0x08000226   0x08000226   0x00000004   Code   RO            4    i.BusFault_Handler  stm32f10x_it.o
+    0x0800022a   0x0800022a   0x00000002   Code   RO            5    i.DebugMon_Handler  stm32f10x_it.o
+    0x0800022c   0x0800022c   0x00000116   Code   RO          442    i.GPIO_Init         stm32f10x_gpio.o
+    0x08000342   0x08000342   0x00000012   Code   RO          446    i.GPIO_ReadInputDataBit  stm32f10x_gpio.o
+    0x08000354   0x08000354   0x00000004   Code   RO          449    i.GPIO_ResetBits    stm32f10x_gpio.o
+    0x08000358   0x08000358   0x00000004   Code   RO          450    i.GPIO_SetBits      stm32f10x_gpio.o
+    0x0800035c   0x0800035c   0x00000004   Code   RO            6    i.HardFault_Handler  stm32f10x_it.o
+    0x08000360   0x08000360   0x00000004   Code   RO            7    i.MemManage_Handler  stm32f10x_it.o
+    0x08000364   0x08000364   0x00000002   Code   RO            8    i.NMI_Handler       stm32f10x_it.o
+    0x08000366   0x08000366   0x00000002   Code   RO            9    i.PendSV_Handler    stm32f10x_it.o
+    0x08000368   0x08000368   0x00000020   Code   RO          782    i.RCC_APB2PeriphClockCmd  stm32f10x_rcc.o
+    0x08000388   0x08000388   0x00000008   Code   RO          130    i.RCC_Configuration  main.o
+    0x08000390   0x08000390   0x00000050   Code   RO          262    i.SCCB_Init         sccb.o
+    0x080003e0   0x080003e0   0x00000040   Code   RO          263    i.SCCB_No_Ack       sccb.o
+    0x08000420   0x08000420   0x00000050   Code   RO          264    i.SCCB_RD_Byte      sccb.o
+    0x08000470   0x08000470   0x0000004e   Code   RO          265    i.SCCB_RD_Reg       sccb.o
+    0x080004be   0x080004be   0x00000002   PAD
+    0x080004c0   0x080004c0   0x00000024   Code   RO          266    i.SCCB_SDA_IN       sccb.o
+    0x080004e4   0x080004e4   0x00000024   Code   RO          267    i.SCCB_SDA_OUT      sccb.o
+    0x08000508   0x08000508   0x00000034   Code   RO          268    i.SCCB_Start        sccb.o
+    0x0800053c   0x0800053c   0x00000034   Code   RO          269    i.SCCB_Stop         sccb.o
+    0x08000570   0x08000570   0x00000084   Code   RO          270    i.SCCB_WR_Byte      sccb.o
+    0x080005f4   0x080005f4   0x00000002   Code   RO           10    i.SVC_Handler       stm32f10x_it.o
+    0x080005f6   0x080005f6   0x00000008   Code   RO         1045    i.SetSysClock       system_stm32f10x.o
+    0x080005fe   0x080005fe   0x00000002   PAD
+    0x08000600   0x08000600   0x000000e0   Code   RO         1046    i.SetSysClockTo72   system_stm32f10x.o
+    0x080006e0   0x080006e0   0x00000002   Code   RO           11    i.SysTick_Handler   stm32f10x_it.o
+    0x080006e2   0x080006e2   0x00000002   PAD
+    0x080006e4   0x080006e4   0x00000060   Code   RO         1048    i.SystemInit        system_stm32f10x.o
+    0x08000744   0x08000744   0x00000004   Code   RO           12    i.UsageFault_Handler  stm32f10x_it.o
+    0x08000748   0x08000748   0x0000001a   Code   RO          272    i.delay_us          sccb.o
+    0x08000762   0x08000762   0x00000028   Code   RO          131    i.main              main.o
+    0x0800078a   0x0800078a   0x00000002   PAD
+    0x0800078c   0x0800078c   0x00000010   Data   RO         1247    Region$$Table       anon$$obj.o
 
 
-    Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000934, Size: 0x00000014, Max: 0xffffffff, ABSOLUTE)
+    Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800079c, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
+
+    **** No section assigned to this execution region ****
+
+
+    Execution Region ER_ZI (Exec base: 0x20000000, Load base: 0x0800079c, Size: 0x00000660, Max: 0xffffffff, ABSOLUTE)
 
     Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
 
-    0x20000000   0x08000934   0x00000014   Data   RW          588    .data               stm32f10x_rcc.o
-
-
-    Execution Region ER_ZI (Exec base: 0x20000014, Load base: 0x08000948, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE)
-
-    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
-
-    0x20000014        -       0x00000060   Zero   RW         1025    .bss                c_w.l(libspace.o)
-    0x20000074   0x08000948   0x00000004   PAD
-    0x20000078        -       0x00000200   Zero   RW          766    HEAP                startup_stm32f10x_md.o
-    0x20000278        -       0x00000400   Zero   RW          765    STACK               startup_stm32f10x_md.o
+    0x20000000        -       0x00000060   Zero   RW         1121    .bss                c_w.l(libspace.o)
+    0x20000060        -       0x00000200   Zero   RW         1036    HEAP                startup_stm32f10x_md.o
+    0x20000260        -       0x00000400   Zero   RW         1035    STACK               startup_stm32f10x_md.o
 
 
 ==============================================================================
@@ -810,18 +844,18 @@ Image component sizes
 
       Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
 
-       334         24          0          0          0       2313   main.o
+        48          0          0          0          0       1631   main.o
+       636         40          0          0          0       4779   sccb.o
         64         26        236          0       1536        812   startup_stm32f10x_md.o
-       278          0          0          0          0       2184   stm32f10x_gpio.o
-       460         20          0          0          0       8037   stm32f10x_i2c.o
-        26          0          0          0          0     235306   stm32f10x_it.o
-       308         38          0         20          0       5303   stm32f10x_rcc.o
+       304          0          0          0          0       3968   stm32f10x_gpio.o
+        26          0          0          0          0     218438   stm32f10x_it.o
+        32          6          0          0          0        601   stm32f10x_rcc.o
        328         28          0          0          0       2077   system_stm32f10x.o
 
     ----------------------------------------------------------------------
-      1810        136        268         20       1536     256032   Object Totals
-         0          0         32          0          0          0   (incl. Generated)
-        12          0          0          0          0          0   (incl. Padding)
+      1446        100        252          0       1536     232306   Object Totals
+         0          0         16          0          0          0   (incl. Generated)
+         8          0          0          0          0          0   (incl. Padding)
 
     ----------------------------------------------------------------------
 
@@ -832,7 +866,6 @@ Image component sizes
         12          0          0          0          0          0   __rtentry2.o
          6          0          0          0          0          0   __rtentry4.o
         52          8          0          0          0          0   __scatter.o
-        26          0          0          0          0          0   __scatter_copy.o
         28          0          0          0          0          0   __scatter_zi.o
         18          0          0          0          0         80   exit.o
          6          0          0          0          0        152   heapauxi.o
@@ -849,17 +882,17 @@ Image component sizes
          2          0          0          0          0         68   use_no_semi.o
 
     ----------------------------------------------------------------------
-       278         16          0          0        100        584   Library Totals
-         6          0          0          0          4          0   (incl. Padding)
+       250         16          0          0         96        584   Library Totals
+         4          0          0          0          0          0   (incl. Padding)
 
     ----------------------------------------------------------------------
 
       Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
 
-       272         16          0          0         96        584   c_w.l
+       246         16          0          0         96        584   c_w.l
 
     ----------------------------------------------------------------------
-       278         16          0          0        100        584   Library Totals
+       250         16          0          0         96        584   Library Totals
 
     ----------------------------------------------------------------------
 
@@ -868,15 +901,15 @@ Image component sizes
 
       Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
 
-      2088        152        268         20       1636     254948   Grand Totals
-      2088        152        268         20       1636     254948   ELF Image Totals
-      2088        152        268         20          0          0   ROM Totals
+      1696        116        252          0       1632     231310   Grand Totals
+      1696        116        252          0       1632     231310   ELF Image Totals
+      1696        116        252          0          0          0   ROM Totals
 
 ==============================================================================
 
-    Total RO  Size (Code + RO Data)                 2356 (   2.30kB)
-    Total RW  Size (RW Data + ZI Data)              1656 (   1.62kB)
-    Total ROM Size (Code + RO Data + RW Data)       2376 (   2.32kB)
+    Total RO  Size (Code + RO Data)                 1948 (   1.90kB)
+    Total RW  Size (RW Data + ZI Data)              1632 (   1.59kB)
+    Total ROM Size (Code + RO Data + RW Data)       1948 (   1.90kB)
 
 ==============================================================================
 
diff --git a/cmos/gc0307/stm32/Objects/gc0307.axf b/cmos/gc0307/stm32/Objects/gc0307.axf
index 8442423..4a3c853 100644
Binary files a/cmos/gc0307/stm32/Objects/gc0307.axf and b/cmos/gc0307/stm32/Objects/gc0307.axf differ
diff --git a/cmos/gc0307/stm32/Objects/gc0307.lnp b/cmos/gc0307/stm32/Objects/gc0307.lnp
index 17a875b..09242c9 100644
--- a/cmos/gc0307/stm32/Objects/gc0307.lnp
+++ b/cmos/gc0307/stm32/Objects/gc0307.lnp
@@ -2,14 +2,15 @@
 ".\objects\stm32f10x_it.o"
 ".\objects\main.o"
 ".\objects\i2c_ee.o"
+".\objects\sccb.o"
 ".\objects\misc.o"
 ".\objects\stm32f10x_dbgmcu.o"
+".\objects\stm32f10x_gpio.o"
 ".\objects\stm32f10x_i2c.o"
 ".\objects\stm32f10x_rcc.o"
+".\objects\gpio_stm32f10x.o"
 ".\objects\startup_stm32f10x_md.o"
 ".\objects\system_stm32f10x.o"
-".\objects\stm32f10x_gpio.o"
-".\objects\gpio_stm32f10x.o"
 --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
 --info sizes --info totals --info unused --info veneers
 --list ".\Listings\gc0307.map" -o .\Objects\gc0307.axf
\ No newline at end of file
diff --git a/cmos/gc0307/stm32/gc0307.uvoptx b/cmos/gc0307/stm32/gc0307.uvoptx
index c867587..288e046 100644
--- a/cmos/gc0307/stm32/gc0307.uvoptx
+++ b/cmos/gc0307/stm32/gc0307.uvoptx
@@ -152,25 +152,25 @@
         <Bp>
           <Number>0</Number>
           <Type>0</Type>
-          <LineNumber>120</LineNumber>
+          <LineNumber>168</LineNumber>
           <EnabledFlag>1</EnabledFlag>
-          <Address>134220050</Address>
+          <Address>134218938</Address>
           <ByteObject>0</ByteObject>
           <HtxType>0</HtxType>
           <ManyObjects>0</ManyObjects>
           <SizeOfObject>0</SizeOfObject>
           <BreakByAccess>0</BreakByAccess>
           <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\src\main.c</Filename>
+          <Filename>.\sccb.c</Filename>
           <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\120</Expression>
+          <Expression>\\gc0307\sccb.c\168</Expression>
         </Bp>
         <Bp>
           <Number>1</Number>
           <Type>0</Type>
-          <LineNumber>117</LineNumber>
+          <LineNumber>122</LineNumber>
           <EnabledFlag>1</EnabledFlag>
-          <Address>134220044</Address>
+          <Address>134219654</Address>
           <ByteObject>0</ByteObject>
           <HtxType>0</HtxType>
           <ManyObjects>0</ManyObjects>
@@ -179,14 +179,14 @@
           <BreakIfRCount>1</BreakIfRCount>
           <Filename>.\src\main.c</Filename>
           <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\117</Expression>
+          <Expression>\\gc0307\src/main.c\122</Expression>
         </Bp>
         <Bp>
           <Number>2</Number>
           <Type>0</Type>
-          <LineNumber>112</LineNumber>
+          <LineNumber>119</LineNumber>
           <EnabledFlag>1</EnabledFlag>
-          <Address>134220032</Address>
+          <Address>134219636</Address>
           <ByteObject>0</ByteObject>
           <HtxType>0</HtxType>
           <ManyObjects>0</ManyObjects>
@@ -195,59 +195,11 @@
           <BreakIfRCount>1</BreakIfRCount>
           <Filename>.\src\main.c</Filename>
           <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\112</Expression>
+          <Expression>\\gc0307\src/main.c\119</Expression>
         </Bp>
         <Bp>
           <Number>3</Number>
           <Type>0</Type>
-          <LineNumber>94</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>134218758</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\src\main.c</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\94</Expression>
-        </Bp>
-        <Bp>
-          <Number>4</Number>
-          <Type>0</Type>
-          <LineNumber>91</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>134218734</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\src\main.c</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\91</Expression>
-        </Bp>
-        <Bp>
-          <Number>5</Number>
-          <Type>0</Type>
-          <LineNumber>89</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>134218710</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\src\main.c</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression>\\gc0307\src/main.c\89</Expression>
-        </Bp>
-        <Bp>
-          <Number>6</Number>
-          <Type>0</Type>
           <LineNumber>212</LineNumber>
           <EnabledFlag>1</EnabledFlag>
           <Address>0</Address>
@@ -262,7 +214,7 @@
           <Expression></Expression>
         </Bp>
         <Bp>
-          <Number>7</Number>
+          <Number>4</Number>
           <Type>0</Type>
           <LineNumber>218</LineNumber>
           <EnabledFlag>1</EnabledFlag>
@@ -277,6 +229,38 @@
           <ExecCommand></ExecCommand>
           <Expression></Expression>
         </Bp>
+        <Bp>
+          <Number>5</Number>
+          <Type>0</Type>
+          <LineNumber>91</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>0</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>0</BreakIfRCount>
+          <Filename>.\src\main.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression></Expression>
+        </Bp>
+        <Bp>
+          <Number>6</Number>
+          <Type>0</Type>
+          <LineNumber>95</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>0</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>0</BreakIfRCount>
+          <Filename>.\src\main.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression></Expression>
+        </Bp>
       </Breakpoint>
       <Tracepoint>
         <THDelay>0</THDelay>
@@ -284,7 +268,7 @@
       <DebugFlag>
         <trace>0</trace>
         <periodic>1</periodic>
-        <aLwin>1</aLwin>
+        <aLwin>0</aLwin>
         <aCover>0</aCover>
         <aSer1>0</aSer1>
         <aSer2>0</aSer2>
@@ -321,6 +305,10 @@
       <pSingCmdsp></pSingCmdsp>
       <pMultCmdsp></pMultCmdsp>
       <SystemViewers>
+        <Entry>
+          <Name>System Viewer\GPIOB</Name>
+          <WinId>35904</WinId>
+        </Entry>
         <Entry>
           <Name>System Viewer\I2C1</Name>
           <WinId>35905</WinId>
@@ -378,6 +366,18 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\sccb.c</PathWithFileName>
+      <FilenameWithoutPath>sccb.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>
diff --git a/cmos/gc0307/stm32/gc0307.uvprojx b/cmos/gc0307/stm32/gc0307.uvprojx
index 0f4a4eb..197c934 100644
--- a/cmos/gc0307/stm32/gc0307.uvprojx
+++ b/cmos/gc0307/stm32/gc0307.uvprojx
@@ -397,6 +397,11 @@
               <FileType>1</FileType>
               <FilePath>.\src\i2c_ee.c</FilePath>
             </File>
+            <File>
+              <FileName>sccb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\sccb.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
diff --git a/cmos/gc0307/stm32/sccb.c b/cmos/gc0307/stm32/sccb.c
new file mode 100644
index 0000000..964e967
--- /dev/null
+++ b/cmos/gc0307/stm32/sccb.c
@@ -0,0 +1,169 @@
+#include "sccb_gpio.h"
+
+
+#define SCCB_ID   			0x42 
+
+void SCCB_SDA_IN()  
+{
+	GPIO_InitTypeDef  GPIO_InitStructure; 
+
+	GPIO_InitStructure.GPIO_Pin =  I2C_EE_SDA ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure);
+}
+void  SCCB_SDA_OUT() {
+	GPIO_InitTypeDef  GPIO_InitStructure; 
+
+	GPIO_InitStructure.GPIO_Pin =  I2C_EE_SDA ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure);
+}
+
+//???SCCB??
+//CHECK OK
+void SCCB_Init(void){											   
+	GPIO_InitTypeDef  GPIO_InitStructure; 
+  /* Configure I2C_EE pins: SCL and SDA */
+  GPIO_InitStructure.GPIO_Pin =  I2C_EE_SCL ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure);
+	GPIO_InitStructure.GPIO_Pin =  I2C_EE_SDA ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure);
+	SCCB_SDA_OUT();	  
+	GPIO_SetBits(GPIOB,I2C_EE_SDA);
+	GPIO_SetBits(GPIOB,I2C_EE_SCL);
+}			 
+void delay_us(unsigned int x){
+	for(unsigned int i = 0;i < x;i++){
+		for(unsigned int z = 0;z < 2;z++){
+			z = z;
+		}
+	}
+		
+}
+	
+
+//SCCB????
+//??????,???????,?????
+//??????,SDA?SCL?????
+void SCCB_Start(void){
+		GPIO_SetBits(GPIOB,I2C_EE_SDA);
+		GPIO_SetBits(GPIOB,I2C_EE_SCL);
+    delay_us(50);  
+		GPIO_ResetBits(GPIOB,I2C_EE_SDA);
+    delay_us(50);	 
+		GPIO_ResetBits(GPIOB,I2C_EE_SCL);
+}
+
+//SCCB????
+//??????,???????,?????
+//??????,SDA?SCL?????
+void SCCB_Stop(void){
+		GPIO_ResetBits(GPIOB,I2C_EE_SDA);
+    delay_us(50);	 
+		GPIO_SetBits(GPIOB,I2C_EE_SCL);
+    delay_us(50); 
+		GPIO_SetBits(GPIOB,I2C_EE_SDA);
+    delay_us(50);
+}  
+//??NA??
+void SCCB_No_Ack(void)
+{
+	delay_us(50);
+	GPIO_SetBits(GPIOB,I2C_EE_SDA);
+	GPIO_SetBits(GPIOB,I2C_EE_SCL);
+	delay_us(50);
+	GPIO_ResetBits(GPIOB,I2C_EE_SCL);
+	delay_us(50);
+	GPIO_SetBits(GPIOB,I2C_EE_SDA);
+	delay_us(50);
+}
+//SCCB,??????
+//??0????
+u8 SCCB_WR_Byte(u8 dat)
+{
+	u8 j,res;	 
+	for(j=0;j<8;j++) //??8?????
+	{
+		if(dat&0x80)
+			GPIO_SetBits(GPIOB,I2C_EE_SDA);
+		else 
+			GPIO_ResetBits(GPIOB,I2C_EE_SDA);
+		dat<<=1;
+		delay_us(50);
+		GPIO_SetBits(GPIOB,I2C_EE_SCL);
+		delay_us(50);
+		GPIO_ResetBits(GPIOB,I2C_EE_SCL);
+	}
+	SCCB_SDA_IN();
+	delay_us(50);
+	GPIO_SetBits(GPIOB,I2C_EE_SCL);
+	delay_us(50);
+	
+	if(GPIO_ReadInputDataBit(GPIOB,I2C_EE_SDA))
+		res=1;  //SDA=1????
+	else 
+		res=0;         //SDA=0????
+	GPIO_ResetBits(GPIOB,I2C_EE_SCL);
+	SCCB_SDA_OUT();
+	return res;  
+}	 
+//SCCB ??????
+//?SCL????,????
+//???:?????
+u8 SCCB_RD_Byte(void)
+{
+	u8 temp=0,j;    
+	SCCB_SDA_IN();
+	for(j=8;j>0;j--) 	//??8?????
+	{		     	  
+		delay_us(50);
+		GPIO_SetBits(GPIOB,I2C_EE_SCL);
+		temp=temp<<1;
+		if(GPIO_ReadInputDataBit(GPIOB,I2C_EE_SDA))
+			temp++;   
+		delay_us(50);
+		GPIO_ResetBits(GPIOB,I2C_EE_SCL);
+	}	
+	SCCB_SDA_OUT();
+	return temp;
+} 							    
+//????
+//???:0??
+u8 SCCB_WR_Reg(u8 reg,u8 data)
+{
+	u8 res=0;
+	SCCB_Start(); //????
+	if(SCCB_WR_Byte(SCCB_ID))res=1;	//???ID
+	delay_us(100);
+  	if(SCCB_WR_Byte(reg))res=1;		//??????  
+	delay_us(100);
+  	if(SCCB_WR_Byte(data))res=1; 	//??? 
+  	SCCB_Stop();	 //????  
+  	return	res;
+}		  					    
+//????
+u8 SCCB_RD_Reg(u8 reg)
+{
+	u8 val=0;
+	SCCB_Start(); //????
+	SCCB_WR_Byte(SCCB_ID);			//???ID 
+	delay_us(100);	 
+  SCCB_WR_Byte(reg);			//??????  	  
+	delay_us(100);	  
+	SCCB_Stop();   
+	delay_us(100);	   
+	//???????????
+	SCCB_Start();
+	SCCB_WR_Byte(SCCB_ID|0X01);	//?????  
+	delay_us(100);
+	val=SCCB_RD_Byte();		 	//???
+  SCCB_No_Ack(); //??NA
+  SCCB_Stop(); //????  
+  return val;
+}
diff --git a/cmos/gc0307/stm32/sccb_gpio.h b/cmos/gc0307/stm32/sccb_gpio.h
new file mode 100644
index 0000000..963e781
--- /dev/null
+++ b/cmos/gc0307/stm32/sccb_gpio.h
@@ -0,0 +1,14 @@
+
+#ifndef __SCCB
+#define __SCCB
+#include "src/i2c_ee.h"
+
+
+void SCCB_SDA_IN();
+void  SCCB_SDA_OUT();
+void SCCB_Init(void);
+void SCCB_No_Ack(void);
+u8 SCCB_RD_Reg(u8 reg);
+
+#endif
+
diff --git a/cmos/gc0307/stm32/src/main.c b/cmos/gc0307/stm32/src/main.c
index fe3523e..a90a74f 100644
--- a/cmos/gc0307/stm32/src/main.c
+++ b/cmos/gc0307/stm32/src/main.c
@@ -19,7 +19,7 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "i2c_ee.h"
+#include "../sccb_gpio.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
@@ -58,12 +58,12 @@ TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength
  
 void I2C_GPIO_Config()
 {
-GPIO_InitTypeDef GPIO_InitStructure;
-RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
-GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-GPIO_Init(GPIOB, &GPIO_InitStructure);
+	GPIO_InitTypeDef GPIO_InitStructure;
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
 }
  
 void I2C1_Init()
@@ -86,14 +86,14 @@ u8 I2C1_Read(u8 nAddr)
 	I2C_AcknowledgeConfig(I2C1,ENABLE); //????
 	I2C_GenerateSTART(I2C1,ENABLE); //???????
 	while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_MODE_SELECT)){;} //??EV5
-	I2C_Send7bitAddress(I2C1,0x21,I2C_Direction_Receiver); //????????
+	I2C_Send7bitAddress(I2C1,0x22,I2C_Direction_Transmitter); //????????
 	while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)){;}//??EV6
 	I2C_SendData(I2C1,nAddr);//?????
 	while(!I2C_CheckEvent(I2C1,I2C_Direction_Receiver)){;} //??EV8
 	 
 	I2C_GenerateSTART(I2C1,ENABLE); //???????
 	while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_MODE_SELECT)){;} //??EV5
-	I2C_Send7bitAddress(I2C1,0x21,I2C_Direction_Transmitter); //???????
+	I2C_Send7bitAddress(I2C1,0x22,I2C_Direction_Transmitter); //???????
 	while(!I2C_CheckEvent(I2C1,I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)){;} //??EV6
 	I2C_AcknowledgeConfig(I2C1,DISABLE); //??????
 	I2C_GenerateSTOP(I2C1,ENABLE); //???????
@@ -108,14 +108,16 @@ u8 I2C1_Read(u8 nAddr)
   */
 int main(void)
 {
+	volatile uint8_t buf ;
   /* System clocks configuration ---------------------------------------------*/
   RCC_Configuration();
-	I2C_GPIO_Config();
-  /* Initialize the I2C EEPROM driver ----------------------------------------*/
-  I2C1_Init();
-	
-	uint8_t buf = I2C1_Read(0x00);
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 
+	SCCB_Init();
+  /* Initialize the I2C EEPROM driver ----------------------------------------*/
+	
+	buf = SCCB_RD_Reg(0x00);
+	buf++;
 
   while (1)
   {
diff --git a/steper/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf b/steper/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf
new file mode 100644
index 0000000..90dabd8
--- /dev/null
+++ b/steper/stm32/DebugConfig/Target_1_STM32F103RB_1.0.0.dbgconf
@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// <h> Debug MCU Configuration
+//   <o0.0>    DBG_SLEEP
+// <i> Debug Sleep Mode
+// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+//   <o0.1>    DBG_STOP
+// <i> Debug Stop Mode
+// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.2>    DBG_STANDBY
+// <i> Debug Standby Mode
+// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.8>    DBG_IWDG_STOP
+// <i> Debug independent watchdog stopped when core is halted
+// <i> 0: The watchdog counter clock continues even if the core is halted
+// <i> 1: The watchdog counter clock is stopped when the core is halted
+//   <o0.9>    DBG_WWDG_STOP
+// <i> Debug window watchdog stopped when core is halted
+// <i> 0: The window watchdog counter clock continues even if the core is halted
+// <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>   DBG_TIM1_STOP
+// <i> Timer 1 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.11>   DBG_TIM2_STOP
+// <i> Timer 2 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.12>   DBG_TIM3_STOP
+// <i> Timer 3 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.13>   DBG_TIM4_STOP
+// <i> Timer 4 counter stopped when core is halted
+// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
+// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
+//   <o0.14>   DBG_CAN1_STOP
+// <i> Debug CAN1 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN1 receive registers are frozen
+//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
+// <i> I2C1 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
+// <i> I2C2 SMBUS timeout mode stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: The SMBUS timeout is frozen
+//   <o0.17>   DBG_TIM8_STOP
+// <i> Timer 8 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.18>   DBG_TIM5_STOP
+// <i> Timer 5 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.19>   DBG_TIM6_STOP
+// <i> Timer 6 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.20>   DBG_TIM7_STOP
+// <i> Timer 7 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.21>   DBG_CAN2_STOP
+// <i> Debug CAN2 stopped when Core is halted
+// <i> 0: Same behavior as in normal mode
+// <i> 1: CAN2 receive registers are frozen
+//   <o0.25>   DBG_TIM12_STOP
+// <i> Timer 12 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.26>   DBG_TIM13_STOP
+// <i> Timer 13 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.27>   DBG_TIM14_STOP
+// <i> Timer 14 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.28>   DBG_TIM9_STOP
+// <i> Timer 9 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.29>   DBG_TIM10_STOP
+// <i> Timer 10 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//   <o0.30>   DBG_TIM11_STOP
+// <i> Timer 11 counter stopped when core is halted
+// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// </h>
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/steper/stm32/EventRecorderStub.scvd b/steper/stm32/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/steper/stm32/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
diff --git a/steper/stm32/JLinkLog.txt b/steper/stm32/JLinkLog.txt
new file mode 100644
index 0000000..c988f6a
--- /dev/null
+++ b/steper/stm32/JLinkLog.txt
@@ -0,0 +1,552 @@
+T06D0 790:227 SEGGER J-Link V4.90 Log File (0000ms, 13882ms total)
+T06D0 790:227 DLL Compiled: Jul 28 2014 10:35:20 (0000ms, 13882ms total)
+T06D0 790:227 Logging started @ 2019-12-30 20:39 (0000ms, 13882ms total)
+T06D0 790:227 JLINK_SetWarnOutHandler(...) (0000ms, 13882ms total)
+T06D0 790:227 JLINK_OpenEx(...)
+Firmware: J-Link ARM V8 compiled Jan 31 2018 18:34:52
+Hardware: V8.00
+S/N: 20080643
+Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull  returns O.K. (0264ms, 14146ms total)
+T06D0 790:491 JLINK_GetEmuCaps()  returns 0xB9FF7BBF (0000ms, 14146ms total)
+T06D0 790:491 JLINK_TIF_GetAvailable(...) (0000ms, 14146ms total)
+T06D0 790:492 JLINK_SetErrorOutHandler(...) (0000ms, 14146ms total)
+T06D0 790:492 JLINK_ExecCommand("ProjectFile = "D:\project\HardwareDriver\steper\stm32\JLinkSettings.ini"", ...)  returns 0x00 (0000ms, 14146ms total)
+T06D0 790:497 JLINK_ExecCommand("Device = STM32F103RB", ...)Device "STM32F103RB" selected (128 KB flash, 20 KB RAM).  returns 0x00 (0021ms, 14167ms total)
+T06D0 790:518 JLINK_ExecCommand("DisableConnectionTimeout", ...)  returns 0x01 (0000ms, 14167ms total)
+T06D0 790:518 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 14167ms total)
+T06D0 790:518 JLINK_GetDLLVersion()  returns 49000 (0000ms, 14167ms total)
+T06D0 790:518 JLINK_GetFirmwareString(...) (0000ms, 14167ms total)
+T06D0 790:544 JLINK_GetDLLVersion()  returns 49000 (0000ms, 14167ms total)
+T06D0 790:544 JLINK_GetCompileDateTime() (0000ms, 14167ms total)
+T06D0 790:550 JLINK_GetFirmwareString(...) (0000ms, 14167ms total)
+T06D0 790:553 JLINK_GetHardwareVersion()  returns 0x13880 (0000ms, 14167ms total)
+T06D0 790:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG)  returns 0x00 (0001ms, 14168ms total)
+T06D0 790:568 JLINK_SetSpeed(5000) (0000ms, 14168ms total)
+T06D0 790:568 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG>
+Found Cortex-M3 r1p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE00FF010)TPIU fitted. -- CPU_ReadMem(4 bytes @ 0xE00FF014) -- CPU_ReadMem(4 bytes @ 0xE00FF018)
+ ScanLen=9 NumDevices=2 aId[0]=0x3BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0043ms, 14211ms total)
+T06D0 790:611 JLINK_JTAG_GetDeviceID(DeviceIndex = 0)  returns 0x3BA00477 (0000ms, 14211ms total)
+T06D0 790:611 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0)  returns 0x00 (0000ms, 14211ms total)
+T06D0 790:611 JLINK_JTAG_GetDeviceID(DeviceIndex = 1)  returns 0x16410041 (0000ms, 14211ms total)
+T06D0 790:611 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1)  returns 0x00 (0000ms, 14211ms total)
+T06D0 790:611 JLINK_GetDLLVersion()  returns 49000 (0000ms, 14211ms total)
+T06D0 790:611 JLINK_CORE_GetFound()  returns 0x30000FF (0001ms, 14212ms total)
+T06D0 790:615 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003  returns 0x00 (0000ms, 14212ms total)
+T06D0 790:615 JLINK_GetDebugInfo(0x101)  returns 0xFFFFFFFF (0000ms, 14212ms total)
+T06D0 790:615 JLINK_ReadMemEx(0xE0041FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  returns 0x10 (0001ms, 14213ms total)
+T06D0 790:616 JLINK_GetDebugInfo(0x102)  returns 0xFFFFFFFF (0000ms, 14213ms total)
+T06D0 790:616 JLINK_GetDebugInfo(0x103)  returns 0xFFFFFFFF (0000ms, 14213ms total)
+T06D0 790:616 JLINK_ReadMemEx(0xE0040FF0, 0x0010 Bytes, ..., AccessWidth = 33554436) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00  returns 0x10 (0001ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x104)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x105)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x106)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x107)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x10C)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDebugInfo(0x01)  returns 0xFFFFFFFF (0000ms, 14214ms total)
+T06D0 790:617 JLINK_GetDeviceFamily()  returns 3 (0000ms, 14214ms total)
+T06D0 790:617 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41  returns 0x01 (0001ms, 14215ms total)
+T06D0 790:618 JLINK_GetDebugInfo(0x10F)  returns 0xFFFFFFFF (0000ms, 14215ms total)
+T06D0 790:618 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)  returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 14215ms total)
+T06D0 790:618 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG>
+ >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0026ms, 14241ms total)
+T06D0 790:644 JLINK_Halt()  returns 0x00 (0000ms, 14241ms total)
+T06D0 790:644 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00  returns 0x01 (0001ms, 14242ms total)
+T06D0 790:645 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0)  returns 0x00 (0000ms, 14242ms total)
+T06D0 790:645 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)  returns 0x00 (0001ms, 14243ms total)
+T06D0 790:660 JLINK_GetHWStatus(...)  returns 0x00 (0001ms, 14244ms total)
+T06D0 790:671 JLINK_GetNumBPUnits(Type = 0xFFFFFF00)  returns 0x06 (0000ms, 14244ms total)
+T06D0 790:671 JLINK_GetNumBPUnits(Type = 0xF0)  returns 0x2000 (0000ms, 14244ms total)
+T06D0 790:671 JLINK_GetNumWPUnits()  returns 0x04 (0000ms, 14244ms total)
+T06D0 790:683 JLINK_GetSpeed()  returns 0x12C0 (0001ms, 14245ms total)
+T06D0 790:689 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0001ms, 14246ms total)
+T06D0 790:690 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00  returns 0x01 (0000ms, 14246ms total)
+T06D0 790:690 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., AccessWidth = 33554436) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000)  returns 0x1C (0001ms, 14247ms total)
+T06D0 790:691 JLINK_Halt()  returns 0x00 (0000ms, 14247ms total)
+T06D0 790:691 JLINK_IsHalted()  returns TRUE (0000ms, 14247ms total)
+T06D0 790:694 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000)  returns 0x164 (0004ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R1, 0x00B71B00)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R2, 0x00000001)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(R15 (PC), 0x20000038)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14251ms total)
+T06D0 790:698 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000)  returns 0x00000001 (0001ms, 14252ms total)
+T06D0 790:699 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0005ms, 14257ms total)
+T06D0 790:704 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14261ms total)
+T06D0 790:708 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_ClrBPEx(BPHandle = 0x00000001)  returns 0x00 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14257ms total)
+T06D0 790:708 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0001ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(R15 (PC), 0x20000020)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000002 (0000ms, 14258ms total)
+T06D0 790:709 JLINK_Go() (0001ms, 14259ms total)
+T06D0 790:710 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14263ms total)
+T06D0 790:714 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_ClrBPEx(BPHandle = 0x00000002)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_ReadReg(R0)  returns 0x00000001 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(R15 (PC), 0x200000B6)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000003 (0000ms, 14259ms total)
+T06D0 790:714 JLINK_Go() (0002ms, 14261ms total)
+T06D0 790:716 JLINK_IsHalted()  returns FALSE (0000ms, 14261ms total)
+T06D0 790:788 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0003ms, 14264ms total)
+T06D0 790:791 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14261ms total)
+T06D0 790:791 JLINK_ClrBPEx(BPHandle = 0x00000003)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:791 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R0, 0x08000400)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(R15 (PC), 0x20000020)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:792 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14261ms total)
+T06D0 790:793 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14262ms total)
+T06D0 790:793 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14262ms total)
+T06D0 790:793 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14262ms total)
+T06D0 790:793 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000004 (0000ms, 14262ms total)
+T06D0 790:793 JLINK_Go() (0001ms, 14263ms total)
+T06D0 790:794 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14267ms total)
+T06D0 790:798 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_ClrBPEx(BPHandle = 0x00000004)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_ReadReg(R0)  returns 0x00000001 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R0, 0x08000400)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(R15 (PC), 0x200000B6)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000005 (0000ms, 14263ms total)
+T06D0 790:798 JLINK_Go() (0001ms, 14264ms total)
+T06D0 790:799 JLINK_IsHalted()  returns FALSE (0001ms, 14265ms total)
+T06D0 790:805 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:807 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:809 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:811 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:813 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:815 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:817 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:819 JLINK_IsHalted()  returns FALSE (0000ms, 14264ms total)
+T06D0 790:824 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0003ms, 14267ms total)
+T06D0 790:827 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14264ms total)
+T06D0 790:827 JLINK_ClrBPEx(BPHandle = 0x00000005)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:827 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R0, 0x08000800)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(R15 (PC), 0x20000020)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000006 (0000ms, 14264ms total)
+T06D0 790:829 JLINK_Go() (0001ms, 14265ms total)
+T06D0 790:830 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14269ms total)
+T06D0 790:834 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_ClrBPEx(BPHandle = 0x00000006)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_ReadReg(R0)  returns 0x00000001 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R0, 0x08000800)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(R15 (PC), 0x200000B6)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14265ms total)
+T06D0 790:834 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000007 (0000ms, 14265ms total)
+T06D0 790:835 JLINK_Go() (0001ms, 14266ms total)
+T06D0 790:836 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:840 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:842 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:849 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:851 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:853 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:855 JLINK_IsHalted()  returns FALSE (0000ms, 14266ms total)
+T06D0 790:860 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0003ms, 14269ms total)
+T06D0 790:863 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14266ms total)
+T06D0 790:863 JLINK_ClrBPEx(BPHandle = 0x00000007)  returns 0x00 (0000ms, 14266ms total)
+T06D0 790:863 JLINK_ReadReg(R0)  returns 0x00000000 (0001ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R0, 0x00000001)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R2, 0x000000FF)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(R15 (PC), 0x2000006A)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000008 (0000ms, 14267ms total)
+T06D0 790:864 JLINK_Go() (0002ms, 14269ms total)
+T06D0 790:866 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0003ms, 14272ms total)
+T06D0 790:869 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14269ms total)
+T06D0 790:869 JLINK_ClrBPEx(BPHandle = 0x00000008)  returns 0x00 (0000ms, 14269ms total)
+T06D0 790:869 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14269ms total)
+T06D0 790:928 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000)  returns 0x164 (0004ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R1, 0x00B71B00)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R2, 0x00000002)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(R15 (PC), 0x20000038)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14273ms total)
+T06D0 790:932 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000)  returns 0x00000009 (0001ms, 14274ms total)
+T06D0 790:933 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) (0002ms, 14276ms total)
+T06D0 790:935 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14280ms total)
+T06D0 790:939 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14276ms total)
+T06D0 790:939 JLINK_ClrBPEx(BPHandle = 0x00000009)  returns 0x00 (0000ms, 14276ms total)
+T06D0 790:939 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14276ms total)
+T06D0 790:939 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 88 06 00 20 89 01 00 08 91 01 00 08 93 01 00 08 ... -- CPU_WriteMem(668 bytes @ 0x20000164)  returns 0x29C (0006ms, 14282ms total)
+T06D0 790:945 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 10 0C BC F1 00 0F 03 D0 91 F8 02 C0 4C EA 05 05 ... -- CPU_WriteMem(356 bytes @ 0x20000400)  returns 0x164 (0003ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R2, 0x20000164)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(R15 (PC), 0x200000F4)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:948 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14285ms total)
+T06D0 790:949 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14286ms total)
+T06D0 790:949 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14286ms total)
+T06D0 790:949 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14286ms total)
+T06D0 790:949 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x0000000A (0000ms, 14286ms total)
+T06D0 790:949 JLINK_Go() (0001ms, 14287ms total)
+T06D0 790:950 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:958 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:960 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:962 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:964 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:966 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:968 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:970 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:972 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:977 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:979 JLINK_IsHalted()  returns FALSE (0000ms, 14287ms total)
+T06D0 790:981 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14291ms total)
+T06D0 790:985 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14287ms total)
+T06D0 790:985 JLINK_ClrBPEx(BPHandle = 0x0000000A)  returns 0x00 (0000ms, 14287ms total)
+T06D0 790:985 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14287ms total)
+T06D0 790:985 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F1 D1 29 48 00 68 00 F4 00 30 10 B1 01 20 00 90 ... -- CPU_WriteMem(668 bytes @ 0x20000164)  returns 0x29C (0006ms, 14293ms total)
+T06D0 790:991 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 4F F6 8F 75 2C 40 4F F6 FC 75 2C 40 0D 88 2C 43 ... -- CPU_WriteMem(356 bytes @ 0x20000400)  returns 0x164 (0003ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R0, 0x08000400)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R1, 0x00000400)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R2, 0x20000164)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14296ms total)
+T06D0 790:994 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0001ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(R15 (PC), 0x200000F4)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14297ms total)
+T06D0 790:995 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x0000000B (0000ms, 14297ms total)
+T06D0 790:995 JLINK_Go() (0001ms, 14298ms total)
+T06D0 790:996 JLINK_IsHalted()  returns FALSE (0001ms, 14299ms total)
+T06D0 791:001 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:003 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:007 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:009 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:011 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:013 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:018 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:020 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:022 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:024 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:026 JLINK_IsHalted()  returns FALSE (0000ms, 14298ms total)
+T06D0 791:028 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0003ms, 14301ms total)
+T06D0 791:031 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14298ms total)
+T06D0 791:032 JLINK_ClrBPEx(BPHandle = 0x0000000B)  returns 0x00 (0000ms, 14298ms total)
+T06D0 791:032 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14298ms total)
+T06D0 791:032 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 98 42 05 D0 0D 4B 98 42 02 D0 0D 4B 98 42 01 D1 ... -- CPU_WriteMem(668 bytes @ 0x20000164)  returns 0x29C (0006ms, 14304ms total)
+T06D0 791:038 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... -- CPU_WriteMem(356 bytes @ 0x20000400)  returns 0x164 (0004ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R0, 0x08000800)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R1, 0x0000026C)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R2, 0x20000164)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(R15 (PC), 0x200000F4)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14308ms total)
+T06D0 791:042 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x0000000C (0000ms, 14308ms total)
+T06D0 791:042 JLINK_Go() (0001ms, 14309ms total)
+T06D0 791:043 JLINK_IsHalted()  returns FALSE (0001ms, 14310ms total)
+T06D0 791:049 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:051 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:053 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:055 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:057 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:059 JLINK_IsHalted()  returns FALSE (0000ms, 14309ms total)
+T06D0 791:066 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14313ms total)
+T06D0 791:070 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_ClrBPEx(BPHandle = 0x0000000C)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R0, 0x00000002)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R1, 0x0000026C)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R2, 0x20000164)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(R15 (PC), 0x2000006A)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14309ms total)
+T06D0 791:070 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x0000000D (0000ms, 14309ms total)
+T06D0 791:070 JLINK_Go() (0002ms, 14311ms total)
+T06D0 791:072 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14315ms total)
+T06D0 791:076 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14311ms total)
+T06D0 791:076 JLINK_ClrBPEx(BPHandle = 0x0000000D)  returns 0x00 (0000ms, 14311ms total)
+T06D0 791:076 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14311ms total)
+T06D0 791:134 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000)  returns 0x164 (0004ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R0, 0x08000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R1, 0x00B71B00)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R2, 0x00000003)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R3, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(R15 (PC), 0x20000038)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14315ms total)
+T06D0 791:138 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000)  returns 0x0000000E (0001ms, 14316ms total)
+T06D0 791:139 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) (0002ms, 14318ms total)
+T06D0 791:141 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14322ms total)
+T06D0 791:145 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_ClrBPEx(BPHandle = 0x0000000E)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R0, 0xFFFFFFFF)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R1, 0x08000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R2, 0x00000A6C)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R3, 0x04C11DB7)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(R15 (PC), 0x20000002)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14318ms total)
+T06D0 791:145 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x0000000F (0000ms, 14318ms total)
+T06D0 791:145 JLINK_Go() (0002ms, 14320ms total)
+T06D0 791:147 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:153 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:155 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:157 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:159 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:163 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:165 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:167 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:169 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:171 JLINK_IsHalted()  returns FALSE (0000ms, 14320ms total)
+T06D0 791:177 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14324ms total)
+T06D0 791:181 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14320ms total)
+T06D0 791:181 JLINK_ClrBPEx(BPHandle = 0x0000000F)  returns 0x00 (0000ms, 14320ms total)
+T06D0 791:181 JLINK_ReadReg(R0)  returns 0x48624F75 (0000ms, 14320ms total)
+T06D0 791:181 JLINK_WriteReg(R0, 0x00000003)  returns 0x00 (0001ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R1, 0x08000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R2, 0x00000A6C)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R3, 0x04C11DB7)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R4, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R5, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R6, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R7, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R8, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R9, 0x20000160)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R10, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R11, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R12, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R13 (SP), 0x20001000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R14, 0x20000001)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(R15 (PC), 0x2000006A)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(XPSR, 0x01000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(MSP, 0x20001000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(PSP, 0x20001000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_WriteReg(CFBP, 0x00000000)  returns 0x00 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)  returns 0x00000010 (0000ms, 14321ms total)
+T06D0 791:182 JLINK_Go() (0001ms, 14322ms total)
+T06D0 791:183 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000)  returns TRUE (0004ms, 14326ms total)
+T06D0 791:187 JLINK_ReadReg(R15 (PC))  returns 0x20000000 (0000ms, 14322ms total)
+T06D0 791:187 JLINK_ClrBPEx(BPHandle = 0x00000010)  returns 0x00 (0000ms, 14322ms total)
+T06D0 791:187 JLINK_ReadReg(R0)  returns 0x00000000 (0000ms, 14322ms total)
+T06D0 791:243 JLINK_WriteMemEx(0x20000000, 0x0002 Bytes, ..., AccessWidth = 33554432) - Data: FE E7Mis-aligned memory write: Address: 0x20000000, NumBytes: 2, Alignment: 2 (Halfword-aligned)
+  ***** Mis-aligned memory write: Address: 0x20000000, NumBytes: 2, Alignment: 2 (Halfword-aligned) -- CPU_WriteMem(2 bytes @ 0x20000000)  returns 0x02 (0005ms, 14327ms total)
+T06D0 791:544 JLINK_Close() >0x80 JTAG> >0x08 JTAG> (0003ms, 14330ms total)
+T06D0 791:544  (0003ms, 14330ms total)
+T06D0 791:544 Closed (0003ms, 14330ms total)
diff --git a/steper/stm32/Listings/MG955.map b/steper/stm32/Listings/MG955.map
new file mode 100644
index 0000000..b76d8f8
--- /dev/null
+++ b/steper/stm32/Listings/MG955.map
@@ -0,0 +1,851 @@
+Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]
+
+==============================================================================
+
+Section Cross References
+
+    main.o(i.GPIO_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+    main.o(i.RCC_Configuration) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
+    main.o(i.RCC_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+    main.o(i.main) refers to main.o(i.RCC_Configuration) for RCC_Configuration
+    main.o(i.main) refers to main.o(i.GPIO_Configuration) for GPIO_Configuration
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_OC1Init) for TIM_OC1Init
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_OC2Init) for TIM_OC2Init
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_OC3Init) for TIM_OC3Init
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_OC4Init) for TIM_OC4Init
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd
+    main.o(i.main) refers to stm32f10x_tim.o(i.TIM_CtrlPWMOutputs) for TIM_CtrlPWMOutputs
+    main.o(i.main) refers to main.o(i.sleep1sec) for sleep1sec
+    main.o(i.main) refers to main.o(.bss) for TIM_TimeBaseStructure
+    main.o(i.main) refers to main.o(.data) for CCR1_Val
+    stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+    stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+    stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable
+    stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
+    stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+    stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
+    stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
+    stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI3_Config) for TI3_Config
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI4_Config) for TI4_Config
+    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler
+    stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
+    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
+    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
+    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
+    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_GetPortClockState) for GPIO_GetPortClockState
+    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_PortClock) for GPIO_PortClock
+    startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
+    startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
+    startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+    startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
+    startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main
+    startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem
+    startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem
+    system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
+    system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
+    system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
+    __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
+    __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
+    __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main
+    __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
+    __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
+    __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
+    __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
+    sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
+    sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap
+    exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
+    libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
+    libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+    rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+    rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
+    libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+    libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+    rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
+    rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
+    rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
+    argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
+    sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+    sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+    _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
+    _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
+    _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1
+    libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1
+    sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+    sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+    defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+    defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+    rt_raise.o(.text) refers to __raise.o(.text) for __raise
+    rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit
+    defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit
+    defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
+    defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch
+    sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+    sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+    defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+    defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+    defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+    Removing main.o(.rev16_text), (4 bytes).
+    Removing main.o(.revsh_text), (4 bytes).
+    Removing main.o(.rrx_text), (6 bytes).
+    Removing misc.o(.rev16_text), (4 bytes).
+    Removing misc.o(.revsh_text), (4 bytes).
+    Removing misc.o(.rrx_text), (6 bytes).
+    Removing misc.o(i.NVIC_Init), (112 bytes).
+    Removing misc.o(i.NVIC_PriorityGroupConfig), (20 bytes).
+    Removing misc.o(i.NVIC_SetVectorTable), (20 bytes).
+    Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes).
+    Removing misc.o(i.SysTick_CLKSourceConfig), (40 bytes).
+    Removing stm32f10x_gpio.o(.rev16_text), (4 bytes).
+    Removing stm32f10x_gpio.o(.revsh_text), (4 bytes).
+    Removing stm32f10x_gpio.o(.rrx_text), (6 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (20 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_DeInit), (200 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (64 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (32 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (18 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_PinRemapConfig), (144 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (8 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (18 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (8 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (18 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_ResetBits), (4 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_SetBits), (4 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes).
+    Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes).
+    Removing stm32f10x_rcc.o(.rev16_text), (4 bytes).
+    Removing stm32f10x_rcc.o(.revsh_text), (4 bytes).
+    Removing stm32f10x_rcc.o(.rrx_text), (6 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_DeInit), (76 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_GetClocksFreq), (212 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_GetFlagStatus), (60 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (76 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (28 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (24 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes).
+    Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (56 bytes).
+    Removing stm32f10x_rcc.o(.data), (20 bytes).
+    Removing stm32f10x_tim.o(.rev16_text), (4 bytes).
+    Removing stm32f10x_tim.o(.revsh_text), (4 bytes).
+    Removing stm32f10x_tim.o(.rrx_text), (6 bytes).
+    Removing stm32f10x_tim.o(i.TI1_Config), (128 bytes).
+    Removing stm32f10x_tim.o(i.TI2_Config), (152 bytes).
+    Removing stm32f10x_tim.o(i.TI3_Config), (144 bytes).
+    Removing stm32f10x_tim.o(i.TI4_Config), (152 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ARRPreloadConfig), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (32 bytes).
+    Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_CCxCmd), (30 bytes).
+    Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (30 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearITPendingBit), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_DMACmd), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_DMAConfig), (10 bytes).
+    Removing stm32f10x_tim.o(i.TIM_DeInit), (488 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (54 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (32 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ETRConfig), (28 bytes).
+    Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (66 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetCapture1), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetCapture2), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetCapture3), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetCapture4), (8 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetCounter), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetITStatus), (34 bytes).
+    Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ICInit), (172 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ICStructInit), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ITConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (12 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OC4PreloadConfig), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes).
+    Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (124 bytes).
+    Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectCOM), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (82 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetCompare4), (6 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetCounter), (4 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (26 bytes).
+    Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (62 bytes).
+    Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes).
+    Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (24 bytes).
+    Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (24 bytes).
+    Removing gpio_stm32f10x.o(.rev16_text), (4 bytes).
+    Removing gpio_stm32f10x.o(.revsh_text), (4 bytes).
+    Removing gpio_stm32f10x.o(.rrx_text), (6 bytes).
+    Removing gpio_stm32f10x.o(i.GPIO_AFConfigure), (156 bytes).
+    Removing gpio_stm32f10x.o(i.GPIO_GetPortClockState), (152 bytes).
+    Removing gpio_stm32f10x.o(i.GPIO_PinConfigure), (120 bytes).
+    Removing gpio_stm32f10x.o(i.GPIO_PortClock), (316 bytes).
+    Removing system_stm32f10x.o(.rev16_text), (4 bytes).
+    Removing system_stm32f10x.o(.revsh_text), (4 bytes).
+    Removing system_stm32f10x.o(.rrx_text), (6 bytes).
+    Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
+    Removing system_stm32f10x.o(.data), (20 bytes).
+
+165 unused section(s) (total 5876 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+    Local Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit2.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit3.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardinit1.o ABSOLUTE
+    ../clib/angel/boardlib.s                 0x00000000   Number         0  boardshut.o ABSOLUTE
+    ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_zi.o ABSOLUTE
+    ../clib/angel/handlers.s                 0x00000000   Number         0  __scatter_copy.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  rtexit2.o ABSOLUTE
+    ../clib/angel/kernel.s                   0x00000000   Number         0  __rtentry4.o ABSOLUTE
+    ../clib/angel/rt.s                       0x00000000   Number         0  rt_raise.o ABSOLUTE
+    ../clib/angel/scatter.s                  0x00000000   Number         0  __scatter.o ABSOLUTE
+    ../clib/angel/startup.s                  0x00000000   Number         0  __main.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  libspace.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  use_no_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  indicate_semi.o ABSOLUTE
+    ../clib/angel/sys.s                      0x00000000   Number         0  sys_stackheap_outer.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_command.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_wrch.o ABSOLUTE
+    ../clib/angel/sysapp.c                   0x00000000   Number         0  sys_exit.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  argv_veneer.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  _get_argv_nomalloc.o ABSOLUTE
+    ../clib/armsys.c                         0x00000000   Number         0  no_argv.o ABSOLUTE
+    ../clib/heapalloc.c                      0x00000000   Number         0  hrguard.o ABSOLUTE
+    ../clib/heapaux.c                        0x00000000   Number         0  heapauxi.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libshutdown2.o ABSOLUTE
+    ../clib/libinit.s                        0x00000000   Number         0  libinit2.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtred_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_fpe_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_abrt_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_general.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  __raise.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_exit.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_formal.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_outer.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_rtmem_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_other.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_segv_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_cppl_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_pvfn_inner.o ABSOLUTE
+    ../clib/signal.c                         0x00000000   Number         0  defsig_stak_inner.o ABSOLUTE
+    ../clib/signal.s                         0x00000000   Number         0  defsig.o ABSOLUTE
+    ../clib/stdlib.c                         0x00000000   Number         0  exit.o ABSOLUTE
+    ../fplib/fpinit.s                        0x00000000   Number         0  fpinit.o ABSOLUTE
+    D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\misc.c 0x00000000   Number         0  misc.o ABSOLUTE
+    D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_gpio.c 0x00000000   Number         0  stm32f10x_gpio.o ABSOLUTE
+    D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_rcc.c 0x00000000   Number         0  stm32f10x_rcc.o ABSOLUTE
+    D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\Device\\StdPeriph_Driver\\src\\stm32f10x_tim.c 0x00000000   Number         0  stm32f10x_tim.o ABSOLUTE
+    D:\\keil_arm_pack\\Keil\\STM32F1xx_DFP\\2.2.0\\RTE_Driver\\GPIO_STM32F10x.c 0x00000000   Number         0  gpio_stm32f10x.o ABSOLUTE
+    D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\misc.c 0x00000000   Number         0  misc.o ABSOLUTE
+    D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_gpio.c 0x00000000   Number         0  stm32f10x_gpio.o ABSOLUTE
+    D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_rcc.c 0x00000000   Number         0  stm32f10x_rcc.o ABSOLUTE
+    D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_tim.c 0x00000000   Number         0  stm32f10x_tim.o ABSOLUTE
+    D:\keil_arm_pack\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.c 0x00000000   Number         0  gpio_stm32f10x.o ABSOLUTE
+    RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000   Number         0  startup_stm32f10x_md.o ABSOLUTE
+    RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
+    RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
+    dc.s                                     0x00000000   Number         0  dc.o ABSOLUTE
+    main.c                                   0x00000000   Number         0  main.o ABSOLUTE
+    main.c                                   0x00000000   Number         0  main.o ABSOLUTE
+    RESET                                    0x08000000   Section      236  startup_stm32f10x_md.o(RESET)
+    !!!main                                  0x080000ec   Section        8  __main.o(!!!main)
+    !!!scatter                               0x080000f4   Section       52  __scatter.o(!!!scatter)
+    !!handler_copy                           0x08000128   Section       26  __scatter_copy.o(!!handler_copy)
+    !!handler_zi                             0x08000144   Section       28  __scatter_zi.o(!!handler_zi)
+    .ARM.Collect$$libinit$$00000000          0x08000160   Section        2  libinit.o(.ARM.Collect$$libinit$$00000000)
+    .ARM.Collect$$libinit$$00000002          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000002)
+    .ARM.Collect$$libinit$$00000004          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000004)
+    .ARM.Collect$$libinit$$0000000A          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
+    .ARM.Collect$$libinit$$0000000C          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
+    .ARM.Collect$$libinit$$0000000E          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
+    .ARM.Collect$$libinit$$00000011          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000011)
+    .ARM.Collect$$libinit$$00000013          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000013)
+    .ARM.Collect$$libinit$$00000015          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000015)
+    .ARM.Collect$$libinit$$00000017          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000017)
+    .ARM.Collect$$libinit$$00000019          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000019)
+    .ARM.Collect$$libinit$$0000001B          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
+    .ARM.Collect$$libinit$$0000001D          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
+    .ARM.Collect$$libinit$$0000001F          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
+    .ARM.Collect$$libinit$$00000021          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000021)
+    .ARM.Collect$$libinit$$00000023          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000023)
+    .ARM.Collect$$libinit$$00000025          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000025)
+    .ARM.Collect$$libinit$$0000002C          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
+    .ARM.Collect$$libinit$$0000002E          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
+    .ARM.Collect$$libinit$$00000030          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000030)
+    .ARM.Collect$$libinit$$00000032          0x08000162   Section        0  libinit2.o(.ARM.Collect$$libinit$$00000032)
+    .ARM.Collect$$libinit$$00000033          0x08000162   Section        2  libinit2.o(.ARM.Collect$$libinit$$00000033)
+    .ARM.Collect$$libshutdown$$00000000      0x08000164   Section        2  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+    .ARM.Collect$$libshutdown$$00000002      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+    .ARM.Collect$$libshutdown$$00000004      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+    .ARM.Collect$$libshutdown$$00000007      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+    .ARM.Collect$$libshutdown$$0000000A      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+    .ARM.Collect$$libshutdown$$0000000C      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+    .ARM.Collect$$libshutdown$$0000000F      0x08000166   Section        0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+    .ARM.Collect$$libshutdown$$00000010      0x08000166   Section        2  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+    .ARM.Collect$$rtentry$$00000000          0x08000168   Section        0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+    .ARM.Collect$$rtentry$$00000002          0x08000168   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+    .ARM.Collect$$rtentry$$00000004          0x08000168   Section        6  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+    .ARM.Collect$$rtentry$$00000009          0x0800016e   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+    .ARM.Collect$$rtentry$$0000000A          0x0800016e   Section        4  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+    .ARM.Collect$$rtentry$$0000000C          0x08000172   Section        0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+    .ARM.Collect$$rtentry$$0000000D          0x08000172   Section        8  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+    .ARM.Collect$$rtexit$$00000000           0x0800017a   Section        2  rtexit.o(.ARM.Collect$$rtexit$$00000000)
+    .ARM.Collect$$rtexit$$00000002           0x0800017c   Section        0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+    .ARM.Collect$$rtexit$$00000003           0x0800017c   Section        4  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+    .ARM.Collect$$rtexit$$00000004           0x08000180   Section        6  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+    .text                                    0x08000188   Section       64  startup_stm32f10x_md.o(.text)
+    .text                                    0x080001c8   Section        0  heapauxi.o(.text)
+    .text                                    0x080001ce   Section       74  sys_stackheap_outer.o(.text)
+    .text                                    0x08000218   Section        0  exit.o(.text)
+    .text                                    0x0800022c   Section        8  libspace.o(.text)
+    .text                                    0x08000234   Section        0  sys_exit.o(.text)
+    .text                                    0x08000240   Section        2  use_no_semi.o(.text)
+    .text                                    0x08000242   Section        0  indicate_semi.o(.text)
+    i.GPIO_Configuration                     0x08000244   Section        0  main.o(i.GPIO_Configuration)
+    i.GPIO_Init                              0x0800027c   Section        0  stm32f10x_gpio.o(i.GPIO_Init)
+    i.RCC_APB2PeriphClockCmd                 0x08000394   Section        0  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
+    i.RCC_Configuration                      0x080003b4   Section        0  main.o(i.RCC_Configuration)
+    i.SetSysClock                            0x080003c6   Section        0  system_stm32f10x.o(i.SetSysClock)
+    SetSysClock                              0x080003c7   Thumb Code     8  system_stm32f10x.o(i.SetSysClock)
+    i.SetSysClockTo72                        0x080003d0   Section        0  system_stm32f10x.o(i.SetSysClockTo72)
+    SetSysClockTo72                          0x080003d1   Thumb Code   214  system_stm32f10x.o(i.SetSysClockTo72)
+    i.SystemInit                             0x080004b0   Section        0  system_stm32f10x.o(i.SystemInit)
+    i.TIM_Cmd                                0x08000510   Section        0  stm32f10x_tim.o(i.TIM_Cmd)
+    i.TIM_CtrlPWMOutputs                     0x08000528   Section        0  stm32f10x_tim.o(i.TIM_CtrlPWMOutputs)
+    i.TIM_OC1Init                            0x08000548   Section        0  stm32f10x_tim.o(i.TIM_OC1Init)
+    i.TIM_OC2Init                            0x080005e0   Section        0  stm32f10x_tim.o(i.TIM_OC2Init)
+    i.TIM_OC3Init                            0x08000684   Section        0  stm32f10x_tim.o(i.TIM_OC3Init)
+    i.TIM_OC4Init                            0x08000724   Section        0  stm32f10x_tim.o(i.TIM_OC4Init)
+    i.TIM_TimeBaseInit                       0x080007a0   Section        0  stm32f10x_tim.o(i.TIM_TimeBaseInit)
+    i.main                                   0x08000844   Section        0  main.o(i.main)
+    i.sleep1sec                              0x08000a20   Section        0  main.o(i.sleep1sec)
+    .data                                    0x20000000   Section       12  main.o(.data)
+    .bss                                     0x2000000c   Section       26  main.o(.bss)
+    .bss                                     0x20000028   Section       96  libspace.o(.bss)
+    HEAP                                     0x20000088   Section      512  startup_stm32f10x_md.o(HEAP)
+    Heap_Mem                                 0x20000088   Data         512  startup_stm32f10x_md.o(HEAP)
+    STACK                                    0x20000288   Section     1024  startup_stm32f10x_md.o(STACK)
+    Stack_Mem                                0x20000288   Data        1024  startup_stm32f10x_md.o(STACK)
+    __initial_sp                             0x20000688   Data           0  startup_stm32f10x_md.o(STACK)
+
+    Global Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000   Number         0  anon$$obj.o ABSOLUTE
+    __ARM_use_no_argv                        0x00000000   Number         0  main.o ABSOLUTE
+    __ARM_exceptions_init                     - Undefined Weak Reference
+    __alloca_initialize                       - Undefined Weak Reference
+    __arm_preinit_                            - Undefined Weak Reference
+    __cpp_initialize__aeabi_                  - Undefined Weak Reference
+    __cxa_finalize                            - Undefined Weak Reference
+    __rt_locale                               - Undefined Weak Reference
+    __sigvec_lookup                           - Undefined Weak Reference
+    _atexit_init                              - Undefined Weak Reference
+    _call_atexit_fns                          - Undefined Weak Reference
+    _clock_init                               - Undefined Weak Reference
+    _fp_trap_init                             - Undefined Weak Reference
+    _fp_trap_shutdown                         - Undefined Weak Reference
+    _get_lc_collate                           - Undefined Weak Reference
+    _get_lc_ctype                             - Undefined Weak Reference
+    _get_lc_monetary                          - Undefined Weak Reference
+    _get_lc_numeric                           - Undefined Weak Reference
+    _get_lc_time                              - Undefined Weak Reference
+    _getenv_init                              - Undefined Weak Reference
+    _handle_redirection                       - Undefined Weak Reference
+    _init_alloc                               - Undefined Weak Reference
+    _init_user_alloc                          - Undefined Weak Reference
+    _initio                                   - Undefined Weak Reference
+    _rand_init                                - Undefined Weak Reference
+    _signal_finish                            - Undefined Weak Reference
+    _signal_init                              - Undefined Weak Reference
+    _terminate_alloc                          - Undefined Weak Reference
+    _terminate_user_alloc                     - Undefined Weak Reference
+    _terminateio                              - Undefined Weak Reference
+    __Vectors_Size                           0x000000ec   Number         0  startup_stm32f10x_md.o ABSOLUTE
+    __Vectors                                0x08000000   Data           4  startup_stm32f10x_md.o(RESET)
+    __Vectors_End                            0x080000ec   Data           0  startup_stm32f10x_md.o(RESET)
+    __main                                   0x080000ed   Thumb Code     8  __main.o(!!!main)
+    __scatterload                            0x080000f5   Thumb Code     0  __scatter.o(!!!scatter)
+    __scatterload_rt2                        0x080000f5   Thumb Code    44  __scatter.o(!!!scatter)
+    __scatterload_rt2_thumb_only             0x080000f5   Thumb Code     0  __scatter.o(!!!scatter)
+    __scatterload_null                       0x08000103   Thumb Code     0  __scatter.o(!!!scatter)
+    __scatterload_copy                       0x08000129   Thumb Code    26  __scatter_copy.o(!!handler_copy)
+    __scatterload_zeroinit                   0x08000145   Thumb Code    28  __scatter_zi.o(!!handler_zi)
+    __rt_lib_init                            0x08000161   Thumb Code     0  libinit.o(.ARM.Collect$$libinit$$00000000)
+    __rt_lib_init_alloca_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002E)
+    __rt_lib_init_argv_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000002C)
+    __rt_lib_init_atexit_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001B)
+    __rt_lib_init_clock_1                    0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000021)
+    __rt_lib_init_cpp_1                      0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000032)
+    __rt_lib_init_exceptions_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000030)
+    __rt_lib_init_fp_1                       0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000002)
+    __rt_lib_init_fp_trap_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001F)
+    __rt_lib_init_getenv_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000023)
+    __rt_lib_init_heap_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000A)
+    __rt_lib_init_lc_collate_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000011)
+    __rt_lib_init_lc_ctype_1                 0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000013)
+    __rt_lib_init_lc_monetary_1              0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000015)
+    __rt_lib_init_lc_numeric_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000017)
+    __rt_lib_init_lc_time_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000019)
+    __rt_lib_init_preinit_1                  0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000004)
+    __rt_lib_init_rand_1                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000E)
+    __rt_lib_init_return                     0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000033)
+    __rt_lib_init_signal_1                   0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000001D)
+    __rt_lib_init_stdio_1                    0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$00000025)
+    __rt_lib_init_user_alloc_1               0x08000163   Thumb Code     0  libinit2.o(.ARM.Collect$$libinit$$0000000C)
+    __rt_lib_shutdown                        0x08000165   Thumb Code     0  libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+    __rt_lib_shutdown_cpp_1                  0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+    __rt_lib_shutdown_fp_trap_1              0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+    __rt_lib_shutdown_heap_1                 0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+    __rt_lib_shutdown_return                 0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+    __rt_lib_shutdown_signal_1               0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+    __rt_lib_shutdown_stdio_1                0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+    __rt_lib_shutdown_user_alloc_1           0x08000167   Thumb Code     0  libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+    __rt_entry                               0x08000169   Thumb Code     0  __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+    __rt_entry_presh_1                       0x08000169   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+    __rt_entry_sh                            0x08000169   Thumb Code     0  __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+    __rt_entry_li                            0x0800016f   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+    __rt_entry_postsh_1                      0x0800016f   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+    __rt_entry_main                          0x08000173   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+    __rt_entry_postli_1                      0x08000173   Thumb Code     0  __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+    __rt_exit                                0x0800017b   Thumb Code     0  rtexit.o(.ARM.Collect$$rtexit$$00000000)
+    __rt_exit_ls                             0x0800017d   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+    __rt_exit_prels_1                        0x0800017d   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+    __rt_exit_exit                           0x08000181   Thumb Code     0  rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+    Reset_Handler                            0x08000189   Thumb Code     8  startup_stm32f10x_md.o(.text)
+    NMI_Handler                              0x08000191   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    HardFault_Handler                        0x08000193   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    MemManage_Handler                        0x08000195   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    BusFault_Handler                         0x08000197   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    UsageFault_Handler                       0x08000199   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    SVC_Handler                              0x0800019b   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    DebugMon_Handler                         0x0800019d   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    PendSV_Handler                           0x0800019f   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    SysTick_Handler                          0x080001a1   Thumb Code     2  startup_stm32f10x_md.o(.text)
+    ADC1_2_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    CAN1_RX1_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    CAN1_SCE_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel1_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel2_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel3_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel4_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel5_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel6_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    DMA1_Channel7_IRQHandler                 0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI0_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI15_10_IRQHandler                     0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI1_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI2_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI3_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI4_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    EXTI9_5_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    FLASH_IRQHandler                         0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C1_ER_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C1_EV_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C2_ER_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    I2C2_EV_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    PVD_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RCC_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RTCAlarm_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    RTC_IRQHandler                           0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    SPI1_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    SPI2_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TAMPER_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_BRK_IRQHandler                      0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_CC_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_TRG_COM_IRQHandler                  0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM1_UP_IRQHandler                       0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM2_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM3_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    TIM4_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART1_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART2_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USART3_IRQHandler                        0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USBWakeUp_IRQHandler                     0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USB_HP_CAN1_TX_IRQHandler                0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    USB_LP_CAN1_RX0_IRQHandler               0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    WWDG_IRQHandler                          0x080001a3   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    __user_initial_stackheap                 0x080001a5   Thumb Code     0  startup_stm32f10x_md.o(.text)
+    __use_two_region_memory                  0x080001c9   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_escrow$2region                 0x080001cb   Thumb Code     2  heapauxi.o(.text)
+    __rt_heap_expand$2region                 0x080001cd   Thumb Code     2  heapauxi.o(.text)
+    __user_setup_stackheap                   0x080001cf   Thumb Code    74  sys_stackheap_outer.o(.text)
+    exit                                     0x08000219   Thumb Code    18  exit.o(.text)
+    __user_libspace                          0x0800022d   Thumb Code     8  libspace.o(.text)
+    __user_perproc_libspace                  0x0800022d   Thumb Code     0  libspace.o(.text)
+    __user_perthread_libspace                0x0800022d   Thumb Code     0  libspace.o(.text)
+    _sys_exit                                0x08000235   Thumb Code     8  sys_exit.o(.text)
+    __I$use$semihosting                      0x08000241   Thumb Code     0  use_no_semi.o(.text)
+    __use_no_semihosting_swi                 0x08000241   Thumb Code     2  use_no_semi.o(.text)
+    __semihosting_library_function           0x08000243   Thumb Code     0  indicate_semi.o(.text)
+    GPIO_Configuration                       0x08000245   Thumb Code    48  main.o(i.GPIO_Configuration)
+    GPIO_Init                                0x0800027d   Thumb Code   278  stm32f10x_gpio.o(i.GPIO_Init)
+    RCC_APB2PeriphClockCmd                   0x08000395   Thumb Code    26  stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
+    RCC_Configuration                        0x080003b5   Thumb Code    18  main.o(i.RCC_Configuration)
+    SystemInit                               0x080004b1   Thumb Code    78  system_stm32f10x.o(i.SystemInit)
+    TIM_Cmd                                  0x08000511   Thumb Code    24  stm32f10x_tim.o(i.TIM_Cmd)
+    TIM_CtrlPWMOutputs                       0x08000529   Thumb Code    30  stm32f10x_tim.o(i.TIM_CtrlPWMOutputs)
+    TIM_OC1Init                              0x08000549   Thumb Code   132  stm32f10x_tim.o(i.TIM_OC1Init)
+    TIM_OC2Init                              0x080005e1   Thumb Code   154  stm32f10x_tim.o(i.TIM_OC2Init)
+    TIM_OC3Init                              0x08000685   Thumb Code   150  stm32f10x_tim.o(i.TIM_OC3Init)
+    TIM_OC4Init                              0x08000725   Thumb Code   114  stm32f10x_tim.o(i.TIM_OC4Init)
+    TIM_TimeBaseInit                         0x080007a1   Thumb Code   122  stm32f10x_tim.o(i.TIM_TimeBaseInit)
+    main                                     0x08000845   Thumb Code   442  main.o(i.main)
+    sleep1sec                                0x08000a21   Thumb Code    30  main.o(i.sleep1sec)
+    Region$$Table$$Base                      0x08000a40   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x08000a60   Number         0  anon$$obj.o(Region$$Table)
+    CCR1_Val                                 0x20000000   Data           2  main.o(.data)
+    CCR2_Val                                 0x20000002   Data           2  main.o(.data)
+    CCR3_Val                                 0x20000004   Data           2  main.o(.data)
+    CCR4_Val                                 0x20000006   Data           2  main.o(.data)
+    down                                     0x20000008   Data           4  main.o(.data)
+    TIM_TimeBaseStructure                    0x2000000c   Data          10  main.o(.bss)
+    TIM_OCInitStructure                      0x20000016   Data          16  main.o(.bss)
+    __libspace_start                         0x20000028   Data          96  libspace.o(.bss)
+    __temporary_stack_top$libspace           0x20000088   Data           0  libspace.o(.bss)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x08000189
+
+  Load Region LR_1 (Base: 0x08000000, Size: 0x00000a6c, Max: 0xffffffff, ABSOLUTE)
+
+    Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00000a60, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x08000000   0x08000000   0x000000ec   Data   RO         1087    RESET               startup_stm32f10x_md.o
+    0x080000ec   0x080000ec   0x00000008   Code   RO         1142  * !!!main             c_w.l(__main.o)
+    0x080000f4   0x080000f4   0x00000034   Code   RO         1299    !!!scatter          c_w.l(__scatter.o)
+    0x08000128   0x08000128   0x0000001a   Code   RO         1301    !!handler_copy      c_w.l(__scatter_copy.o)
+    0x08000142   0x08000142   0x00000002   PAD
+    0x08000144   0x08000144   0x0000001c   Code   RO         1303    !!handler_zi        c_w.l(__scatter_zi.o)
+    0x08000160   0x08000160   0x00000002   Code   RO         1169    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1176    .ARM.Collect$$libinit$$00000002  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1178    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1181    .ARM.Collect$$libinit$$0000000A  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1183    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1185    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1188    .ARM.Collect$$libinit$$00000011  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1190    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1192    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1194    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1196    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1198    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1200    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1202    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1204    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1206    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1208    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1212    .ARM.Collect$$libinit$$0000002C  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1214    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1216    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000000   Code   RO         1218    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
+    0x08000162   0x08000162   0x00000002   Code   RO         1219    .ARM.Collect$$libinit$$00000033  c_w.l(libinit2.o)
+    0x08000164   0x08000164   0x00000002   Code   RO         1239    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1252    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1254    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1257    .ARM.Collect$$libshutdown$$00000007  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1260    .ARM.Collect$$libshutdown$$0000000A  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1262    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000000   Code   RO         1265    .ARM.Collect$$libshutdown$$0000000F  c_w.l(libshutdown2.o)
+    0x08000166   0x08000166   0x00000002   Code   RO         1266    .ARM.Collect$$libshutdown$$00000010  c_w.l(libshutdown2.o)
+    0x08000168   0x08000168   0x00000000   Code   RO         1144    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
+    0x08000168   0x08000168   0x00000000   Code   RO         1146    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
+    0x08000168   0x08000168   0x00000006   Code   RO         1158    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
+    0x0800016e   0x0800016e   0x00000000   Code   RO         1148    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
+    0x0800016e   0x0800016e   0x00000004   Code   RO         1149    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
+    0x08000172   0x08000172   0x00000000   Code   RO         1151    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
+    0x08000172   0x08000172   0x00000008   Code   RO         1152    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
+    0x0800017a   0x0800017a   0x00000002   Code   RO         1173    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
+    0x0800017c   0x0800017c   0x00000000   Code   RO         1221    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
+    0x0800017c   0x0800017c   0x00000004   Code   RO         1222    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
+    0x08000180   0x08000180   0x00000006   Code   RO         1223    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
+    0x08000186   0x08000186   0x00000002   PAD
+    0x08000188   0x08000188   0x00000040   Code   RO         1088  * .text               startup_stm32f10x_md.o
+    0x080001c8   0x080001c8   0x00000006   Code   RO         1140    .text               c_w.l(heapauxi.o)
+    0x080001ce   0x080001ce   0x0000004a   Code   RO         1160    .text               c_w.l(sys_stackheap_outer.o)
+    0x08000218   0x08000218   0x00000012   Code   RO         1162    .text               c_w.l(exit.o)
+    0x0800022a   0x0800022a   0x00000002   PAD
+    0x0800022c   0x0800022c   0x00000008   Code   RO         1170    .text               c_w.l(libspace.o)
+    0x08000234   0x08000234   0x0000000c   Code   RO         1231    .text               c_w.l(sys_exit.o)
+    0x08000240   0x08000240   0x00000002   Code   RO         1242    .text               c_w.l(use_no_semi.o)
+    0x08000242   0x08000242   0x00000000   Code   RO         1244    .text               c_w.l(indicate_semi.o)
+    0x08000242   0x08000242   0x00000002   PAD
+    0x08000244   0x08000244   0x00000038   Code   RO            4    i.GPIO_Configuration  main.o
+    0x0800027c   0x0800027c   0x00000116   Code   RO          148    i.GPIO_Init         stm32f10x_gpio.o
+    0x08000392   0x08000392   0x00000002   PAD
+    0x08000394   0x08000394   0x00000020   Code   RO          272    i.RCC_APB2PeriphClockCmd  stm32f10x_rcc.o
+    0x080003b4   0x080003b4   0x00000012   Code   RO            5    i.RCC_Configuration  main.o
+    0x080003c6   0x080003c6   0x00000008   Code   RO         1095    i.SetSysClock       system_stm32f10x.o
+    0x080003ce   0x080003ce   0x00000002   PAD
+    0x080003d0   0x080003d0   0x000000e0   Code   RO         1096    i.SetSysClockTo72   system_stm32f10x.o
+    0x080004b0   0x080004b0   0x00000060   Code   RO         1098    i.SystemInit        system_stm32f10x.o
+    0x08000510   0x08000510   0x00000018   Code   RO          496    i.TIM_Cmd           stm32f10x_tim.o
+    0x08000528   0x08000528   0x0000001e   Code   RO          498    i.TIM_CtrlPWMOutputs  stm32f10x_tim.o
+    0x08000546   0x08000546   0x00000002   PAD
+    0x08000548   0x08000548   0x00000098   Code   RO          525    i.TIM_OC1Init       stm32f10x_tim.o
+    0x080005e0   0x080005e0   0x000000a4   Code   RO          530    i.TIM_OC2Init       stm32f10x_tim.o
+    0x08000684   0x08000684   0x000000a0   Code   RO          535    i.TIM_OC3Init       stm32f10x_tim.o
+    0x08000724   0x08000724   0x0000007c   Code   RO          540    i.TIM_OC4Init       stm32f10x_tim.o
+    0x080007a0   0x080007a0   0x000000a4   Code   RO          567    i.TIM_TimeBaseInit  stm32f10x_tim.o
+    0x08000844   0x08000844   0x000001dc   Code   RO            6    i.main              main.o
+    0x08000a20   0x08000a20   0x0000001e   Code   RO            7    i.sleep1sec         main.o
+    0x08000a3e   0x08000a3e   0x00000002   PAD
+    0x08000a40   0x08000a40   0x00000020   Data   RO         1297    Region$$Table       anon$$obj.o
+
+
+    Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x08000a60, Size: 0x0000000c, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x20000000   0x08000a60   0x0000000c   Data   RW            9    .data               main.o
+
+
+    Execution Region ER_ZI (Exec base: 0x2000000c, Load base: 0x08000a6c, Size: 0x0000067c, Max: 0xffffffff, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x2000000c        -       0x0000001a   Zero   RW            8    .bss                main.o
+    0x20000026   0x08000a6c   0x00000002   PAD
+    0x20000028        -       0x00000060   Zero   RW         1171    .bss                c_w.l(libspace.o)
+    0x20000088        -       0x00000200   Zero   RW         1086    HEAP                startup_stm32f10x_md.o
+    0x20000288        -       0x00000400   Zero   RW         1085    STACK               startup_stm32f10x_md.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
+
+       580         42          0         12         26     237697   main.o
+        64         26        236          0       1536        804   startup_stm32f10x_md.o
+       278          0          0          0          0       2184   stm32f10x_gpio.o
+        32          6          0          0          0        601   stm32f10x_rcc.o
+       818         92          0          0          0       5526   stm32f10x_tim.o
+       328         28          0          0          0       2049   system_stm32f10x.o
+
+    ----------------------------------------------------------------------
+      2108        194        268         12       1564     248861   Object Totals
+         0          0         32          0          0          0   (incl. Generated)
+         8          0          0          0          2          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
+
+         8          0          0          0          0         68   __main.o
+         0          0          0          0          0          0   __rtentry.o
+        12          0          0          0          0          0   __rtentry2.o
+         6          0          0          0          0          0   __rtentry4.o
+        52          8          0          0          0          0   __scatter.o
+        26          0          0          0          0          0   __scatter_copy.o
+        28          0          0          0          0          0   __scatter_zi.o
+        18          0          0          0          0         80   exit.o
+         6          0          0          0          0        152   heapauxi.o
+         0          0          0          0          0          0   indicate_semi.o
+         2          0          0          0          0          0   libinit.o
+         2          0          0          0          0          0   libinit2.o
+         2          0          0          0          0          0   libshutdown.o
+         2          0          0          0          0          0   libshutdown2.o
+         8          4          0          0         96         68   libspace.o
+         2          0          0          0          0          0   rtexit.o
+        10          0          0          0          0          0   rtexit2.o
+        12          4          0          0          0         68   sys_exit.o
+        74          0          0          0          0         80   sys_stackheap_outer.o
+         2          0          0          0          0         68   use_no_semi.o
+
+    ----------------------------------------------------------------------
+       280         16          0          0         96        584   Library Totals
+         8          0          0          0          0          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
+
+       272         16          0          0         96        584   c_w.l
+
+    ----------------------------------------------------------------------
+       280         16          0          0         96        584   Library Totals
+
+    ----------------------------------------------------------------------
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+      2388        210        268         12       1660     248557   Grand Totals
+      2388        210        268         12       1660     248557   ELF Image Totals
+      2388        210        268         12          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                 2656 (   2.59kB)
+    Total RW  Size (RW Data + ZI Data)              1672 (   1.63kB)
+    Total ROM Size (Code + RO Data + RW Data)       2668 (   2.61kB)
+
+==============================================================================
+
diff --git a/steper/stm32/MG955.uvoptx b/steper/stm32/MG955.uvoptx
new file mode 100644
index 0000000..48d3f4f
--- /dev/null
+++ b/steper/stm32/MG955.uvoptx
@@ -0,0 +1,240 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target 1</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>d</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U20080643 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("ST TMC") -D01(16410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/steper/stm32/MG955.uvprojx b/steper/stm32/MG955.uvprojx
new file mode 100644
index 0000000..f85c779
--- /dev/null
+++ b/steper/stm32/MG955.uvprojx
@@ -0,0 +1,484 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target 1</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103RB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32F1xx_DFP.2.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F103RB$Device\Include\stm32f10x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F103RB$SVD\STM32F103xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>MG955</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>1</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>src</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.3" condition="STM32F1xx CMSIS">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="Framework" Cvendor="Keil" Cversion="3.5.1" condition="STM32F1xx STDPERIPH">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="GPIO" Cvendor="Keil" Cversion="3.5.0" condition="STM32F1xx STDPERIPH RCC">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="RCC" Cvendor="Keil" Cversion="3.5.0" condition="STM32F1xx STDPERIPH">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="TIM" Cvendor="Keil" Cversion="3.5.0" condition="STM32F1xx STDPERIPH RCC">
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="1.1.2">
+        <instance index="0">RTE\Device\STM32F103RB\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" condition="STM32F1xx MD ARMCC" name="Device\Source\ARM\startup_stm32f10x_md.s" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F103RB\startup_stm32f10x_md.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\StdPeriph_Driver\templates\stm32f10x_conf.h" version="3.5.0">
+        <instance index="0">RTE\Device\STM32F103RB\stm32f10x_conf.h</instance>
+        <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="Framework" Cvendor="Keil" Cversion="3.5.1" condition="STM32F1xx STDPERIPH"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32f10x.c" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F103RB\system_stm32f10x.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>
diff --git a/steper/stm32/Objects/MG955.axf b/steper/stm32/Objects/MG955.axf
new file mode 100644
index 0000000..df1ca64
Binary files /dev/null and b/steper/stm32/Objects/MG955.axf differ
diff --git a/steper/stm32/Objects/MG955.lnp b/steper/stm32/Objects/MG955.lnp
new file mode 100644
index 0000000..ce14ca6
--- /dev/null
+++ b/steper/stm32/Objects/MG955.lnp
@@ -0,0 +1,12 @@
+--cpu Cortex-M3
+".\objects\main.o"
+".\objects\misc.o"
+".\objects\stm32f10x_gpio.o"
+".\objects\stm32f10x_rcc.o"
+".\objects\stm32f10x_tim.o"
+".\objects\gpio_stm32f10x.o"
+".\objects\startup_stm32f10x_md.o"
+".\objects\system_stm32f10x.o"
+--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\Listings\MG955.map" -o .\Objects\MG955.axf
\ No newline at end of file
diff --git a/steper/stm32/RTE/Device/STM32F103RB/RTE_Device.h b/steper/stm32/RTE/Device/STM32F103RB/RTE_Device.h
new file mode 100644
index 0000000..d53b023
--- /dev/null
+++ b/steper/stm32/RTE/Device/STM32F103RB/RTE_Device.h
@@ -0,0 +1,1811 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (C) 2016 ARM Limited. All rights reserved.
+ *
+ * $Date:        29. August 2016
+ * $Revision:    V1.1.2
+ *
+ * Project:      RTE Device Configuration for STMicroelectronics STM32F1xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  NULL)
+
+
+// <h> Clock Configuration
+//   <o> High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         8000000
+//   <o> High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//   <o> System Clock <1-999999999>
+#define RTE_SYSCLK                      72000000
+//   <o> HCLK Clock   <1-999999999>
+#define RTE_HCLK                        72000000
+//   <o> APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       36000000
+//   <o> APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       72000000
+//   <o> ADC Clock    <1-999999999>
+#define RTE_ADCCLK                      36000000
+//       USB Clock
+#define RTE_USBCLK                      48000000
+// </h>
+
+
+// <e> USART1 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1                       0
+
+//   <o> USART1_TX Pin <0=>Not Used <1=>PA9
+#define RTE_USART1_TX_PORT_ID_DEF       0
+#if    (RTE_USART1_TX_PORT_ID_DEF == 0)
+#define RTE_USART1_TX_DEF               0
+#elif  (RTE_USART1_TX_PORT_ID_DEF == 1)
+#define RTE_USART1_TX_DEF               1
+#define RTE_USART1_TX_PORT_DEF          GPIOA
+#define RTE_USART1_TX_BIT_DEF           9
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//   <o> USART1_RX Pin <0=>Not Used <1=>PA10
+#define RTE_USART1_RX_PORT_ID_DEF       0
+#if    (RTE_USART1_RX_PORT_ID_DEF == 0)
+#define RTE_USART1_RX_DEF               0
+#elif  (RTE_USART1_RX_PORT_ID_DEF == 1)
+#define RTE_USART1_RX_DEF               1
+#define RTE_USART1_RX_PORT_DEF          GPIOA
+#define RTE_USART1_RX_BIT_DEF           10
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//   <o> USART1_CK Pin <0=>Not Used <1=>PA8
+#define RTE_USART1_CK_PORT_ID_DEF       0
+#if    (RTE_USART1_CK_PORT_ID_DEF == 0)
+#define RTE_USART1_CK                   0
+#elif  (RTE_USART1_CK_PORT_ID_DEF == 1)
+#define RTE_USART1_CK                   1
+#define RTE_USART1_CK_PORT_DEF          GPIOA
+#define RTE_USART1_CK_BIT_DEF           8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//   <o> USART1_CTS Pin <0=>Not Used <1=>PA11
+#define RTE_USART1_CTS_PORT_ID_DEF      0
+#if    (RTE_USART1_CTS_PORT_ID_DEF == 0)
+#define RTE_USART1_CTS                  0
+#elif  (RTE_USART1_CTS_PORT_ID_DEF == 1)
+#define RTE_USART1_CTS                  1
+#define RTE_USART1_CTS_PORT_DEF         GPIOA
+#define RTE_USART1_CTS_BIT_DEF          11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+
+//   <o> USART1_RTS Pin <0=>Not Used <1=>PA12
+#define RTE_USART1_RTS_PORT_ID_DEF      0
+#if    (RTE_USART1_RTS_PORT_ID_DEF == 0)
+#define RTE_USART1_RTS                  0
+#elif  (RTE_USART1_RTS_PORT_ID_DEF == 1)
+#define RTE_USART1_RTS                  1
+#define RTE_USART1_RTS_PORT_DEF         GPIOA
+#define RTE_USART1_RTS_BIT_DEF          12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//   <e> USART1 Pin Remap
+//   <i> Enable USART1 Pin Remapping
+#define RTE_USART1_REMAP_FULL           0
+
+//     <o> USART1_TX Pin <0=>Not Used <1=>PB6
+#define RTE_USART1_TX_PORT_ID_FULL      0
+#if    (RTE_USART1_TX_PORT_ID_FULL == 0)
+#define RTE_USART1_TX_FULL              0
+#elif  (RTE_USART1_TX_PORT_ID_FULL == 1)
+#define RTE_USART1_TX_FULL              1
+#define RTE_USART1_TX_PORT_FULL         GPIOB
+#define RTE_USART1_TX_BIT_FULL          6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//     <o> USART1_RX Pin <0=>Not Used <1=>PB7
+#define RTE_USART1_RX_PORT_ID_FULL      0
+#if    (RTE_USART1_RX_PORT_ID_FULL == 0)
+#define RTE_USART1_RX_FULL              0
+#elif  (RTE_USART1_RX_PORT_ID_FULL == 1)
+#define RTE_USART1_RX_FULL              1
+#define RTE_USART1_RX_PORT_FULL         GPIOB
+#define RTE_USART1_RX_BIT_FULL          7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART1_REMAP_FULL)
+#define RTE_USART1_AF_REMAP              AFIO_USART1_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_FULL
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_FULL
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_FULL
+#define RTE_USART1_RX                    RTE_USART1_RX_FULL
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_FULL
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_FULL
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#else 
+#define RTE_USART1_AF_REMAP              AFIO_USART1_NO_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_DEF
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_DEF
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_DEF
+#define RTE_USART1_RX                    RTE_USART1_RX_DEF
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_DEF
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_DEF
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_RX_DMA               0
+#define RTE_USART1_RX_DMA_NUMBER        1
+#define RTE_USART1_RX_DMA_CHANNEL       5
+#define RTE_USART1_RX_DMA_PRIORITY      0
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_TX_DMA               0
+#define RTE_USART1_TX_DMA_NUMBER        1
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+// </e>
+
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_USART2                      0
+
+//   <o> USART2_TX Pin <0=>Not Used <1=>PA2
+#define RTE_USART2_TX_PORT_ID_DEF       0
+#if    (RTE_USART2_TX_PORT_ID_DEF == 0)
+#define RTE_USART2_TX_DEF               0
+#elif  (RTE_USART2_TX_PORT_ID_DEF == 1)
+#define RTE_USART2_TX_DEF               1
+#define RTE_USART2_TX_PORT_DEF          GPIOA
+#define RTE_USART2_TX_BIT_DEF           2
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//   <o> USART2_RX Pin <0=>Not Used <1=>PA3
+#define RTE_USART2_RX_PORT_ID_DEF       0
+#if    (RTE_USART2_RX_PORT_ID_DEF == 0)
+#define RTE_USART2_RX_DEF               0
+#elif  (RTE_USART2_RX_PORT_ID_DEF == 1)
+#define RTE_USART2_RX_DEF               1
+#define RTE_USART2_RX_PORT_DEF          GPIOA
+#define RTE_USART2_RX_BIT_DEF           3
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//   <o> USART2_CK Pin <0=>Not Used <1=>PA4
+#define RTE_USART2_CK_PORT_ID_DEF       0
+#if    (RTE_USART2_CK_PORT_ID_DEF == 0)
+#define RTE_USART2_CK_DEF               0
+#elif  (RTE_USART2_CK_PORT_ID_DEF == 1)
+#define RTE_USART2_CK_DEF               1
+#define RTE_USART2_CK_PORT_DEF          GPIOA
+#define RTE_USART2_CK_BIT_DEF           4
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//   <o> USART2_CTS Pin <0=>Not Used <1=>PA0
+#define RTE_USART2_CTS_PORT_ID_DEF      0
+#if    (RTE_USART2_CTS_PORT_ID_DEF == 0)
+#define RTE_USART2_CTS_DEF              0
+#elif  (RTE_USART2_CTS_PORT_ID_DEF == 1)
+#define RTE_USART2_CTS_DEF              1
+#define RTE_USART2_CTS_PORT_DEF         GPIOA
+#define RTE_USART2_CTS_BIT_DEF          0
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//   <o> USART2_RTS Pin <0=>Not Used <1=>PA1
+#define RTE_USART2_RTS_PORT_ID_DEF      0
+#if    (RTE_USART2_RTS_PORT_ID_DEF == 0)
+#define RTE_USART2_RTS_DEF              0
+#elif  (RTE_USART2_RTS_PORT_ID_DEF == 1)
+#define RTE_USART2_RTS_DEF              1
+#define RTE_USART2_RTS_PORT_DEF         GPIOA
+#define RTE_USART2_RTS_BIT_DEF          1
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//   <e> USART2 Pin Remap
+//   <i> Enable USART2 Pin Remapping
+#define RTE_USART2_REMAP_FULL           0
+
+//     <o> USART2_TX Pin <0=>Not Used <1=>PD5
+#define RTE_USART2_TX_PORT_ID_FULL      0
+#if    (RTE_USART2_TX_PORT_ID_FULL == 0)
+#define RTE_USART2_TX_FULL              0
+#elif  (RTE_USART2_TX_PORT_ID_FULL == 1)
+#define RTE_USART2_TX_FULL              1
+#define RTE_USART2_TX_PORT_FULL         GPIOD
+#define RTE_USART2_TX_BIT_FULL          5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//     <o> USART2_RX Pin <0=>Not Used <1=>PD6
+#define RTE_USART2_RX_PORT_ID_FULL      0
+#if    (RTE_USART2_RX_PORT_ID_FULL == 0)
+#define RTE_USART2_RX_FULL              0
+#elif  (RTE_USART2_RX_PORT_ID_FULL == 1)
+#define RTE_USART2_RX_FULL              1
+#define RTE_USART2_RX_PORT_FULL         GPIOD
+#define RTE_USART2_RX_BIT_FULL          6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//     <o> USART2_CK Pin <0=>Not Used <1=>PD7
+#define RTE_USART2_CK_PORT_ID_FULL      0
+#if    (RTE_USART2_CK_PORT_ID_FULL == 0)
+#define RTE_USART2_CK_FULL              0
+#elif  (RTE_USART2_CK_PORT_ID_FULL == 1)
+#define RTE_USART2_CK_FULL              1
+#define RTE_USART2_CK_PORT_FULL         GPIOD
+#define RTE_USART2_CK_BIT_FULL          7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//     <o> USART2_CTS Pin <0=>Not Used <1=>PD3
+#define RTE_USART2_CTS_PORT_ID_FULL     0
+#if    (RTE_USART2_CTS_PORT_ID_FULL == 0)
+#define RTE_USART2_CTS_FULL             0
+#elif  (RTE_USART2_CTS_PORT_ID_FULL == 1)
+#define RTE_USART2_CTS_FULL             1
+#define RTE_USART2_CTS_PORT_FULL        GPIOD
+#define RTE_USART2_CTS_BIT_FULL         3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//     <o> USART2_RTS Pin <0=>Not Used <1=>PD4
+#define RTE_USART2_RTS_PORT_ID_FULL     0
+#if    (RTE_USART2_RTS_PORT_ID_FULL == 0)
+#define RTE_USART2_RTS_FULL             0
+#elif  (RTE_USART2_RTS_PORT_ID_FULL == 1)
+#define RTE_USART2_RTS_FULL             1
+#define RTE_USART2_RTS_PORT_FULL        GPIOD
+#define RTE_USART2_RTS_BIT_FULL         4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART2_REMAP_FULL)
+#define RTE_USART2_AF_REMAP              AFIO_USART2_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_FULL
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_FULL
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_FULL
+#define RTE_USART2_RX                    RTE_USART2_RX_FULL
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_FULL
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_FULL
+#define RTE_USART2_CK                    RTE_USART2_CK_FULL
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_FULL
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_FULL
+#define RTE_USART2_CTS                   RTE_USART2_CTS_FULL
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_FULL
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_FULL
+#define RTE_USART2_RTS                   RTE_USART2_RTS_FULL
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_FULL
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_FULL
+#else 
+#define RTE_USART2_AF_REMAP              AFIO_USART2_NO_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_DEF
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_DEF
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_DEF
+#define RTE_USART2_RX                    RTE_USART2_RX_DEF
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_DEF
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_DEF
+#define RTE_USART2_CK                    RTE_USART2_CK_DEF
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_DEF
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_DEF
+#define RTE_USART2_CTS                   RTE_USART2_CTS_DEF
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_DEF
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_DEF
+#define RTE_USART2_RTS                   RTE_USART2_RTS_DEF
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_DEF
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_RX_DMA               0
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_CHANNEL       6
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_TX_DMA               0
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_CHANNEL       7
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_USART3                      0
+
+//   <o> USART3_TX Pin <0=>Not Used <1=>PB10
+#define RTE_USART3_TX_PORT_ID_DEF       0
+#if    (RTE_USART3_TX_PORT_ID_DEF == 0)
+#define RTE_USART3_TX_DEF               0
+#elif  (RTE_USART3_TX_PORT_ID_DEF == 1)
+#define RTE_USART3_TX_DEF               1
+#define RTE_USART3_TX_PORT_DEF          GPIOB
+#define RTE_USART3_TX_BIT_DEF           10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//   <o> USART3_RX Pin <0=>Not Used <1=>PB11
+#define RTE_USART3_RX_PORT_ID_DEF       0
+#if    (RTE_USART3_RX_PORT_ID_DEF == 0)
+#define RTE_USART3_RX_DEF               0
+#elif  (RTE_USART3_RX_PORT_ID_DEF == 1)
+#define RTE_USART3_RX_DEF               1
+#define RTE_USART3_RX_PORT_DEF          GPIOB
+#define RTE_USART3_RX_BIT_DEF           11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//   <o> USART3_CK Pin <0=>Not Used <1=>PB12
+#define RTE_USART3_CK_PORT_ID_DEF       0
+#if    (RTE_USART3_CK_PORT_ID_DEF == 0)
+#define RTE_USART3_CK_DEF               0
+#elif  (RTE_USART3_CK_PORT_ID_DEF == 1)
+#define RTE_USART3_CK_DEF               1
+#define RTE_USART3_CK_PORT_DEF          GPIOB
+#define RTE_USART3_CK_BIT_DEF           12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//   <o> USART3_CTS Pin <0=>Not Used <1=>PB13
+#define RTE_USART3_CTS_PORT_ID_DEF      0
+#if    (RTE_USART3_CTS_PORT_ID_DEF == 0)
+#define RTE_USART3_CTS_DEF              0
+#elif  (RTE_USART3_CTS_PORT_ID_DEF == 1)
+#define RTE_USART3_CTS_DEF              1
+#define RTE_USART3_CTS_PORT_DEF         GPIOB
+#define RTE_USART3_CTS_BIT_DEF          13
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//   <o> USART3_RTS Pin <0=>Not Used <1=>PB14
+#define RTE_USART3_RTS_PORT_ID_DEF      0
+#if    (RTE_USART3_RTS_PORT_ID_DEF == 0)
+#define RTE_USART3_RTS_DEF              0
+#elif  (RTE_USART3_RTS_PORT_ID_DEF == 1)
+#define RTE_USART3_RTS_DEF              1
+#define RTE_USART3_RTS_PORT_DEF         GPIOB
+#define RTE_USART3_RTS_BIT_DEF          14
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//   <e> USART3 Partial Pin Remap
+//   <i> Enable USART3 Partial Pin Remapping
+#define RTE_USART3_REMAP_PARTIAL        0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PC10
+#define RTE_USART3_TX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_TX_PARTIAL           0
+#elif  (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_TX_PARTIAL           1
+#define RTE_USART3_TX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_TX_BIT_PARTIAL       10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PC11
+#define RTE_USART3_RX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_RX_PARTIAL           0
+#elif  (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_RX_PARTIAL           1
+#define RTE_USART3_RX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_RX_BIT_PARTIAL       11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PC12
+#define RTE_USART3_CK_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_CK_PARTIAL           0
+#elif  (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_CK_PARTIAL           1
+#define RTE_USART3_CK_PORT_PARTIAL      GPIOC
+#define RTE_USART3_CK_BIT_PARTIAL       12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+//   </e>
+
+//   <e> USART3 Full Pin Remap
+//   <i> Enable USART3 Full Pin Remapping
+#define RTE_USART3_REMAP_FULL           0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PD8
+#define RTE_USART3_TX_PORT_ID_FULL      0
+#if    (RTE_USART3_TX_PORT_ID_FULL == 0)
+#define RTE_USART3_TX_FULL              0
+#elif  (RTE_USART3_TX_PORT_ID_FULL == 1)
+#define RTE_USART3_TX_FULL              1
+#define RTE_USART3_TX_PORT_FULL         GPIOD
+#define RTE_USART3_TX_BIT_FULL          8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PD9
+#define RTE_USART3_RX_PORT_ID_FULL      0
+#if    (RTE_USART3_RX_PORT_ID_FULL == 0)
+#define RTE_USART3_RX_FULL              0
+#elif  (RTE_USART3_RX_PORT_ID_FULL == 1)
+#define RTE_USART3_RX_FULL              1
+#define RTE_USART3_RX_PORT_FULL         GPIOD
+#define RTE_USART3_RX_BIT_FULL          9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PD10
+#define RTE_USART3_CK_PORT_ID_FULL      0
+#if    (RTE_USART3_CK_PORT_ID_FULL == 0)
+#define RTE_USART3_CK_FULL              0
+#elif  (RTE_USART3_CK_PORT_ID_FULL == 1)
+#define RTE_USART3_CK_FULL              1
+#define RTE_USART3_CK_PORT_FULL         GPIOD
+#define RTE_USART3_CK_BIT_FULL          10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//     <o> USART3_CTS Pin <0=>Not Used <1=>PD11
+#define RTE_USART3_CTS_PORT_ID_FULL     0
+#if    (RTE_USART3_CTS_PORT_ID_FULL == 0)
+#define RTE_USART3_CTS_FULL             0
+#elif  (RTE_USART3_CTS_PORT_ID_FULL == 1)
+#define RTE_USART3_CTS_FULL             1
+#define RTE_USART3_CTS_PORT_FULL        GPIOD
+#define RTE_USART3_CTS_BIT_FULL         11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//     <o> USART3_RTS Pin <0=>Not Used <1=>PD12
+#define RTE_USART3_RTS_PORT_ID_FULL     0
+#if    (RTE_USART3_RTS_PORT_ID_FULL == 0)
+#define RTE_USART3_RTS_FULL             0
+#elif  (RTE_USART3_RTS_PORT_ID_FULL == 1)
+#define RTE_USART3_RTS_FULL             1
+#define RTE_USART3_RTS_PORT_FULL        GPIOD
+#define RTE_USART3_RTS_BIT_FULL         12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
+#error "Invalid USART3 Pin Remap Configuration!"
+#endif
+
+#if    (RTE_USART3_REMAP_FULL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_FULL
+#define RTE_USART3_TX                    RTE_USART3_TX_FULL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_FULL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_FULL
+#define RTE_USART3_RX                    RTE_USART3_RX_FULL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_FULL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_FULL
+#define RTE_USART3_CK                    RTE_USART3_CK_FULL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_FULL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_FULL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_FULL
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_FULL
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_FULL
+#define RTE_USART3_RTS                   RTE_USART3_RTS_FULL
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_FULL
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_FULL
+#elif  (RTE_USART3_REMAP_PARTIAL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_PARTIAL
+#define RTE_USART3_TX                    RTE_USART3_TX_PARTIAL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_PARTIAL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_PARTIAL
+#define RTE_USART3_RX                    RTE_USART3_RX_PARTIAL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_PARTIAL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_PARTIAL
+#define RTE_USART3_CK                    RTE_USART3_CK_PARTIAL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_PARTIAL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_PARTIAL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#else
+#define RTE_USART3_AF_REMAP              AFIO_USART3_NO_REMAP
+#define RTE_USART3_TX                    RTE_USART3_TX_DEF
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_DEF
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_DEF
+#define RTE_USART3_RX                    RTE_USART3_RX_DEF
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_DEF
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_DEF
+#define RTE_USART3_CK                    RTE_USART3_CK_DEF
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_DEF
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_DEF
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_RX_DMA               0
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_CHANNEL       3
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_TX_DMA               0
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_CHANNEL       2
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> UART4 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
+#define RTE_UART4                       0
+#define RTE_UART4_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART4_TX Pin <0=>Not Used <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX                    0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX                    1
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//   <o> UART4_RX Pin <0=>Not Used <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX                    0
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX                    1
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_RX_DMA                0
+#define RTE_UART4_RX_DMA_NUMBER         2
+#define RTE_UART4_RX_DMA_CHANNEL        3
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_TX_DMA                0
+#define RTE_UART4_TX_DMA_NUMBER         2
+#define RTE_UART4_TX_DMA_CHANNEL        5
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// </e>
+
+
+// <e> UART5 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
+#define RTE_UART5                       0
+#define RTE_UART5_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART5_TX Pin <0=>Not Used <1=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX                    0
+#elif  (RTE_UART5_TX_ID == 1)
+#define RTE_UART5_TX                    1
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//   <o> UART5_RX Pin <0=>Not Used <1=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX                    0
+#elif  (RTE_UART5_RX_ID == 1)
+#define RTE_UART5_RX                    1
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+// </e>
+
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1)
+// <i> Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
+#define RTE_I2C1                        0
+
+//   <o> I2C1_SCL Pin <0=>PB6
+#define RTE_I2C1_SCL_PORT_ID_DEF        0
+#if    (RTE_I2C1_SCL_PORT_ID_DEF == 0)
+#define RTE_I2C1_SCL_PORT_DEF           GPIOB
+#define RTE_I2C1_SCL_BIT_DEF            6
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB7
+#define RTE_I2C1_SDA_PORT_ID_DEF        0
+#if    (RTE_I2C1_SDA_PORT_ID_DEF == 0)
+#define RTE_I2C1_SDA_PORT_DEF           GPIOB
+#define RTE_I2C1_SDA_BIT_DEF            7
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <e> I2C1 Pin Remap
+//   <i> Enable I2C1 Pin Remapping
+#define RTE_I2C1_REMAP_FULL             0
+
+//   <o> I2C1_SCL Pin <0=>PB8
+#define RTE_I2C1_SCL_PORT_ID_FULL       0
+#if    (RTE_I2C1_SCL_PORT_ID_FULL == 0)
+#define RTE_I2C1_SCL_PORT_FULL          GPIOB
+#define RTE_I2C1_SCL_BIT_FULL           8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB9
+#define RTE_I2C1_SDA_PORT_ID_FULL       0
+#if    (RTE_I2C1_SDA_PORT_ID_FULL == 0)
+#define RTE_I2C1_SDA_PORT_FULL          GPIOB
+#define RTE_I2C1_SDA_BIT_FULL           9
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_I2C1_REMAP_FULL)
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_FULL
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_FULL
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_FULL
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_FULL
+#else
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_NO_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_DEF
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_DEF
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_DEF
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_DEF
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_RX_DMA                 0
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_CHANNEL         7
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_TX_DMA                 0
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_CHANNEL         6
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> I2C2 (Inter-integrated Circuit Interface 2)
+// <i> Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
+#define RTE_I2C2                        0
+#define RTE_I2C2_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> I2C2_SCL Pin <0=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C2_SDA Pin <0=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_CHANNEL         5
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_CHANNEL         4
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
+#define RTE_SPI1                        0
+
+//   <e> SPI1_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//   <o> SPI1_SCK Pin <0=>PA5
+#define RTE_SPI1_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI1_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI1_SCK_PORT_DEF           GPIOA
+#define RTE_SPI1_SCK_BIT_DEF            5
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PA6
+#define RTE_SPI1_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI1_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI1_MISO_DEF               0
+#elif   (RTE_SPI1_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI1_MISO_DEF               1
+#define RTE_SPI1_MISO_PORT_DEF          GPIOA
+#define RTE_SPI1_MISO_BIT_DEF           6
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PA7
+#define RTE_SPI1_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI1_MOSI_DEF               0
+#elif  (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI1_MOSI_DEF               1
+#define RTE_SPI1_MOSI_PORT_DEF          GPIOA
+#define RTE_SPI1_MOSI_BIT_DEF           7
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <e> SPI1 Pin Remap
+//   <i> Enable SPI1 Pin Remapping.
+#define RTE_SPI1_REMAP                  0
+
+//   <o> SPI1_SCK Pin <0=>PB3
+#define RTE_SPI1_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI1_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI1_SCK_PORT_FULL          GPIOB
+#define RTE_SPI1_SCK_BIT_FULL           3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI1_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI1_MISO_FULL              0
+#elif  (RTE_SPI1_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI1_MISO_FULL              1
+#define RTE_SPI1_MISO_PORT_FULL         GPIOB
+#define RTE_SPI1_MISO_BIT_FULL          4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI1_MOSI_FULL              0
+#elif  (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI1_MOSI_FULL              1
+#define RTE_SPI1_MOSI_PORT_FULL         GPIOB
+#define RTE_SPI1_MOSI_BIT_FULL          5
+#else
+#error "Invalid SPI1_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI1_REMAP)
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_FULL
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_FULL
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_FULL
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_FULL
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_FULL
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_FULL
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_FULL
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_FULL
+#else 
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_NO_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_DEF
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_DEF
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_DEF
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_DEF
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_DEF
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_DEF
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_DEF
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_RX_DMA                 0
+#define RTE_SPI1_RX_DMA_NUMBER          1
+#define RTE_SPI1_RX_DMA_CHANNEL         2
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_TX_DMA                 0
+#define RTE_SPI1_TX_DMA_NUMBER          1
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+// <i> Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
+#define RTE_SPI2                        0
+
+//   <e> SPI2_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//   <o> SPI2_SCK Pin <0=>PB13
+#define RTE_SPI2_SCK_PORT_ID            0
+#if    (RTE_SPI2_SCK_PORT_ID == 0)
+#define RTE_SPI2_SCK_PORT               GPIOB
+#define RTE_SPI2_SCK_BIT                13
+#define RTE_SPI2_SCK_REMAP              0
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI2_MISO Pin <0=>Not Used <1=>PB14
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO                   0
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO                   1
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#define RTE_SPI2_MISO_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI2_MOSI Pin <0=>Not Used <1=>PB15
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI                   0
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI                   1
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#define RTE_SPI2_MOSI_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_RX_DMA                 0
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_CHANNEL         4
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_TX_DMA                 0
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_CHANNEL         5
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+// <i> Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
+#define RTE_SPI3                        0
+
+//   <e> SPI3_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//   <o> SPI3_SCK Pin <0=>PB3
+#define RTE_SPI3_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI3_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI3_SCK_PORT_DEF           GPIOB
+#define RTE_SPI3_SCK_BIT_DEF            3
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI3_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI3_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI3_MISO_DEF               0
+#elif  (RTE_SPI3_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI3_MISO_DEF               1
+#define RTE_SPI3_MISO_PORT_DEF          GPIOB
+#define RTE_SPI3_MISO_BIT_DEF           4
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI3_MOSI <0=>Not Used Pin <1=>PB5
+#define RTE_SPI3_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI3_MOSI_DEF               0
+#elif  (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI3_MOSI_DEF               1
+#define RTE_SPI3_MOSI_PORT_DEF          GPIOB
+#define RTE_SPI3_MOSI_BIT_DEF           5
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   <e> SPI3 Pin Remap
+//   <i> Enable SPI3 Pin Remapping.
+//   <i> SPI 3 Pin Remapping is available only in connectivity line devices!
+#define RTE_SPI3_REMAP                  0
+
+//   <o> SPI3_SCK Pin <0=>PC10
+#define RTE_SPI3_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI3_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI3_SCK_PORT_FULL          GPIOC
+#define RTE_SPI3_SCK_BIT_FULL           10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI3_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI3_MISO_FULL              0
+#elif  (RTE_SPI3_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI3_MISO_FULL              1
+#define RTE_SPI3_MISO_PORT_FULL         GPIOC
+#define RTE_SPI3_MISO_BIT_FULL          11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+//   <o> SPI3_MOSI Pin <0=>Not Used <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI3_MOSI_FULL              0
+#elif  (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI3_MOSI_FULL              1
+#define RTE_SPI3_MOSI_PORT_FULL         GPIOC
+#define RTE_SPI3_MOSI_BIT_FULL          12
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI3_REMAP)
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_FULL
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_FULL
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_FULL
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_FULL
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_FULL
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_FULL
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_FULL
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_FULL
+#else 
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_NO_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_DEF
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_DEF
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_DEF
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_DEF
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_DEF
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_DEF
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_DEF
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <1=>1
+//     <i>  Selects DMA Channel (only Channel 1 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_RX_DMA                 0
+#define RTE_SPI3_RX_DMA_NUMBER          2
+#define RTE_SPI3_RX_DMA_CHANNEL         1
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_TX_DMA                 0
+#define RTE_SPI3_TX_DMA_NUMBER          2
+#define RTE_SPI3_TX_DMA_CHANNEL         2
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SDIO (Secure Digital Input/Output) [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
+#define RTE_SDIO                        0
+
+//   <h> SDIO Peripheral Bus
+//     <o> SDIO_CK Pin <0=>PC12
+#define   RTE_SDIO_CK_PORT_ID           0
+#if      (RTE_SDIO_CK_PORT_ID == 0)
+  #define RTE_SDIO_CK_PORT              GPIOC
+  #define RTE_SDIO_CK_PIN               12
+#else
+  #error "Invalid SDIO_CLK Pin Configuration!"
+#endif
+//     <o> SDIO_CMD Pin <0=>PD2
+#define   RTE_SDIO_CMD_PORT_ID          0
+#if      (RTE_SDIO_CMD_PORT_ID == 0)
+  #define RTE_SDIO_CMD_PORT             GPIOD
+  #define RTE_SDIO_CMD_PIN              2
+#else
+  #error "Invalid SDIO_CMD Pin Configuration!"
+#endif
+//     <o> SDIO_D0 Pin <0=>PC8
+#define   RTE_SDIO_D0_PORT_ID           0
+#if      (RTE_SDIO_D0_PORT_ID == 0)
+  #define RTE_SDIO_D0_PORT              GPIOC
+  #define RTE_SDIO_D0_PIN               8
+#else
+  #error "Invalid SDIO_DAT0 Pin Configuration!"
+#endif
+//     <e> SDIO_D[1 .. 3]
+#define   RTE_SDIO_BUS_WIDTH_4          1
+//       <o> SDIO_D1 Pin <0=>PC9
+#define   RTE_SDIO_D1_PORT_ID           0
+#if      (RTE_SDIO_D1_PORT_ID == 0)
+  #define RTE_SDIO_D1_PORT              GPIOC
+  #define RTE_SDIO_D1_PIN               9
+#else
+  #error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//       <o> SDIO_D2 Pin <0=>PC10
+#define   RTE_SDIO_D2_PORT_ID           0
+#if      (RTE_SDIO_D2_PORT_ID == 0)
+  #define RTE_SDIO_D2_PORT              GPIOC
+  #define RTE_SDIO_D2_PIN               10
+#else
+  #error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//       <o> SDIO_D3 Pin <0=>PC11
+#define   RTE_SDIO_D3_PORT_ID           0
+#if      (RTE_SDIO_D3_PORT_ID == 0)
+  #define RTE_SDIO_D3_PORT              GPIOC
+  #define RTE_SDIO_D3_PIN               11
+#else
+  #error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//     </e> SDIO_D[1 .. 3]
+//     <e> SDIO_D[4 .. 7]
+#define   RTE_SDIO_BUS_WIDTH_8          0
+//       <o> SDIO_D4 Pin <0=>PB8
+#define   RTE_SDIO_D4_PORT_ID           0
+#if      (RTE_SDIO_D4_PORT_ID == 0)
+  #define RTE_SDIO_D4_PORT              GPIOB
+  #define RTE_SDIO_D4_PIN               8
+#else
+  #error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//       <o> SDIO_D5 Pin <0=>PB9
+#define   RTE_SDIO_D5_PORT_ID           0
+#if      (RTE_SDIO_D5_PORT_ID == 0)
+  #define RTE_SDIO_D5_PORT              GPIOB
+  #define RTE_SDIO_D5_PIN               9
+#else
+  #error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//       <o> SDIO_D6 Pin <0=>PC6
+#define   RTE_SDIO_D6_PORT_ID           0
+#if      (RTE_SDIO_D6_PORT_ID == 0)
+  #define RTE_SDIO_D6_PORT              GPIOC
+  #define RTE_SDIO_D6_PIN               6
+#else
+  #error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//       <o> SDIO_D7 Pin <0=>PC7
+#define   RTE_SDIO_D7_PORT_ID           0
+#if      (RTE_SDIO_D7_PORT_ID == 0)
+  #define RTE_SDIO_D7_PORT              GPIOC
+  #define RTE_SDIO_D7_PIN               7
+#else
+  #error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//     </e> SDIO_D[4 .. 7]
+//   </h> SDIO Peripheral Bus
+
+//   <e> Card Detect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_CD_EN                  1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(5)
+#define RTE_SDIO_CD_PIN                 11
+
+//   <e> Write Protect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_WP_EN                  0
+#define RTE_SDIO_WP_ACTIVE              1
+#define RTE_SDIO_WP_PORT                GPIO_PORT(0)
+#define RTE_SDIO_WP_PIN                 10
+
+//   <h> DMA
+//     <o0> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o1> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o2> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </h>
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// </e>
+
+
+// <e> CAN1 (Controller Area Network 1) [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
+#define RTE_CAN1                        0
+
+//   <o> CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
+#define RTE_CAN1_RX_PORT_ID             0
+#if    (RTE_CAN1_RX_PORT_ID == 0)
+#define RTE_CAN1_RX_PORT                GPIOA
+#define RTE_CAN1_RX_BIT                 11
+#elif  (RTE_CAN1_RX_PORT_ID == 1)
+#define RTE_CAN1_RX_PORT                GPIOB
+#define RTE_CAN1_RX_BIT                 8
+#elif  (RTE_CAN1_RX_PORT_ID == 2)
+#define RTE_CAN1_RX_PORT                GPIOD
+#define RTE_CAN1_RX_BIT                 0
+#else
+#error "Invalid CAN1_RX Pin Configuration!"
+#endif
+
+//   <o> CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
+#define RTE_CAN1_TX_PORT_ID             0
+#if    (RTE_CAN1_TX_PORT_ID == 0)
+#define RTE_CAN1_TX_PORT                GPIOA
+#define RTE_CAN1_TX_BIT                 12
+#elif  (RTE_CAN1_TX_PORT_ID == 1)
+#define RTE_CAN1_TX_PORT                GPIOB
+#define RTE_CAN1_TX_BIT                 9
+#elif  (RTE_CAN1_TX_PORT_ID == 2)
+#define RTE_CAN1_TX_PORT                GPIOD
+#define RTE_CAN1_TX_BIT                 1
+#else
+#error "Invalid CAN1_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> CAN2 (Controller Area Network 2) [Driver_CAN2]
+// <i> Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
+#define RTE_CAN2                        0
+
+//   <o> CAN2_RX Pin <0=>PB5 <1=>PB12
+#define RTE_CAN2_RX_PORT_ID             0
+#if    (RTE_CAN2_RX_PORT_ID == 0)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 5
+#elif  (RTE_CAN2_RX_PORT_ID == 1)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 12
+#else
+#error "Invalid CAN2_RX Pin Configuration!"
+#endif
+
+//   <o> CAN2_TX Pin <0=>PB6 <1=>PB13
+#define RTE_CAN2_TX_PORT_ID             0
+#if    (RTE_CAN2_TX_PORT_ID == 0)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 6
+#elif  (RTE_CAN2_TX_PORT_ID == 1)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 13
+#else
+#error "Invalid CAN2_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> ETH (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
+#define RTE_ETH                         0
+
+//   <e> MII (Media Independent Interface)
+//   <i> Enable Media Independent Interface pin configuration
+#define RTE_ETH_MII                     0
+
+//     <o> ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD0 Pin <0=>PB12
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD1 Pin <0=>PB13
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD3 Pin <0=>PB8
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TX_EN Pin <0=>PB11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_DEF            0
+
+//     <o> ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_DEF            0
+
+//     <o> ETH_MII_RXD2 Pin <0=>PB0
+#define RTE_ETH_MII_RXD2_DEF            0
+
+//     <o> ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
+#define RTE_ETH_MII_RXD3_DEF            0
+
+//     <o> ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_DEF           0
+
+//     <o> ETH_MII_RX_ER Pin <0=>PB10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//     <o> ETH_MII_CRS Pin <0=>PA0
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//     <o> ETH_MII_COL Pin <0=>PA3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//     <e> Ethernet MAC I/O remapping
+//     <i> Remap Ethernet pins
+#define RTE_ETH_MII_REMAP               0
+
+//     <o> ETH_MII_RXD0 Pin <1=>PD9
+#define RTE_ETH_MII_RXD0_REMAP          1
+
+//     <o> ETH_MII_RXD1 Pin <1=>PD10
+#define RTE_ETH_MII_RXD1_REMAP          1
+
+//     <o> ETH_MII_RXD2 Pin <1=>PD11
+#define RTE_ETH_MII_RXD2_REMAP          1
+
+//       <o> ETH_MII_RXD3 Pin <1=>PD12
+#define RTE_ETH_MII_RXD3_REMAP          1
+
+//       <o> ETH_MII_RX_DV Pin <1=>PD8
+#define RTE_ETH_MII_RX_DV_REMAP         1
+//     </e>
+
+//   </e>
+
+#if    ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#elif  ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
+#define RTE_ETH_MII_RXD0_PORT           GPIOD
+#define RTE_ETH_MII_RXD0_PIN            9
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
+#define RTE_ETH_MII_RXD1_PORT           GPIOD
+#define RTE_ETH_MII_RXD1_PIN            10
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
+#define RTE_ETH_MII_RXD2_PORT           GPIOD
+#define RTE_ETH_MII_RXD2_PIN            11
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
+#define RTE_ETH_MII_RXD3_PORT           GPIOD
+#define RTE_ETH_MII_RXD3_PIN            12
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOD
+#define RTE_ETH_MII_RX_DV_PIN           8
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    0
+
+//     <o> ETH_RMII_TXD0 Pin <0=>PB12
+#define RTE_ETH_RMII_TXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TXD1 Pin <0=>PB13
+#define RTE_ETH_RMII_TXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TX_EN Pin <0=>PB11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      0
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_DEF           0
+
+//     <o> ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_DEF           0
+
+//     <o> ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//     <o> ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_DEF     0
+
+//   <e> Ethernet MAC I/O remapping
+//   <i> Remap Ethernet pins
+#define RTE_ETH_RMII_REMAP              0
+//     <o> ETH_RMII_RXD0 Pin <1=>PD9
+#define RTE_ETH_RMII_RXD0_REMAP         1
+
+//     <o> ETH_RMII_RXD1 Pin <1=>PD10
+#define RTE_ETH_RMII_RXD1_REMAP         1
+
+//     <o> ETH_RMII_CRS_DV Pin <1=>PD8
+#define RTE_ETH_RMII_CRS_DV_REMAP       1
+//   </e>
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOD
+#define RTE_ETH_RMII_RXD0_PIN           9
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOD
+#define RTE_ETH_RMII_RXD1_PIN           10
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOD
+#define RTE_ETH_RMII_CRS_DV_PIN         8
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   </e>
+
+//   <h> Management Data Interface
+//     <o> ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//     <o> ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   </h>
+
+//   <o> Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
+#define RTE_ETH_REF_CLOCK_ID            0
+#if    (RTE_ETH_REF_CLOCK_ID == 0)
+#define RTE_ETH_REF_CLOCK               0
+#elif  (RTE_ETH_REF_CLOCK_ID == 1)
+#define RTE_ETH_REF_CLOCK               1
+#else
+#error "Invalid MCO Ethernet Reference Clock Configuration!"
+#endif
+// </e>
+
+
+// <e> USB Device Full-speed
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_DEVICE                  0
+
+//     <e> CON On/Off Pin
+//     <i> Configure Pin for driving D+ pull-up
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_USB_DEVICE_CON_PIN          1
+#define RTE_USB_DEVICE_CON_ACTIVE       0
+#define RTE_USB_DEVICE_CON_PORT         GPIO_PORT(1)
+#define RTE_USB_DEVICE_CON_BIT          14
+
+//   </e>
+
+
+// <e> USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//   <e> Host [Driver_USBH0]
+//   <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             0
+
+//     <e> VBUS Power On/Off Pin
+//     <i> Configure Pin for driving VBUS
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_FS_VBUS_BIT             9
+
+//     <e> Overcurrent Detection Pin
+//     <i> Configure Pin for overcurrent detection
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(4)
+#define RTE_OTG_FS_OC_BIT               1
+//   </e>
+
+// </e>
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/steper/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/steper/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
new file mode 100644
index 0000000..74da96c
--- /dev/null
+++ b/steper/stm32/RTE/Device/STM32F103RB/startup_stm32f10x_md.s
@@ -0,0 +1,307 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
+;*                      toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/steper/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h b/steper/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h
new file mode 100644
index 0000000..e49e560
--- /dev/null
+++ b/steper/stm32/RTE/Device/STM32F103RB/stm32f10x_conf.h
@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Run Time Environment will set specific #define for each selected module below */
+#include "RTE_Components.h"
+
+#ifdef RTE_DEVICE_STDPERIPH_ADC
+#include "stm32f10x_adc.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_BKP
+#include "stm32f10x_bkp.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_CAN
+#include "stm32f10x_can.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_CEC
+#include "stm32f10x_cec.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_CRC
+#include "stm32f10x_crc.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_DAC
+#include "stm32f10x_dac.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_DBGMCU
+#include "stm32f10x_dbgmcu.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_DMA
+#include "stm32f10x_dma.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_EXTI
+#include "stm32f10x_exti.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_FLASH
+#include "stm32f10x_flash.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_FSMC
+#include "stm32f10x_fsmc.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_GPIO
+#include "stm32f10x_gpio.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_I2C
+#include "stm32f10x_i2c.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_IWDG
+#include "stm32f10x_iwdg.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_PWR
+#include "stm32f10x_pwr.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_RCC
+#include "stm32f10x_rcc.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_RTC
+#include "stm32f10x_rtc.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_SDIO
+#include "stm32f10x_sdio.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_SPI
+#include "stm32f10x_spi.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_TIM
+#include "stm32f10x_tim.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_USART
+#include "stm32f10x_usart.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_WWDG
+#include "stm32f10x_wwdg.h"
+#endif
+#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/steper/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c b/steper/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c
new file mode 100644
index 0000000..71efc85
--- /dev/null
+++ b/steper/stm32/RTE/Device/STM32F103RB/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/steper/stm32/RTE/_Target_1/RTE_Components.h b/steper/stm32/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 0000000..87aafdd
--- /dev/null
+++ b/steper/stm32/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'MG955' 
+ * Target:  'Target 1' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32f10x.h"
+
+/*  Keil::Device:StdPeriph Drivers:Framework:3.5.1 */
+#define RTE_DEVICE_STDPERIPH_FRAMEWORK
+/*  Keil::Device:StdPeriph Drivers:GPIO:3.5.0 */
+#define RTE_DEVICE_STDPERIPH_GPIO
+/*  Keil::Device:StdPeriph Drivers:RCC:3.5.0 */
+#define RTE_DEVICE_STDPERIPH_RCC
+/*  Keil::Device:StdPeriph Drivers:TIM:3.5.0 */
+#define RTE_DEVICE_STDPERIPH_TIM
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/steper/stm32/main.c b/steper/stm32/main.c
new file mode 100644
index 0000000..8cd88d4
--- /dev/null
+++ b/steper/stm32/main.c
@@ -0,0 +1,259 @@
+/**
+  ******************************************************************************
+  * @file TIM/7PWM_Output/main.c 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   Main program body
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup TIM_7PWM_Output
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+TIM_OCInitTypeDef  TIM_OCInitStructure;
+uint16_t CCR1_Val = 2500;
+uint16_t CCR2_Val = 2500;
+uint16_t CCR3_Val = 2500;
+uint16_t CCR4_Val = 2500;
+
+int down = 1;
+void sleep1sec(void){
+	uint16_t x = 600;
+	for(;x > 0;x--){
+		uint16_t y = 500;
+		for(;y > 0;y--){
+			
+		}
+	}
+}
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* GPIO Configuration */
+  GPIO_Configuration();
+
+  /* TIM1 Configuration ---------------------------------------------------
+   Generates 7 PWM signals with 4 different duty cycles:
+   TIM1CLK = 72 MHz, Prescaler = 0, TIM1 counter clock = 72 MHz
+   TIM1 frequency = TIM1CLK/(TIM1_Period + 1) = 17.57 KHz
+  - TIM1 Channel1 & Channel1N duty cycle = TIM1->CCR1 / (TIM1_Period + 1) = 50% 
+  - TIM1 Channel2 & Channel2N duty cycle = TIM1->CCR2 / (TIM1_Period + 1) = 37.5% 
+  - TIM1 Channel3 & Channel3N duty cycle = TIM1->CCR3 / (TIM1_Period + 1) = 25%
+  - TIM1 Channel4 duty cycle = TIM1->CCR4 / (TIM1_Period + 1) = 12.5% 
+  ----------------------------------------------------------------------- */
+
+  /* Time Base configuration */
+  TIM_TimeBaseStructure.TIM_Prescaler = 72; // 1mhz
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseStructure.TIM_Period = 20000;
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+  TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
+
+  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
+
+  /* Channel 1, 2,3 and 4 Configuration in PWM mode */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
+  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
+
+  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
+
+  TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
+  TIM_OC2Init(TIM1, &TIM_OCInitStructure);
+
+  TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
+  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
+
+  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
+  TIM_OC4Init(TIM1, &TIM_OCInitStructure);
+
+  /* TIM1 counter enable */
+  TIM_Cmd(TIM1, ENABLE);
+
+  /* TIM1 Main Output Enable */
+  TIM_CtrlPWMOutputs(TIM1, ENABLE);
+
+  while (1)
+  {
+			sleep1sec();
+			if(1 == down){
+					CCR1_Val-=40;
+					CCR2_Val-=40;
+					CCR3_Val-=40;
+					CCR4_Val-=40;
+					/* Channel 1, 2,3 and 4 Configuration in PWM mode */
+					TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
+					TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+					TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+					TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
+					TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+					TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
+					TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+					TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
+
+					TIM_OC1Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
+					TIM_OC2Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
+					TIM_OC3Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
+					TIM_OC4Init(TIM1, &TIM_OCInitStructure);
+					if(CCR3_Val < 500)
+						down = 2;
+			}
+			else{
+					CCR1_Val+=40;
+					CCR2_Val+=40;
+					CCR3_Val+=40;
+					CCR4_Val+=40;
+					/* Channel 1, 2,3 and 4 Configuration in PWM mode */
+					TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
+					TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+					TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+					TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
+					TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+					TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
+					TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+					TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
+
+					TIM_OC1Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
+					TIM_OC2Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
+					TIM_OC3Init(TIM1, &TIM_OCInitStructure);
+
+					TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
+					TIM_OC4Init(TIM1, &TIM_OCInitStructure);
+					if(CCR3_Val > 2500)
+						down = 1;
+			
+			}
+	}
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* Setup the microcontroller system. Initialize the Embedded Flash Interface,  
+     initialize the PLL and update the SystemFrequency variable. */
+  SystemInit();
+
+  /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
+                         RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
+}
+
+/**
+  * @brief  Configure the TIM1 Pins.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#ifdef STM32F10X_CL
+  /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N and 4 as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|GPIO_Pin_14|
+                                GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  /* TIM1 Full remapping pins */
+  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); 
+
+#else
+  /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *   where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {}
+}
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/steper/stm32/readme.txt b/steper/stm32/readme.txt
new file mode 100644
index 0000000..9e38dd1
--- /dev/null
+++ b/steper/stm32/readme.txt
@@ -0,0 +1,121 @@
+/**
+  @page TIM_7PWM_Output TIM_7PWM_Output
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2009 STMicroelectronics *******************
+  * @file    TIM/7PWM_Output/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   Description of the TIM 7PWM_Output example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example shows how to configure the TIM1 peripheral to generate 7 PWM signals 
+with 4 different duty cycles.
+
+TIM1CLK is fixed to 72 MHz, the TIM1 Prescaler is equal to 0 so the TIM1 counter
+clock used is 72 MHz.
+
+TIM1 frequency is defined as follow:
+TIM1 frequency = TIM1CLK/(TIM1_Period + 1) = 17.57 KHz.
+
+The TIM1 CCR1 register value is equal to 0x7FF, so the TIM1 Channel 1 and TIM1 
+Channel 1N generate a PWM signal with a frequency equal to 17.57 KHz 
+and a duty cycle equal to:
+TIM1 Channel1 duty cycle = TIM1_CCR1 /( TIM1_Period + 1) = 50%.
+
+The TIM1 CCR2 register value is equal to 0x5FF, so the TIM1 Channel 2 and TIM1
+Channel 2N generate a PWM signal with a frequency equal to 17.57 KHz 
+and a duty cycle equal to:
+TIM1 Channel2 duty cycle = TIM1_CCR2 / ( TIM1_Period + 1)= 37.5%.
+
+The TIM1 CCR3 register value is equal to 0x3FF, so the TIM1 Channel 3 and TIM1 
+Channel 3N generate a PWM signal with a frequency equal to 17.57 KHz 
+and a duty cycle equal to:
+TIM1 Channel3 duty cycle = TIM1_CCR3 / ( TIM1_Period + 1) = 25%.
+
+The TIM1 CCR4 register value is equal to 0x1FF, so the TIM1 Channel 4 
+generate a PWM signal with a frequency equal to 17.57 KHz 
+and a duty cycle equal to:
+TIM1 Channel4 duty cycle = TIM1_CCR4 / ( TIM1_Period + 1) = 12.5%.
+
+The TIM1 waveform can be displayed using an oscilloscope.
+
+@par Directory contents 
+
+  - TIM/7PWM_Output/stm32f10x_conf.h  Library Configuration file
+  - TIM/7PWM_Output/stm32f10x_it.c    Interrupt handlers
+  - TIM/7PWM_Output/stm32f10x_it.h    Interrupt handlers header file
+  - TIM/7PWM_Output/main.c            Main program
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density 
+    and Low-Density Devices.
+  
+  - This example has been tested with STMicroelectronics STM3210C-EVAL (STM32F10x 
+    Connectivity line), STM3210E-EVAL (STM32F10x High-Density) and STM3210B-EVAL
+    (STM32F10x Medium-Density) evaluation boards and can be easily tailored to
+    any other supported device and development board.
+    
+
+  - STM3210C-EVAL Set-up 
+    - Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
+      - TIM1_CH1  pin (PE.08)  
+      - TIM1_CH1N pin (PE.09)  
+      - TIM1_CH2  pin (PE.10)  
+      - TIM1_CH2N pin (PE.11)  
+      - TIM1_CH3  pin (PE.12)  
+      - TIM1_CH3N pin (PE.13)
+      - TIM1_CH4  pin (PE.14)      
+
+  - STM3210E-EVAL and STM3210B-EVAL Set-up 
+    - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
+      - TIM1_CH1  pin (PA.08)  
+      - TIM1_CH1N pin (PB.13)  
+      - TIM1_CH2  pin (PA.09)  
+      - TIM1_CH2N pin (PB.14)  
+      - TIM1_CH3  pin (PA.10)  
+      - TIM1_CH3N pin (PB.15)
+      - TIM1_CH4  pin (PA.11)    
+  
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+- Create a project and setup all project configuration
+- Add the required Library files:
+  - stm32f10x_gpio.c
+  - stm32f10x_rcc.c  
+  - stm32f10x_tim.c  
+  - system_stm32f10x.c (under Libraries\CMSIS\Core\CM3)
+      
+- Edit stm32f10x.h file to select the device you are working on.
+  
+@b Tip: You can tailor the provided project template to run this example, for 
+        more details please refer to "stm32f10x_stdperiph_lib_um.chm" user 
+        manual; select "Peripheral Examples" then follow the instructions 
+        provided in "How to proceed" section.   
+- Link all compiled files and load your image into target memory
+- Run the example
+
+@note
+ - Low-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 32 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h3>
+ */
diff --git a/steper/stm32/stm32f10x_conf.h b/steper/stm32/stm32f10x_conf.h
new file mode 100644
index 0000000..e2e1456
--- /dev/null
+++ b/steper/stm32/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file TIM/7PWM_Output/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+/* #include "stm32f10x_adc.h" */
+/* #include "stm32f10x_bkp.h" */
+/* #include "stm32f10x_can.h" */
+/* #include "stm32f10x_crc.h" */
+/* #include "stm32f10x_dac.h" */
+/* #include "stm32f10x_dbgmcu.h" */
+/* #include "stm32f10x_dma.h" */
+/* #include "stm32f10x_exti.h" */
+/* #include "stm32f10x_flash.h" */
+/* #include "stm32f10x_fsmc.h" */
+#include "stm32f10x_gpio.h" 
+/* #include "stm32f10x_i2c.h" */
+/* #include "stm32f10x_iwdg.h" */
+/* #include "stm32f10x_pwr.h" */
+#include "stm32f10x_rcc.h" 
+/* #include "stm32f10x_rtc.h" */
+/* #include "stm32f10x_sdio.h" */
+/* #include "stm32f10x_spi.h" */
+#include "stm32f10x_tim.h"
+/* #include "stm32f10x_usart.h" */
+/* #include "stm32f10x_wwdg.h" */
+/* #include "misc.h" */ /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/steper/stm32/stm32f10x_it.c b/steper/stm32/stm32f10x_it.c
new file mode 100644
index 0000000..0d7253f
--- /dev/null
+++ b/steper/stm32/stm32f10x_it.c
@@ -0,0 +1,157 @@
+/**
+  ******************************************************************************
+  * @file    TIM/7PWM_Output/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup TIM_7PWM_Output
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/steper/stm32/stm32f10x_it.h b/steper/stm32/stm32f10x_it.h
new file mode 100644
index 0000000..ed4ed62
--- /dev/null
+++ b/steper/stm32/stm32f10x_it.h
@@ -0,0 +1,45 @@
+/**
+  ******************************************************************************
+  * @file TIM/7PWM_Output/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+					 
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/