添加OLED驱动程序
parent
59a4861c87
commit
ee719804d2
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<?xml version="1.0" encoding="utf-8"?>
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<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
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<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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<events>
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</events>
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</component_viewer>
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Load Diff
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Load Diff
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Load Diff
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@ -0,0 +1,790 @@
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[Version]
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||||
Nu_LinkVersion=V5.4
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||||
[Process]
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||||
ProcessID=0x00008ea4
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||||
ProcessCreationTime_L=0x521d9361
|
||||
ProcessCreationTime_H=0x01d4dc63
|
||||
NuLinkID=0x18000c06
|
||||
NuLinkIDs_Count=0x00000001
|
||||
NuLinkID0=0x18000c06
|
||||
[ChipSelect]
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||||
;ChipName=<NUC1xx|NUC2xx|M05x|N571|N572|Nano100|N512|Mini51|NUC505|General>
|
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ChipName=M451
|
||||
[NUC505]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NUC505_SPIFLASH.FLM
|
||||
[NUC4xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NUC400_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x014fb180
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[NUC2xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NUC200_AP_128.FLM
|
||||
[NUC126]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
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||||
ProgramAlgorithm=NUC126_AP_256.FLM
|
||||
[NUC121]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NUC121_AP_32.FLM
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||||
[NUC1xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
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||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NUC100_AP_128.FLM
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||||
[NUC029]
|
||||
Connect=0
|
||||
Reset=Autodetect
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||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x800
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||||
ProgramAlgorithm=NUC029_AP_16.FLM
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||||
[NM1820]
|
||||
Connect=0
|
||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
|
||||
IOVoltage=3300
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||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=1
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||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x800
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||||
ProgramAlgorithm=NM1820_AP_17_5.FLM
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||||
[NM1810]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
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||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x800
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||||
ProgramAlgorithm=NM1810_AP_29_5.FLM
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||||
[NM1500]
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||||
Connect=0
|
||||
Reset=Autodetect
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||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NM1500_AP_128.FLM
|
||||
[NM1330]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NM1330_AP_64.FLM
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||||
[NM1320]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NM1320_AP_32.FLM
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||||
[NM1230]
|
||||
Connect=0
|
||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
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||||
IOVoltage=3300
|
||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=1
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||||
EnableLog=0
|
||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=NM1230_AP_64.FLM
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||||
[NM1200]
|
||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
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||||
IOVoltage=3300
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||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=1
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||||
EnableLog=0
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||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x800
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||||
ProgramAlgorithm=NM1200_AP_8.FLM
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||||
[NM1120]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
|
||||
IOVoltage=3300
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||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=1
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||||
EnableLog=0
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||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x800
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||||
ProgramAlgorithm=NM1120_AP_29_5.FLM
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||||
[NDA102]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NDA102_AP_29_5.FLM
|
||||
[Nano103]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=Nano103_AP_64.FLM
|
||||
[Nano100]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=Nano100_AP_64.FLM
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||||
[N576]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
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||||
IOVoltage=3300
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||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
|
||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=0
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||||
EnableLog=0
|
||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=N576_AP_145.FLM
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||||
[N575]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=N575_AP_145.FLM
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||||
[N572]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
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||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x2000
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||||
ProgramAlgorithm=N572Fxxx.FLM
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||||
[N571]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
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||||
IOVoltage=3300
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=1
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||||
EnableLog=0
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||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x2000
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||||
ProgramAlgorithm=N571E000.FLM
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||||
[N570]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
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||||
IOVoltage=3300
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||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
|
||||
Verify=1
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||||
ResetAndRun=0
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||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
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||||
MemAccessWhileRun=0
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||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=N570_AP_64.FLM
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||||
[N569]
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||||
Connect=0
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||||
Reset=Autodetect
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||||
MaxClock=1MHz
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||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
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||||
Erase=1
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||||
Program=1
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||||
Verify=1
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||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
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||||
RAMForAlgorithmSize=0x1000
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||||
ProgramAlgorithm=N569_AP_64.FLM
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||||
[N512]
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||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N512_AP_64.FLM
|
||||
[Mini57]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=Mini57_AP_29_5.FLM
|
||||
[Mini51]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=Mini51_AP_16.FLM
|
||||
[M481]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M481_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x00b71b00
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||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[M480LD]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M480LD_AP_256.FLM
|
||||
[M451]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=12MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M451_AP_256.FLM
|
||||
[M251]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=M251_AP_192.FLM
|
||||
[M2351]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=1
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M2351_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x00b71b00
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[M0564]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=M0564_AP_256.FLM
|
||||
[M0519]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=M0519_AP_128.FLM
|
||||
[M0518]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=M0518_AP_64.FLM
|
||||
[M05x]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=M0516_AP_64.FLM
|
||||
[M031]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=M031_AP_128.FLM
|
||||
[NPCX]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NPCX_AP_512.FLM
|
||||
[I94000]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=I94000_AP_512.FLM
|
||||
[ISD9300]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9300_AP_145.FLM
|
||||
[I9200]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=I9200_AP_128.FLM
|
||||
[ISD9xxx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9100_AP_145.FLM
|
||||
[ISD9000]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9000_AP_64.FLM
|
||||
[AU9xxx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=AU9100_AP_145.FLM
|
||||
[General]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,290 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>oled</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>8</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>NULink\Nu_Link.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=105,177,312,398,0)(1008=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>Nu_Link</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0M451_AP_256 -FL040000 -FS00 -FP0($$Device:M451VG6AE$Flash\M451_AP_256.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<SystemViewers>
|
||||
<Entry>
|
||||
<Name>System Viewer\CLK</Name>
|
||||
<WinId>35903</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\GPIO</Name>
|
||||
<WinId>35902</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\I2C0</Name>
|
||||
<WinId>35901</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\I2C1</Name>
|
||||
<WinId>35905</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\SYS</Name>
|
||||
<WinId>35904</WinId>
|
||||
</Entry>
|
||||
<Entry>
|
||||
<Name>System Viewer\UART0</Name>
|
||||
<WinId>35900</WinId>
|
||||
</Entry>
|
||||
</SystemViewers>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\ssd1306.c</PathWithFileName>
|
||||
<FilenameWithoutPath>ssd1306.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\ssd1306.h</PathWithFileName>
|
||||
<FilenameWithoutPath>ssd1306.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\codetab.h</PathWithFileName>
|
||||
<FilenameWithoutPath>codetab.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,620 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>oled</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>M451VG6AE</Device>
|
||||
<Vendor>Nuvoton</Vendor>
|
||||
<PackID>Nuvoton.NuMicro_DFP.1.2.0</PackID>
|
||||
<PackURL>http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M451VG6AE$Flash\M451_AP_256.FLM))</FlashDriverDll>
|
||||
<DeviceId>8164</DeviceId>
|
||||
<RegisterFile>$$Device:M451VG6AE$Device\M451\Include\M451Series.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:M451VG6AE$SVD\Nuvoton\M451_v1.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>OLED</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments></TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>1</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<GroupOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<GroupArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<uGnu>2</uGnu>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>2</vShortEn>
|
||||
<vShortWch>2</vShortWch>
|
||||
<v6Lto>2</v6Lto>
|
||||
<v6WtE>2</v6WtE>
|
||||
<v6Rtti>2</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\OLED_TEST</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>2</interw>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<thumb>2</thumb>
|
||||
<SplitLS>2</SplitLS>
|
||||
<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<useXO>2</useXO>
|
||||
<uClangAs>2</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
</GroupArmAds>
|
||||
</GroupOption>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ssd1306.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\ssd1306.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ssd1306.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\ssd1306.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>codetab.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\codetab.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<packages>
|
||||
<filter>
|
||||
<targetInfos/>
|
||||
</filter>
|
||||
<package name="CMSIS-Driver" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="ARM" version="2.2.0">
|
||||
<targetInfos>
|
||||
<targetInfo name="oled" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0">
|
||||
<targetInfos>
|
||||
<targetInfo name="oled" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0">
|
||||
<targetInfos>
|
||||
<targetInfo name="oled" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0">
|
||||
<targetInfos>
|
||||
<targetInfo name="oled" versionMatchMode="fixed"/>
|
||||
</targetInfos>
|
||||
</package>
|
||||
</packages>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.1.1" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="CLK" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="GPIO" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="I2C" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="SC" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="SYS" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="UART" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="sourceC" name="Device\M451\Driver\retarget.c" version="3.01.001">
|
||||
<instance index="0" removed="1">RTE\Device\M451LD3AE\retarget.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="Compiler ARM" name="Device\M451\Source\ARM\startup_M451Series.s" version="3.01.001">
|
||||
<instance index="0" removed="1">RTE\Device\M451LD3AE\startup_M451Series.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\M451\Source\system_M451Series.c" version="3.01.001">
|
||||
<instance index="0" removed="1">RTE\Device\M451LD3AE\system_M451Series.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="sourceC" name="Device\M451\Driver\retarget.c" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M451VG6AE\retarget.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="Compiler ARM" name="Device\M451\Source\ARM\startup_M451Series.s" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M451VG6AE\startup_M451Series.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\M451\Source\system_M451Series.c" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M451VG6AE\system_M451Series.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="oled"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="Compiler ARM" name="Device\NUC100\Source\ARM\startup_NUC100Series.s" version="3.00.002">
|
||||
<instance index="0" removed="1">RTE\Device\NUC120LD3AN\startup_NUC100Series.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.00.002" condition="M0NuMicro NUC100 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\NUC100\Source\system_NUC100Series.c" version="3.00.002">
|
||||
<instance index="0" removed="1">RTE\Device\NUC120LD3AN\system_NUC100Series.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.00.002" condition="M0NuMicro NUC100 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos/>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,678 @@
|
|||
/**************************************************************************//**
|
||||
* @file retarget.c
|
||||
* @version V3.00
|
||||
* $Revision: 13 $
|
||||
* $Date: 15/08/11 10:26a $
|
||||
* @brief M451 Series Debug Port and Semihost Setting Source File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include "M451Series.h"
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
#else
|
||||
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
|
||||
#pragma import _printf_widthprec
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Global variables */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
#endif
|
||||
FILE __stdout;
|
||||
FILE __stdin;
|
||||
|
||||
enum { r0, r1, r2, r3, r12, lr, pc, psr};
|
||||
|
||||
/**
|
||||
* @brief Helper function to dump register while hard fault occurred
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*/
|
||||
static void stackDump(uint32_t stack[])
|
||||
{
|
||||
printf("r0 = 0x%x\n", stack[r0]);
|
||||
printf("r1 = 0x%x\n", stack[r1]);
|
||||
printf("r2 = 0x%x\n", stack[r2]);
|
||||
printf("r3 = 0x%x\n", stack[r3]);
|
||||
printf("r12 = 0x%x\n", stack[r12]);
|
||||
printf("lr = 0x%x\n", stack[lr]);
|
||||
printf("pc = 0x%x\n", stack[pc]);
|
||||
printf("psr = 0x%x\n", stack[psr]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hard fault handler
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product
|
||||
*/
|
||||
void Hard_Fault_Handler(uint32_t stack[])
|
||||
{
|
||||
printf("In Hard Fault Handler\n");
|
||||
|
||||
stackDump(stack);
|
||||
// Replace while(1) with chip reset if WDT is not enabled for end product
|
||||
while(1);
|
||||
//SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Routine to write a char */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
/* The static buffer is used to speed up the semihost */
|
||||
static char g_buf[16];
|
||||
static char g_buf_len = 0;
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void SH_End(void)
|
||||
{
|
||||
asm("MOVS R0,#1 \n" //; Set return value to 1
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
}
|
||||
|
||||
void SH_ICE(void)
|
||||
{
|
||||
asm("CMP R2,#0 \n"
|
||||
"BEQ SH_End \n"
|
||||
"STR R0,[R2] \n" //; Save the return value to *pn32Out_R0
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
|
||||
"B SH_ICE \n"
|
||||
"SH_HardFault: \n" //; Captured by HardFault
|
||||
"MOVS R0,#0 \n" //; Set return value to 0
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
|
||||
return 1; //; Return 1 when it is trap by ICE
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LR value and branch to Hard_Fault_Handler function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get LR value and branch to Hard_Fault_Handler function.
|
||||
*/
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MSP value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void HardFault_Handler_Ret(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void SP_Read_Ready(void)
|
||||
{
|
||||
asm("LDR R1, [R0, #24] \n" //; Get previous PC
|
||||
"LDRH R3, [R1] \n" //; Get instruction
|
||||
"LDR R2, [pc, #8] \n" //; The special BKPT instruction
|
||||
"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
|
||||
"BNE HardFault_Handler_Ret \n" //; Not BKPT
|
||||
"ADDS R1, #4 \n" //; Skip BKPT and next line
|
||||
"STR R1, [R0, #24] \n" //; Save previous PC
|
||||
"BX lr \n" //; Return
|
||||
"DCD 0xBEAB \n" //; BKPT instruction code
|
||||
"B HardFault_Handler_Ret \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void SP_is_PSP(void)
|
||||
{
|
||||
asm(
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler (void)
|
||||
{
|
||||
asm("MOV R0, lr \n"
|
||||
"LSLS R0, #29 \n" //; Check bit 2
|
||||
"BMI SP_is_PSP \n" //; previous stack is PSP
|
||||
"MRS R0, MSP \n" //; previous stack is MSP, read MSP
|
||||
"B SP_Read_Ready \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOV R0, LR
|
||||
LSLS R0, #29 //; Check bit 2
|
||||
BMI SP_is_PSP //; previous stack is PSP
|
||||
MRS R0, MSP //; previous stack is MSP, read MSP
|
||||
B SP_Read_Ready
|
||||
SP_is_PSP
|
||||
MRS R0, PSP //; Read PSP
|
||||
|
||||
SP_Read_Ready
|
||||
LDR R1, [R0, #24] //; Get previous PC
|
||||
LDRH R3, [R1] //; Get instruction
|
||||
LDR R2, =0xBEAB //; The special BKPT instruction
|
||||
CMP R3, R2 //; Test if the instruction at previous PC is BKPT
|
||||
BNE HardFault_Handler_Ret //; Not BKPT
|
||||
|
||||
ADDS R1, #4 //; Skip BKPT and next line
|
||||
STR R1, [R0, #24] //; Save previous PC
|
||||
|
||||
BX LR //; Return
|
||||
HardFault_Handler_Ret
|
||||
|
||||
/* TODO: Implement your own hard fault handler here. */
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP ;stack use PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP ; stack use MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR ; LR current value //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
|
||||
B .
|
||||
|
||||
ALIGN
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
BKPT 0xAB //; Wait ICE or HardFault
|
||||
//; ICE will step over BKPT directly
|
||||
//; HardFault will step BKPT and the next line
|
||||
B SH_ICE
|
||||
|
||||
SH_HardFault //; Captured by HardFault
|
||||
MOVS R0, #0 //; Set return value to 0
|
||||
BX lr //; Return
|
||||
|
||||
SH_ICE //; Captured by ICE
|
||||
//; Save return value
|
||||
CMP R2, #0
|
||||
BEQ SH_End
|
||||
STR R0, [R2] //; Save the return value to *pn32Out_R0
|
||||
|
||||
SH_End
|
||||
MOVS R0, #1 //; Set return value to 1
|
||||
BX lr //; Return
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function extracts the location of stack frame and passes it to Hard_Fault_Handler function as a pointer
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port
|
||||
*
|
||||
* @details Send a target char to UART debug port .
|
||||
*/
|
||||
#ifndef NONBLOCK_PRINTF
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
|
||||
DEBUG_PORT->DAT = ch;
|
||||
if(ch == '\n')
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
DEBUG_PORT->DAT = '\r';
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* Non-block implement of send char */
|
||||
#define BUF_SIZE 2048
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
static uint8_t u8Buf[BUF_SIZE] = {0};
|
||||
static int32_t i32Head = 0;
|
||||
static int32_t i32Tail = 0;
|
||||
int32_t i32Tmp;
|
||||
|
||||
/* Only flush the data in buffer to UART when ch == 0 */
|
||||
if(ch)
|
||||
{
|
||||
// Push char
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = ch;
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
|
||||
if(ch == '\n')
|
||||
{
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = '\r';
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(i32Tail == i32Head)
|
||||
return;
|
||||
}
|
||||
|
||||
// pop char
|
||||
do
|
||||
{
|
||||
i32Tmp = i32Tail + 1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) == 0)
|
||||
{
|
||||
DEBUG_PORT->DAT = u8Buf[i32Tail];
|
||||
i32Tail = i32Tmp;
|
||||
}
|
||||
else
|
||||
break; // FIFO full
|
||||
}while(i32Tail != i32Head);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port or semihost
|
||||
*
|
||||
* @details Send a target char to UART debug port or semihost.
|
||||
*/
|
||||
void SendChar(int ch)
|
||||
{
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
g_buf[g_buf_len++] = ch;
|
||||
g_buf[g_buf_len] = '\0';
|
||||
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
|
||||
{
|
||||
/* Send the char */
|
||||
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
|
||||
{
|
||||
g_buf_len = 0;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 0; i < g_buf_len; i++)
|
||||
SendChar_ToUART(g_buf[i]);
|
||||
g_buf_len = 0;
|
||||
}
|
||||
}
|
||||
#else
|
||||
SendChar_ToUART(ch);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Routine to get a char
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns Get value from UART debug port or semihost
|
||||
*
|
||||
* @details Wait UART debug port or semihost to input a char.
|
||||
*/
|
||||
char GetChar(void)
|
||||
{
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# if defined (__CC_ARM)
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x101, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
{
|
||||
SH_DoCommand(0x07, 0, &nRet);
|
||||
return (char)nRet;
|
||||
}
|
||||
}
|
||||
# else
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x7, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
return (char)nRet;
|
||||
}
|
||||
# endif
|
||||
return (0);
|
||||
#else
|
||||
|
||||
while(1)
|
||||
{
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)
|
||||
{
|
||||
return (DEBUG_PORT->DAT);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check any char input from UART
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: No any char input
|
||||
* @retval 0: Have some char input
|
||||
*
|
||||
* @details Check UART RSR RX EMPTY or not to determine if any char input from UART
|
||||
*/
|
||||
|
||||
int kbhit(void)
|
||||
{
|
||||
return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0);
|
||||
}
|
||||
/**
|
||||
* @brief Check if debug message finished
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: Message is finished
|
||||
* @retval 0: Message is transmitting.
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
int IsDebugFifoEmpty(void)
|
||||
{
|
||||
return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief C library retargetting
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
SendChar(ch);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write character to stream
|
||||
*
|
||||
* @param[in] ch Character to be written. The character is passed as its int promotion.
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
|
||||
*
|
||||
* @returns If there are no errors, the same character that has been written is returned.
|
||||
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
|
||||
*
|
||||
* @details Writes a character to the stream and advances the position indicator.\n
|
||||
* The character is written at the current position of the stream as indicated \n
|
||||
* by the internal position indicator, which is then advanced one character.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
int fputc(int ch, FILE *stream)
|
||||
{
|
||||
SendChar(ch);
|
||||
return ch;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get character from UART debug port or semihosting input
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
|
||||
*
|
||||
* @returns The character read from UART debug port or semihosting
|
||||
*
|
||||
* @details For get message from debug port or semihosting.
|
||||
*
|
||||
*/
|
||||
|
||||
int fgetc(FILE *stream)
|
||||
{
|
||||
return (GetChar());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check error indicator
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream.
|
||||
*
|
||||
* @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
|
||||
* Otherwise, it returns a zero value.
|
||||
*
|
||||
* @details Checks if the error indicator associated with stream is set, returning a value different
|
||||
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
|
||||
*
|
||||
*/
|
||||
|
||||
int ferror(FILE *stream)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# ifdef __ICCARM__
|
||||
void __exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# else
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
;/******************************************************************************
|
||||
; * @file startup_M451Series.s
|
||||
; * @version V0.10
|
||||
; * $Revision: 5 $
|
||||
; * $Date: 14/12/24 10:20a $
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for M451 Series MCU
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
;*****************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
; User may overwrite stack size setting by pre-defined symbol
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00000400
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD BOD_IRQHandler ; 0: Brown Out detection
|
||||
DCD IRC_IRQHandler ; 1: Internal RC
|
||||
DCD PWRWU_IRQHandler ; 2: Power down wake up
|
||||
DCD RAMPE_IRQHandler ; 3: RAM parity error
|
||||
DCD CLKFAIL_IRQHandler ; 4: Clock detection fail
|
||||
DCD Default_Handler ; 5: Reserved
|
||||
DCD RTC_IRQHandler ; 6: Real Time Clock
|
||||
DCD TAMPER_IRQHandler ; 7: Tamper detection
|
||||
DCD WDT_IRQHandler ; 8: Watchdog timer
|
||||
DCD WWDT_IRQHandler ; 9: Window watchdog timer
|
||||
DCD EINT0_IRQHandler ; 10: External Input 0
|
||||
DCD EINT1_IRQHandler ; 11: External Input 1
|
||||
DCD EINT2_IRQHandler ; 12: External Input 2
|
||||
DCD EINT3_IRQHandler ; 13: External Input 3
|
||||
DCD EINT4_IRQHandler ; 14: External Input 4
|
||||
DCD EINT5_IRQHandler ; 15: External Input 5
|
||||
DCD GPA_IRQHandler ; 16: GPIO Port A
|
||||
DCD GPB_IRQHandler ; 17: GPIO Port B
|
||||
DCD GPC_IRQHandler ; 18: GPIO Port C
|
||||
DCD GPD_IRQHandler ; 19: GPIO Port D
|
||||
DCD GPE_IRQHandler ; 20: GPIO Port E
|
||||
DCD GPF_IRQHandler ; 21: GPIO Port F
|
||||
DCD SPI0_IRQHandler ; 22: SPI0
|
||||
DCD SPI1_IRQHandler ; 23: SPI1
|
||||
DCD BRAKE0_IRQHandler ; 24:
|
||||
DCD PWM0P0_IRQHandler ; 25:
|
||||
DCD PWM0P1_IRQHandler ; 26:
|
||||
DCD PWM0P2_IRQHandler ; 27:
|
||||
DCD BRAKE1_IRQHandler ; 28:
|
||||
DCD PWM1P0_IRQHandler ; 29:
|
||||
DCD PWM1P1_IRQHandler ; 30:
|
||||
DCD PWM1P2_IRQHandler ; 31:
|
||||
DCD TMR0_IRQHandler ; 32: Timer 0
|
||||
DCD TMR1_IRQHandler ; 33: Timer 1
|
||||
DCD TMR2_IRQHandler ; 34: Timer 2
|
||||
DCD TMR3_IRQHandler ; 35: Timer 3
|
||||
DCD UART0_IRQHandler ; 36: UART0
|
||||
DCD UART1_IRQHandler ; 37: UART1
|
||||
DCD I2C0_IRQHandler ; 38: I2C0
|
||||
DCD I2C1_IRQHandler ; 39: I2C1
|
||||
DCD PDMA_IRQHandler ; 40: Peripheral DMA
|
||||
DCD DAC_IRQHandler ; 41: DAC
|
||||
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
|
||||
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
|
||||
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
|
||||
DCD Default_Handler ; 45: Reserved
|
||||
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
|
||||
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
|
||||
DCD UART2_IRQHandler ; 48: UART2
|
||||
DCD UART3_IRQHandler ; 49: UART3
|
||||
DCD Default_Handler ; 50: Reserved
|
||||
DCD SPI2_IRQHandler ; 51: SPI2
|
||||
DCD Default_Handler ; 52: Reserved
|
||||
DCD USBD_IRQHandler ; 53: USB device
|
||||
DCD USBH_IRQHandler ; 54: USB host
|
||||
DCD USBOTG_IRQHandler ; 55: USB OTG
|
||||
DCD CAN0_IRQHandler ; 56: CAN0
|
||||
DCD Default_Handler ; 57: Reserved
|
||||
DCD SC0_IRQHandler ; 58:
|
||||
DCD Default_Handler ; 59: Reserved.
|
||||
DCD Default_Handler ; 60:
|
||||
DCD Default_Handler ; 61:
|
||||
DCD Default_Handler ; 62:
|
||||
DCD TK_IRQHandler ; 63:
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Select INV Type
|
||||
LDR R2, =0x40000200
|
||||
LDR R1, [R2]
|
||||
BIC R1, R1, #0x1000
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT IRC_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT RAMPE_IRQHandler [WEAK]
|
||||
EXPORT CLKFAIL_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT EINT4_IRQHandler [WEAK]
|
||||
EXPORT EINT5_IRQHandler [WEAK]
|
||||
EXPORT GPA_IRQHandler [WEAK]
|
||||
EXPORT GPB_IRQHandler [WEAK]
|
||||
EXPORT GPC_IRQHandler [WEAK]
|
||||
EXPORT GPD_IRQHandler [WEAK]
|
||||
EXPORT GPE_IRQHandler [WEAK]
|
||||
EXPORT GPF_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT BRAKE0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P1_IRQHandler [WEAK]
|
||||
EXPORT PWM0P2_IRQHandler [WEAK]
|
||||
EXPORT BRAKE1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P0_IRQHandler [WEAK]
|
||||
EXPORT PWM1P1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P2_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT ADC00_IRQHandler [WEAK]
|
||||
EXPORT ADC01_IRQHandler [WEAK]
|
||||
EXPORT ACMP01_IRQHandler [WEAK]
|
||||
EXPORT ADC02_IRQHandler [WEAK]
|
||||
EXPORT ADC03_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT USBH_IRQHandler [WEAK]
|
||||
EXPORT USBOTG_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT SC0_IRQHandler [WEAK]
|
||||
EXPORT TK_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
IRC_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
RAMPE_IRQHandler
|
||||
CLKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
WDT_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
EINT4_IRQHandler
|
||||
EINT5_IRQHandler
|
||||
GPA_IRQHandler
|
||||
GPB_IRQHandler
|
||||
GPC_IRQHandler
|
||||
GPD_IRQHandler
|
||||
GPE_IRQHandler
|
||||
GPF_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
BRAKE0_IRQHandler
|
||||
PWM0P0_IRQHandler
|
||||
PWM0P1_IRQHandler
|
||||
PWM0P2_IRQHandler
|
||||
BRAKE1_IRQHandler
|
||||
PWM1P0_IRQHandler
|
||||
PWM1P1_IRQHandler
|
||||
PWM1P2_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
DAC_IRQHandler
|
||||
ADC00_IRQHandler
|
||||
ADC01_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
ADC02_IRQHandler
|
||||
ADC03_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USBD_IRQHandler
|
||||
USBH_IRQHandler
|
||||
USBOTG_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
SC0_IRQHandler
|
||||
TK_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
;/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/******************************************************************************
|
||||
* @file system_M451Series.c
|
||||
* @version V0.10
|
||||
* $Revision: 11 $
|
||||
* $Date: 15/09/02 10:02a $
|
||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "M451Series.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
||||
{
|
||||
#if 1
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
|
||||
//if(SystemCoreClock == 0)
|
||||
// __BKPT(0);
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param None
|
||||
* @return None
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* ToDo: add code to initialize the system
|
||||
do not use global variables because this function is called before
|
||||
reaching pre-main. RW section maybe overwritten afterwards. */
|
||||
|
||||
SYS_UnlockReg();
|
||||
/* One-time POR18 */
|
||||
if((SYS->PDID >> 12) == 0x945)
|
||||
{
|
||||
M32(GCR_BASE+0x14) |= BIT7;
|
||||
}
|
||||
/* Force to use INV type with HXT */
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
|
||||
SYS_LockReg();
|
||||
|
||||
|
||||
#ifdef EBI_INIT
|
||||
extern void SYS_Init();
|
||||
extern void EBI_Init();
|
||||
|
||||
SYS_UnlockReg();
|
||||
SYS_Init();
|
||||
EBI_Init();
|
||||
SYS_LockReg();
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
|
||||
(3UL << 11 * 2)); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
}
|
||||
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,678 @@
|
|||
/**************************************************************************//**
|
||||
* @file retarget.c
|
||||
* @version V3.00
|
||||
* $Revision: 13 $
|
||||
* $Date: 15/08/11 10:26a $
|
||||
* @brief M451 Series Debug Port and Semihost Setting Source File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include "M451Series.h"
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
#else
|
||||
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
|
||||
#pragma import _printf_widthprec
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Global variables */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
#endif
|
||||
FILE __stdout;
|
||||
FILE __stdin;
|
||||
|
||||
enum { r0, r1, r2, r3, r12, lr, pc, psr};
|
||||
|
||||
/**
|
||||
* @brief Helper function to dump register while hard fault occurred
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*/
|
||||
static void stackDump(uint32_t stack[])
|
||||
{
|
||||
printf("r0 = 0x%x\n", stack[r0]);
|
||||
printf("r1 = 0x%x\n", stack[r1]);
|
||||
printf("r2 = 0x%x\n", stack[r2]);
|
||||
printf("r3 = 0x%x\n", stack[r3]);
|
||||
printf("r12 = 0x%x\n", stack[r12]);
|
||||
printf("lr = 0x%x\n", stack[lr]);
|
||||
printf("pc = 0x%x\n", stack[pc]);
|
||||
printf("psr = 0x%x\n", stack[psr]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hard fault handler
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product
|
||||
*/
|
||||
void Hard_Fault_Handler(uint32_t stack[])
|
||||
{
|
||||
printf("In Hard Fault Handler\n");
|
||||
|
||||
stackDump(stack);
|
||||
// Replace while(1) with chip reset if WDT is not enabled for end product
|
||||
while(1);
|
||||
//SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Routine to write a char */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
/* The static buffer is used to speed up the semihost */
|
||||
static char g_buf[16];
|
||||
static char g_buf_len = 0;
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void SH_End(void)
|
||||
{
|
||||
asm("MOVS R0,#1 \n" //; Set return value to 1
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
}
|
||||
|
||||
void SH_ICE(void)
|
||||
{
|
||||
asm("CMP R2,#0 \n"
|
||||
"BEQ SH_End \n"
|
||||
"STR R0,[R2] \n" //; Save the return value to *pn32Out_R0
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
|
||||
"B SH_ICE \n"
|
||||
"SH_HardFault: \n" //; Captured by HardFault
|
||||
"MOVS R0,#0 \n" //; Set return value to 0
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
|
||||
return 1; //; Return 1 when it is trap by ICE
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LR value and branch to Hard_Fault_Handler function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get LR value and branch to Hard_Fault_Handler function.
|
||||
*/
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MSP value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void HardFault_Handler_Ret(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void SP_Read_Ready(void)
|
||||
{
|
||||
asm("LDR R1, [R0, #24] \n" //; Get previous PC
|
||||
"LDRH R3, [R1] \n" //; Get instruction
|
||||
"LDR R2, [pc, #8] \n" //; The special BKPT instruction
|
||||
"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
|
||||
"BNE HardFault_Handler_Ret \n" //; Not BKPT
|
||||
"ADDS R1, #4 \n" //; Skip BKPT and next line
|
||||
"STR R1, [R0, #24] \n" //; Save previous PC
|
||||
"BX lr \n" //; Return
|
||||
"DCD 0xBEAB \n" //; BKPT instruction code
|
||||
"B HardFault_Handler_Ret \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void SP_is_PSP(void)
|
||||
{
|
||||
asm(
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler (void)
|
||||
{
|
||||
asm("MOV R0, lr \n"
|
||||
"LSLS R0, #29 \n" //; Check bit 2
|
||||
"BMI SP_is_PSP \n" //; previous stack is PSP
|
||||
"MRS R0, MSP \n" //; previous stack is MSP, read MSP
|
||||
"B SP_Read_Ready \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOV R0, LR
|
||||
LSLS R0, #29 //; Check bit 2
|
||||
BMI SP_is_PSP //; previous stack is PSP
|
||||
MRS R0, MSP //; previous stack is MSP, read MSP
|
||||
B SP_Read_Ready
|
||||
SP_is_PSP
|
||||
MRS R0, PSP //; Read PSP
|
||||
|
||||
SP_Read_Ready
|
||||
LDR R1, [R0, #24] //; Get previous PC
|
||||
LDRH R3, [R1] //; Get instruction
|
||||
LDR R2, =0xBEAB //; The special BKPT instruction
|
||||
CMP R3, R2 //; Test if the instruction at previous PC is BKPT
|
||||
BNE HardFault_Handler_Ret //; Not BKPT
|
||||
|
||||
ADDS R1, #4 //; Skip BKPT and next line
|
||||
STR R1, [R0, #24] //; Save previous PC
|
||||
|
||||
BX LR //; Return
|
||||
HardFault_Handler_Ret
|
||||
|
||||
/* TODO: Implement your own hard fault handler here. */
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP ;stack use PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP ; stack use MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR ; LR current value //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
|
||||
B .
|
||||
|
||||
ALIGN
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
BKPT 0xAB //; Wait ICE or HardFault
|
||||
//; ICE will step over BKPT directly
|
||||
//; HardFault will step BKPT and the next line
|
||||
B SH_ICE
|
||||
|
||||
SH_HardFault //; Captured by HardFault
|
||||
MOVS R0, #0 //; Set return value to 0
|
||||
BX lr //; Return
|
||||
|
||||
SH_ICE //; Captured by ICE
|
||||
//; Save return value
|
||||
CMP R2, #0
|
||||
BEQ SH_End
|
||||
STR R0, [R2] //; Save the return value to *pn32Out_R0
|
||||
|
||||
SH_End
|
||||
MOVS R0, #1 //; Set return value to 1
|
||||
BX lr //; Return
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function extracts the location of stack frame and passes it to Hard_Fault_Handler function as a pointer
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port
|
||||
*
|
||||
* @details Send a target char to UART debug port .
|
||||
*/
|
||||
#ifndef NONBLOCK_PRINTF
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
|
||||
DEBUG_PORT->DAT = ch;
|
||||
if(ch == '\n')
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
DEBUG_PORT->DAT = '\r';
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* Non-block implement of send char */
|
||||
#define BUF_SIZE 2048
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
static uint8_t u8Buf[BUF_SIZE] = {0};
|
||||
static int32_t i32Head = 0;
|
||||
static int32_t i32Tail = 0;
|
||||
int32_t i32Tmp;
|
||||
|
||||
/* Only flush the data in buffer to UART when ch == 0 */
|
||||
if(ch)
|
||||
{
|
||||
// Push char
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = ch;
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
|
||||
if(ch == '\n')
|
||||
{
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = '\r';
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(i32Tail == i32Head)
|
||||
return;
|
||||
}
|
||||
|
||||
// pop char
|
||||
do
|
||||
{
|
||||
i32Tmp = i32Tail + 1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) == 0)
|
||||
{
|
||||
DEBUG_PORT->DAT = u8Buf[i32Tail];
|
||||
i32Tail = i32Tmp;
|
||||
}
|
||||
else
|
||||
break; // FIFO full
|
||||
}while(i32Tail != i32Head);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port or semihost
|
||||
*
|
||||
* @details Send a target char to UART debug port or semihost.
|
||||
*/
|
||||
void SendChar(int ch)
|
||||
{
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
g_buf[g_buf_len++] = ch;
|
||||
g_buf[g_buf_len] = '\0';
|
||||
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
|
||||
{
|
||||
/* Send the char */
|
||||
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
|
||||
{
|
||||
g_buf_len = 0;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 0; i < g_buf_len; i++)
|
||||
SendChar_ToUART(g_buf[i]);
|
||||
g_buf_len = 0;
|
||||
}
|
||||
}
|
||||
#else
|
||||
SendChar_ToUART(ch);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Routine to get a char
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns Get value from UART debug port or semihost
|
||||
*
|
||||
* @details Wait UART debug port or semihost to input a char.
|
||||
*/
|
||||
char GetChar(void)
|
||||
{
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# if defined (__CC_ARM)
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x101, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
{
|
||||
SH_DoCommand(0x07, 0, &nRet);
|
||||
return (char)nRet;
|
||||
}
|
||||
}
|
||||
# else
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x7, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
return (char)nRet;
|
||||
}
|
||||
# endif
|
||||
return (0);
|
||||
#else
|
||||
|
||||
while(1)
|
||||
{
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)
|
||||
{
|
||||
return (DEBUG_PORT->DAT);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check any char input from UART
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: No any char input
|
||||
* @retval 0: Have some char input
|
||||
*
|
||||
* @details Check UART RSR RX EMPTY or not to determine if any char input from UART
|
||||
*/
|
||||
|
||||
int kbhit(void)
|
||||
{
|
||||
return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0);
|
||||
}
|
||||
/**
|
||||
* @brief Check if debug message finished
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: Message is finished
|
||||
* @retval 0: Message is transmitting.
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
int IsDebugFifoEmpty(void)
|
||||
{
|
||||
return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief C library retargetting
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
SendChar(ch);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write character to stream
|
||||
*
|
||||
* @param[in] ch Character to be written. The character is passed as its int promotion.
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
|
||||
*
|
||||
* @returns If there are no errors, the same character that has been written is returned.
|
||||
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
|
||||
*
|
||||
* @details Writes a character to the stream and advances the position indicator.\n
|
||||
* The character is written at the current position of the stream as indicated \n
|
||||
* by the internal position indicator, which is then advanced one character.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
int fputc(int ch, FILE *stream)
|
||||
{
|
||||
SendChar(ch);
|
||||
return ch;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get character from UART debug port or semihosting input
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
|
||||
*
|
||||
* @returns The character read from UART debug port or semihosting
|
||||
*
|
||||
* @details For get message from debug port or semihosting.
|
||||
*
|
||||
*/
|
||||
|
||||
int fgetc(FILE *stream)
|
||||
{
|
||||
return (GetChar());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check error indicator
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream.
|
||||
*
|
||||
* @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
|
||||
* Otherwise, it returns a zero value.
|
||||
*
|
||||
* @details Checks if the error indicator associated with stream is set, returning a value different
|
||||
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
|
||||
*
|
||||
*/
|
||||
|
||||
int ferror(FILE *stream)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# ifdef __ICCARM__
|
||||
void __exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# else
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
;/******************************************************************************
|
||||
; * @file startup_M451Series.s
|
||||
; * @version V0.10
|
||||
; * $Revision: 5 $
|
||||
; * $Date: 14/12/24 10:20a $
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for M451 Series MCU
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
;*****************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
; User may overwrite stack size setting by pre-defined symbol
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00000400
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD BOD_IRQHandler ; 0: Brown Out detection
|
||||
DCD IRC_IRQHandler ; 1: Internal RC
|
||||
DCD PWRWU_IRQHandler ; 2: Power down wake up
|
||||
DCD RAMPE_IRQHandler ; 3: RAM parity error
|
||||
DCD CLKFAIL_IRQHandler ; 4: Clock detection fail
|
||||
DCD Default_Handler ; 5: Reserved
|
||||
DCD RTC_IRQHandler ; 6: Real Time Clock
|
||||
DCD TAMPER_IRQHandler ; 7: Tamper detection
|
||||
DCD WDT_IRQHandler ; 8: Watchdog timer
|
||||
DCD WWDT_IRQHandler ; 9: Window watchdog timer
|
||||
DCD EINT0_IRQHandler ; 10: External Input 0
|
||||
DCD EINT1_IRQHandler ; 11: External Input 1
|
||||
DCD EINT2_IRQHandler ; 12: External Input 2
|
||||
DCD EINT3_IRQHandler ; 13: External Input 3
|
||||
DCD EINT4_IRQHandler ; 14: External Input 4
|
||||
DCD EINT5_IRQHandler ; 15: External Input 5
|
||||
DCD GPA_IRQHandler ; 16: GPIO Port A
|
||||
DCD GPB_IRQHandler ; 17: GPIO Port B
|
||||
DCD GPC_IRQHandler ; 18: GPIO Port C
|
||||
DCD GPD_IRQHandler ; 19: GPIO Port D
|
||||
DCD GPE_IRQHandler ; 20: GPIO Port E
|
||||
DCD GPF_IRQHandler ; 21: GPIO Port F
|
||||
DCD SPI0_IRQHandler ; 22: SPI0
|
||||
DCD SPI1_IRQHandler ; 23: SPI1
|
||||
DCD BRAKE0_IRQHandler ; 24:
|
||||
DCD PWM0P0_IRQHandler ; 25:
|
||||
DCD PWM0P1_IRQHandler ; 26:
|
||||
DCD PWM0P2_IRQHandler ; 27:
|
||||
DCD BRAKE1_IRQHandler ; 28:
|
||||
DCD PWM1P0_IRQHandler ; 29:
|
||||
DCD PWM1P1_IRQHandler ; 30:
|
||||
DCD PWM1P2_IRQHandler ; 31:
|
||||
DCD TMR0_IRQHandler ; 32: Timer 0
|
||||
DCD TMR1_IRQHandler ; 33: Timer 1
|
||||
DCD TMR2_IRQHandler ; 34: Timer 2
|
||||
DCD TMR3_IRQHandler ; 35: Timer 3
|
||||
DCD UART0_IRQHandler ; 36: UART0
|
||||
DCD UART1_IRQHandler ; 37: UART1
|
||||
DCD I2C0_IRQHandler ; 38: I2C0
|
||||
DCD I2C1_IRQHandler ; 39: I2C1
|
||||
DCD PDMA_IRQHandler ; 40: Peripheral DMA
|
||||
DCD DAC_IRQHandler ; 41: DAC
|
||||
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
|
||||
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
|
||||
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
|
||||
DCD Default_Handler ; 45: Reserved
|
||||
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
|
||||
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
|
||||
DCD UART2_IRQHandler ; 48: UART2
|
||||
DCD UART3_IRQHandler ; 49: UART3
|
||||
DCD Default_Handler ; 50: Reserved
|
||||
DCD SPI2_IRQHandler ; 51: SPI2
|
||||
DCD Default_Handler ; 52: Reserved
|
||||
DCD USBD_IRQHandler ; 53: USB device
|
||||
DCD USBH_IRQHandler ; 54: USB host
|
||||
DCD USBOTG_IRQHandler ; 55: USB OTG
|
||||
DCD CAN0_IRQHandler ; 56: CAN0
|
||||
DCD Default_Handler ; 57: Reserved
|
||||
DCD SC0_IRQHandler ; 58:
|
||||
DCD Default_Handler ; 59: Reserved.
|
||||
DCD Default_Handler ; 60:
|
||||
DCD Default_Handler ; 61:
|
||||
DCD Default_Handler ; 62:
|
||||
DCD TK_IRQHandler ; 63:
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Select INV Type
|
||||
LDR R2, =0x40000200
|
||||
LDR R1, [R2]
|
||||
BIC R1, R1, #0x1000
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT IRC_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT RAMPE_IRQHandler [WEAK]
|
||||
EXPORT CLKFAIL_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT EINT4_IRQHandler [WEAK]
|
||||
EXPORT EINT5_IRQHandler [WEAK]
|
||||
EXPORT GPA_IRQHandler [WEAK]
|
||||
EXPORT GPB_IRQHandler [WEAK]
|
||||
EXPORT GPC_IRQHandler [WEAK]
|
||||
EXPORT GPD_IRQHandler [WEAK]
|
||||
EXPORT GPE_IRQHandler [WEAK]
|
||||
EXPORT GPF_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT BRAKE0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P1_IRQHandler [WEAK]
|
||||
EXPORT PWM0P2_IRQHandler [WEAK]
|
||||
EXPORT BRAKE1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P0_IRQHandler [WEAK]
|
||||
EXPORT PWM1P1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P2_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT ADC00_IRQHandler [WEAK]
|
||||
EXPORT ADC01_IRQHandler [WEAK]
|
||||
EXPORT ACMP01_IRQHandler [WEAK]
|
||||
EXPORT ADC02_IRQHandler [WEAK]
|
||||
EXPORT ADC03_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT USBH_IRQHandler [WEAK]
|
||||
EXPORT USBOTG_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT SC0_IRQHandler [WEAK]
|
||||
EXPORT TK_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
IRC_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
RAMPE_IRQHandler
|
||||
CLKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
WDT_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
EINT4_IRQHandler
|
||||
EINT5_IRQHandler
|
||||
GPA_IRQHandler
|
||||
GPB_IRQHandler
|
||||
GPC_IRQHandler
|
||||
GPD_IRQHandler
|
||||
GPE_IRQHandler
|
||||
GPF_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
BRAKE0_IRQHandler
|
||||
PWM0P0_IRQHandler
|
||||
PWM0P1_IRQHandler
|
||||
PWM0P2_IRQHandler
|
||||
BRAKE1_IRQHandler
|
||||
PWM1P0_IRQHandler
|
||||
PWM1P1_IRQHandler
|
||||
PWM1P2_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
DAC_IRQHandler
|
||||
ADC00_IRQHandler
|
||||
ADC01_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
ADC02_IRQHandler
|
||||
ADC03_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USBD_IRQHandler
|
||||
USBH_IRQHandler
|
||||
USBOTG_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
SC0_IRQHandler
|
||||
TK_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
;/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/******************************************************************************
|
||||
* @file system_M451Series.c
|
||||
* @version V0.10
|
||||
* $Revision: 11 $
|
||||
* $Date: 15/09/02 10:02a $
|
||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "M451Series.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
||||
{
|
||||
#if 1
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
|
||||
//if(SystemCoreClock == 0)
|
||||
// __BKPT(0);
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param None
|
||||
* @return None
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* ToDo: add code to initialize the system
|
||||
do not use global variables because this function is called before
|
||||
reaching pre-main. RW section maybe overwritten afterwards. */
|
||||
|
||||
SYS_UnlockReg();
|
||||
/* One-time POR18 */
|
||||
if((SYS->PDID >> 12) == 0x945)
|
||||
{
|
||||
M32(GCR_BASE+0x14) |= BIT7;
|
||||
}
|
||||
/* Force to use INV type with HXT */
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
|
||||
SYS_LockReg();
|
||||
|
||||
|
||||
#ifdef EBI_INIT
|
||||
extern void SYS_Init();
|
||||
extern void EBI_Init();
|
||||
|
||||
SYS_UnlockReg();
|
||||
SYS_Init();
|
||||
EBI_Init();
|
||||
SYS_LockReg();
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
|
||||
(3UL << 11 * 2)); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
}
|
||||
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
;/*---------------------------------------------------------------------------------------------------------*/
|
||||
;/* */
|
||||
;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
|
||||
;/* */
|
||||
;/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
CLK_BA_base EQU 0x50000200
|
||||
PWRCON EQU 0x00
|
||||
AHBCLK EQU 0x04
|
||||
APBCLK EQU 0x08
|
||||
CLKSEL0 EQU 0x10
|
||||
CLKSEL1 EQU 0x14
|
||||
CLKDIV EQU 0x18
|
||||
PLLCON EQU 0x20
|
||||
TEST_S EQU 0x30
|
||||
|
||||
CLK_BA_APBCLK EQU 0x50000208
|
||||
|
||||
;// Define clock enable registers
|
||||
|
||||
ADC_COMP_CLK EQU 0x50000208
|
||||
ADC_enable EQU 0x10000000
|
||||
COMP_enable EQU 0x40000000
|
||||
|
||||
PDMA_CLK EQU 0x50000204
|
||||
PDMA_enable EQU 0x00000003
|
||||
|
||||
;; bit 0 CPU_EN
|
||||
;; bit 1 PDMA_EN
|
||||
|
||||
|
||||
|
||||
|
||||
;// Define COMP registers base
|
||||
COMP_base EQU 0x400D0000
|
||||
CMP1CR EQU 0x00
|
||||
CMP2CR EQU 0x04
|
||||
CMPSR EQU 0x08
|
||||
|
||||
;// Define ADC registers base
|
||||
ADC_base EQU 0x400E0000
|
||||
ADDR0 EQU 0x00
|
||||
ADDR1 EQU 0x04
|
||||
ADDR2 EQU 0x08
|
||||
ADDR3 EQU 0x0c
|
||||
ADDR4 EQU 0x10
|
||||
ADDR5 EQU 0x14
|
||||
ADDR6 EQU 0x18
|
||||
ADDR7 EQU 0x1c
|
||||
ADCR EQU 0x20
|
||||
ADCHER EQU 0x24
|
||||
ADCMPR0 EQU 0x28
|
||||
ADCMPR1 EQU 0x2c
|
||||
ADSR EQU 0x30
|
||||
ADCALR EQU 0x34
|
||||
ADCFCR EQU 0x38
|
||||
ADCALD EQU 0x3c
|
||||
|
||||
;// Pattern Table
|
||||
pattern_55555555 EQU 0x55555555
|
||||
pattern_aaaaaaaa EQU 0xaaaaaaaa
|
||||
pattern_00005555 EQU 0x00005555
|
||||
pattern_0000aaaa EQU 0x0000aaaa
|
||||
pattern_05550515 EQU 0x05550515
|
||||
pattern_0aaa0a2a EQU 0x0aaa0a2a
|
||||
|
||||
;// Define PDMA regsiter base
|
||||
PDMA_BA_ch0_base EQU 0x50008000
|
||||
PDMA_BA_ch1_base EQU 0x50008100
|
||||
PDMA_BA_ch2_base EQU 0x50008200
|
||||
PDMA_BA_ch3_base EQU 0x50008300
|
||||
PDMA_BA_ch4_base EQU 0x50008400
|
||||
PDMA_BA_ch5_base EQU 0x50008500
|
||||
PDMA_BA_ch6_base EQU 0x50008600
|
||||
PDMA_BA_ch7_base EQU 0x50008700
|
||||
|
||||
PDMA_BA_GCR EQU 0x50008F00
|
||||
PDMA_BA_GCR_base EQU 0x50008F00
|
||||
|
||||
PDMA_GCRCSR EQU 0X00
|
||||
PDMA_PDSSR2 EQU 0X04
|
||||
PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000
|
||||
PDMA_GCRISR EQU 0X0C
|
||||
|
||||
PDMA_GLOBAL_enable EQU 0x0000FF00
|
||||
|
||||
|
||||
PDMA_CSR EQU 0X00
|
||||
PDMA_SAR EQU 0X04
|
||||
PDMA_DAR EQU 0X08
|
||||
PDMA_BCR EQU 0X0C
|
||||
PDMA_CSAR EQU 0X14
|
||||
PDMA_CDAR EQU 0X18
|
||||
PDMA_CBSR EQU 0X1C
|
||||
PDMA_IER EQU 0X20
|
||||
PDMA_ISR EQU 0X24
|
||||
PDMA_CTCSR EQU 0X28
|
||||
PDMA_SASOCR EQU 0X2C
|
||||
PDMA_DASOCR EQU 0X30
|
||||
PDMA_SBUF0 EQU 0X80
|
||||
PDMA_SBUF1 EQU 0X84
|
||||
PDMA_SBUF2 EQU 0X88
|
||||
PDMA_SBUF3 EQU 0X8C
|
||||
|
||||
|
||||
;// Define VIC control register
|
||||
VIC_base EQU 0xFFFF0000
|
||||
VIC_SCR15 EQU 0x003c
|
||||
VIC_SVR15 EQU 0x00bc
|
||||
VIC_SCR16 EQU 0x0040
|
||||
VIC_SVR16 EQU 0x00c0
|
||||
VIC_SCR30 EQU 0x0078
|
||||
VIC_SVR30 EQU 0x00f8
|
||||
VIC_MECR EQU 0x0318
|
||||
VIC_MDCR EQU 0x031c
|
||||
VIC_EOSCR EQU 0x0130
|
||||
|
||||
;//==================================
|
||||
INT_BA_base EQU 0x50000300
|
||||
|
||||
|
||||
;// Parameter table
|
||||
ADC_PDMA_CFG EQU 0x00002980
|
||||
ADC_PDMA_DST EQU 0xC0000000
|
||||
ADC_PDMA_SRC EQU 0xE0024200
|
||||
ADC_PDMA_TCBL EQU 0x00030008
|
||||
|
||||
;//==================================
|
||||
|
||||
|
||||
GPIO_base EQU 0x50004000
|
||||
GPIOB_PMD EQU 0x0040
|
||||
GPIOB_OFFD EQU 0x0044
|
||||
GPIOB_DOUT EQU 0x0048
|
||||
GPIOB_DMASK EQU 0x004C
|
||||
GPIOB_PIN EQU 0x0050
|
||||
GPIOB_DBEN EQU 0x0054
|
||||
GPIOB_IMD EQU 0x0058
|
||||
GPIOB_IEN EQU 0x005C
|
||||
GPIOB_ISRC EQU 0x0060
|
||||
|
||||
;//==================================
|
||||
|
||||
|
||||
GCR_base EQU 0x50000000
|
||||
GPB_MFP EQU 0x0034
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00000400
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; maximum of 32 External Interrupts are possible
|
||||
DCD BOD_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD EINT0_IRQHandler
|
||||
DCD EINT1_IRQHandler
|
||||
DCD GPAB_IRQHandler
|
||||
DCD GPCDEF_IRQHandler
|
||||
DCD PWMA_IRQHandler
|
||||
DCD PWMB_IRQHandler
|
||||
DCD TMR0_IRQHandler
|
||||
DCD TMR1_IRQHandler
|
||||
DCD TMR2_IRQHandler
|
||||
DCD TMR3_IRQHandler
|
||||
DCD UART02_IRQHandler
|
||||
DCD UART1_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD SPI1_IRQHandler
|
||||
DCD SPI2_IRQHandler
|
||||
DCD SPI3_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD CAN0_IRQHandler
|
||||
DCD CAN1_IRQHandler
|
||||
DCD SC012_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD PS2_IRQHandler
|
||||
DCD ACMP_IRQHandler
|
||||
DCD PDMA_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD PWRWU_IRQHandler
|
||||
DCD ADC_IRQHandler
|
||||
DCD Default_Handler
|
||||
DCD RTC_IRQHandler
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
ENTRY
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x50000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x50000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT GPAB_IRQHandler [WEAK]
|
||||
EXPORT GPCDEF_IRQHandler [WEAK]
|
||||
EXPORT PWMA_IRQHandler [WEAK]
|
||||
EXPORT PWMB_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART02_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_IRQHandler [WEAK]
|
||||
EXPORT SC012_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT PS2_IRQHandler [WEAK]
|
||||
EXPORT ACMP_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
GPAB_IRQHandler
|
||||
GPCDEF_IRQHandler
|
||||
PWMA_IRQHandler
|
||||
PWMB_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART02_IRQHandler
|
||||
UART1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
CAN1_IRQHandler
|
||||
SC012_IRQHandler
|
||||
USBD_IRQHandler
|
||||
PS2_IRQHandler
|
||||
ACMP_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
I2S_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
ADC_IRQHandler
|
||||
RTC_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_NUC100Series.c
|
||||
* @version V3.0
|
||||
* $Revision: 1 $
|
||||
* $Date: 14/12/08 11:47a $
|
||||
* @brief NUC100 Series CMSIS System File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "NUC100Series.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, NULL, NULL, NULL, __HIRC};
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
This function is used to update the variable SystemCoreClock
|
||||
and must be called whenever the core clock is changed.
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
|
||||
|
||||
if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL)
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Function: SystemInit */
|
||||
/* */
|
||||
/* Parameters: */
|
||||
/* None */
|
||||
/* */
|
||||
/* Returns: */
|
||||
/* None */
|
||||
/* */
|
||||
/* Description: */
|
||||
/* The necessary initialization of system. */
|
||||
/* */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'OLED'
|
||||
* Target: 'Target 1'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "NUC100Series.h"
|
||||
|
||||
#define RTE_Drivers_CLK /* Driver CLK */
|
||||
#define RTE_Drivers_GPIO /* Driver GPIO */
|
||||
#define RTE_Drivers_I2C /* Driver I2C */
|
||||
#define RTE_Drivers_SC /* Driver SC */
|
||||
#define RTE_Drivers_UART /* Driver UART */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'OLED'
|
||||
* Target: 'oled'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "M451Series.h"
|
||||
|
||||
#define RTE_Drivers_CLK /* Driver CLK */
|
||||
#define RTE_Drivers_GPIO /* Driver GPIO */
|
||||
#define RTE_Drivers_I2C /* Driver I2C */
|
||||
#define RTE_Drivers_SC /* Driver SC */
|
||||
#define RTE_Drivers_SYS /* Driver SYS */
|
||||
#define RTE_Drivers_UART /* Driver UART */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,380 @@
|
|||
/************************************************************************************
|
||||
* Copyright (c), 2014, HelTec Automatic Technology co.,LTD.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Http: www.heltec.cn
|
||||
* Email: cn.heltec@gmail.com
|
||||
* WebShop: heltec.taobao.com
|
||||
*
|
||||
* File name: OLED.c
|
||||
* Project : HelTec.uvprij
|
||||
* Processor: STM32F103C8T6
|
||||
* Compiler : MDK fo ARM
|
||||
*
|
||||
* Author : С
|
||||
* Version: 1.00
|
||||
* Date : 2014.2.20
|
||||
* Email : hello14blog@gmail.com
|
||||
* Modification: none
|
||||
*
|
||||
* Description:
|
||||
* 1. 128*64ֻ֣OLEDģࠩ٦ŜҝʾԌѲքؖҭìˊԃheltec.taobao.com̹˛ӺƷ;
|
||||
* 2. ؖҭԉղѼ؊אքpȡؖɭݾq݆̣փԶ;
|
||||
* 3. ȡؖʽ -- ٲӵbѐʽbŦвˤԶ
|
||||
*
|
||||
* Others: none;
|
||||
*
|
||||
* Function List: node;
|
||||
*
|
||||
* History: none;
|
||||
*
|
||||
*************************************************************************************/
|
||||
|
||||
/***************************16*16քֳ֣ؖͥȡģʽúٲӵjjѐʽjjŦвˤԶ*********/
|
||||
#ifndef __CODETAB_H_
|
||||
#define __CODETAB_H_
|
||||
|
||||
unsigned char F16x16[] =
|
||||
{
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
|
||||
|
||||
0x00,0x02,0x02,0xFA,0xFA,0xAA,0xAA,0xFF,0xFF,0xAA,0xAA,0xFA,0xFA,0x02,0x02,0x00,
|
||||
0x00,0x42,0x72,0x72,0x3A,0x7A,0x42,0x4B,0x5B,0x52,0x62,0x62,0x13,0x77,0x66,0x00,/*"ܝ",1*/
|
||||
|
||||
0x20,0x3C,0x1C,0xFF,0xFF,0xB0,0xB4,0x24,0x24,0x3F,0x3F,0xE4,0xE4,0x24,0x24,0x20,
|
||||
0x02,0x02,0x03,0xFF,0xFF,0x00,0x01,0x05,0x1D,0x59,0xC1,0xFF,0x7F,0x01,0x01,0x01,/*"͘",2*/
|
||||
|
||||
0x00,0x00,0x00,0xF8,0xF8,0x48,0x4C,0x4F,0x4B,0x4A,0x48,0x48,0xF8,0xF8,0x00,0x00,
|
||||
0x00,0x00,0x00,0xFF,0xFF,0x44,0x44,0x44,0x44,0x44,0x44,0x44,0xFF,0xFF,0x00,0x00,/*"ؔ",3*/
|
||||
|
||||
0x20,0x24,0x24,0xE4,0xE4,0x24,0x24,0x24,0x30,0x10,0xFF,0xFF,0x10,0xF0,0xF0,0x00,
|
||||
0x08,0x1C,0x1F,0x0B,0x0C,0x0D,0x4F,0x6E,0x34,0x1C,0x0F,0x23,0x60,0x7F,0x3F,0x00,/*"֯",4*/
|
||||
|
||||
0x80,0xC0,0x60,0xF8,0xFF,0x07,0x02,0x00,0xFF,0xFF,0xE0,0x70,0x3C,0x1C,0x08,0x00,
|
||||
0x00,0x00,0x00,0x7F,0x7F,0x04,0x06,0x03,0x3F,0x7F,0x40,0x40,0x40,0x78,0x78,0x00,/*"ۯ",5*/
|
||||
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",6*/
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",6*/
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",7*/
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",7*/
|
||||
|
||||
|
||||
0x10,0x21,0x86,0x70,0x00,0x7E,0x4A,0x4A,0x4A,0x4A,0x4A,0x7E,0x00,0x00,0x00,0x00,
|
||||
0x02,0xFE,0x01,0x40,0x7F,0x41,0x41,0x7F,0x41,0x41,0x7F,0x41,0x41,0x7F,0x40,0x00,/*"ς",8*/
|
||||
0x00,0x00,0xFC,0x04,0x24,0x24,0xFC,0xA5,0xA6,0xA4,0xFC,0x24,0x24,0x24,0x04,0x00,
|
||||
0x80,0x60,0x1F,0x80,0x80,0x42,0x46,0x2A,0x12,0x12,0x2A,0x26,0x42,0xC0,0x40,0x00,/*"",9*/
|
||||
0x08,0x08,0x08,0xFF,0x88,0x48,0x00,0x98,0x48,0x28,0x0A,0x2C,0x48,0xD8,0x08,0x00,
|
||||
0x02,0x42,0x81,0x7F,0x00,0x00,0x40,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x40,0x00,/*"࠘",10*/
|
||||
0x00,0x50,0x4F,0x4A,0x48,0xFF,0x48,0x48,0x48,0x00,0xFC,0x00,0x00,0xFF,0x00,0x00,
|
||||
0x00,0x00,0x3F,0x01,0x01,0xFF,0x21,0x61,0x3F,0x00,0x0F,0x40,0x80,0x7F,0x00,0x00,/*"׆",11*/
|
||||
0x00,0x90,0x8C,0xA4,0xA4,0xA4,0xA5,0xA6,0xA4,0xA4,0xA4,0xA4,0x94,0x8C,0x04,0x00,
|
||||
0x00,0x80,0x40,0x20,0x18,0x07,0x00,0x00,0x00,0x3F,0x40,0x40,0x40,0x70,0x00,0x00,/*"Ϊ",12*/
|
||||
0x00,0x04,0x74,0xD4,0xFF,0xD4,0x74,0x04,0x10,0x0C,0xB7,0x44,0xB4,0x0C,0x04,0x00,
|
||||
0x00,0x42,0x43,0x7A,0x43,0x42,0x43,0x7E,0x4B,0x4B,0x4A,0x4A,0x42,0x43,0x01,0x00,/*"ֻ",13*/
|
||||
0x08,0x08,0x08,0x08,0x08,0x08,0xF9,0x4A,0x4C,0x48,0x48,0xC8,0x08,0x08,0x08,0x00,
|
||||
0x40,0x40,0x20,0x10,0x0C,0x03,0x00,0x00,0x20,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,/*"",14*/
|
||||
0x00,0x20,0x2C,0x24,0x64,0x74,0xAD,0xA6,0xE4,0x34,0x24,0x24,0x2C,0x24,0x00,0x00,
|
||||
0x00,0x24,0x24,0x25,0x15,0x15,0x0D,0xFE,0x04,0x0D,0x17,0x14,0x24,0x64,0x24,0x00,/*"и",15*/
|
||||
|
||||
|
||||
0x00,0x00,0x00,0xF8,0x48,0x48,0x4C,0x4B,0x4A,0x48,0x48,0x48,0xF8,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0xFF,0x44,0x44,0x44,0x44,0x44,0x44,0x44,0x44,0xFF,0x00,0x00,0x00,/*"ؔ",16*/
|
||||
0x20,0x24,0x24,0xE4,0x24,0x24,0x24,0x20,0x10,0x10,0xFF,0x10,0x10,0xF0,0x00,0x00,
|
||||
0x08,0x1C,0x0B,0x08,0x0C,0x05,0x4E,0x24,0x10,0x0C,0x03,0x20,0x40,0x3F,0x00,0x00,/*"֯",17*/
|
||||
0x08,0x08,0x08,0xFF,0x88,0x48,0x00,0x98,0x48,0x28,0x0A,0x2C,0x48,0xD8,0x08,0x00,
|
||||
0x02,0x42,0x81,0x7F,0x00,0x00,0x40,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x40,0x00,/*"࠘",18*/
|
||||
0x00,0x50,0x4F,0x4A,0x48,0xFF,0x48,0x48,0x48,0x00,0xFC,0x00,0x00,0xFF,0x00,0x00,
|
||||
0x00,0x00,0x3F,0x01,0x01,0xFF,0x21,0x61,0x3F,0x00,0x0F,0x40,0x80,0x7F,0x00,0x00,/*"׆",19*/
|
||||
0x08,0x07,0xFA,0xAA,0xAE,0xAA,0xAA,0xA8,0xAC,0xAB,0xAA,0xFE,0x0A,0x02,0x02,0x00,
|
||||
0x08,0x08,0x8B,0x6A,0x1E,0x0A,0x0A,0x0A,0x0A,0xFE,0x0A,0x0B,0x08,0x08,0x08,0x00,/*"̣",20*/
|
||||
0x10,0x60,0x01,0xC6,0x30,0x00,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x10,0x00,0x00,
|
||||
0x04,0x04,0xFE,0x01,0x00,0x41,0x61,0x51,0x4D,0x43,0x41,0x41,0x51,0xE1,0x01,0x00,/*"ר",21*/
|
||||
0x40,0x41,0xCE,0x04,0x00,0x80,0x40,0xBE,0x82,0x82,0x82,0xBE,0xC0,0x40,0x40,0x00,
|
||||
0x00,0x00,0x7F,0x20,0x90,0x80,0x40,0x43,0x2C,0x10,0x10,0x2C,0x43,0xC0,0x40,0x00,/*"ʨ",22*/
|
||||
0x20,0x21,0x2E,0xE4,0x00,0x00,0x20,0x20,0x20,0x20,0xFF,0x20,0x20,0x20,0x20,0x00,
|
||||
0x00,0x00,0x00,0x7F,0x20,0x10,0x08,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,/*"݆",23*/
|
||||
|
||||
|
||||
0x00,0x00,0xF8,0x48,0x48,0x48,0x48,0xFF,0x48,0x48,0x48,0x48,0xF8,0x00,0x00,0x00,
|
||||
0x00,0x00,0x0F,0x04,0x04,0x04,0x04,0x3F,0x44,0x44,0x44,0x44,0x4F,0x40,0x70,0x00,/*"֧",24*/
|
||||
0x00,0x00,0x02,0x02,0x02,0x02,0x02,0xE2,0x12,0x0A,0x06,0x02,0x00,0x80,0x00,0x00,
|
||||
0x01,0x01,0x01,0x01,0x01,0x41,0x81,0x7F,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,/*"ؓ",25*/
|
||||
0x00,0x20,0x20,0x22,0x22,0xE2,0x22,0x22,0x22,0xE2,0x22,0x22,0x22,0x20,0x20,0x00,
|
||||
0x00,0x40,0x20,0x10,0x0C,0x03,0x00,0x00,0x00,0x3F,0x40,0x40,0x40,0x40,0x70,0x00,/*"Ԫ",26*/
|
||||
0x40,0x20,0xF8,0x0F,0x82,0x60,0x1E,0x14,0x10,0xFF,0x10,0x10,0x10,0x10,0x00,0x00,
|
||||
0x00,0x00,0xFF,0x00,0x01,0x01,0x01,0x01,0x01,0xFF,0x01,0x01,0x01,0x01,0x01,0x00,/*"ݾ",27*/
|
||||
0x00,0x00,0x00,0x00,0x7E,0x48,0x48,0x48,0x48,0x48,0x48,0x48,0x48,0xCC,0x08,0x00,
|
||||
0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x24,0x46,0x44,0x20,0x1F,0x00,0x00,/*"ԫ",28*/
|
||||
0x84,0x94,0x94,0xFF,0x94,0x94,0x80,0x24,0x24,0x24,0xFC,0x12,0x13,0x12,0x00,0x00,
|
||||
0x20,0x18,0x06,0xFF,0x02,0x1C,0x0A,0x02,0x02,0x02,0x3F,0x41,0x41,0x41,0x71,0x00,/*"ۄ",29*/
|
||||
0x10,0x10,0xD0,0xFE,0x50,0x90,0x00,0x10,0x10,0x10,0xD0,0xFE,0x10,0x10,0x10,0x00,
|
||||
0x08,0x06,0x01,0xFF,0x00,0x01,0x10,0x08,0x04,0x43,0x80,0x7F,0x00,0x00,0x00,0x00,/*"ӄ",30*/
|
||||
0x90,0x88,0xA7,0xA2,0xA6,0xBA,0xA2,0xF8,0xA7,0xA2,0xA6,0xBA,0xA2,0x82,0x80,0x00,
|
||||
0x00,0x04,0x04,0x04,0x04,0x0C,0x34,0x04,0x44,0x84,0x7F,0x04,0x04,0x04,0x00,0x00,/*"ֈ",31*/
|
||||
};
|
||||
|
||||
/************************************6*8քֳ֣************************************/
|
||||
unsigned char F6x8[][6] =
|
||||
{
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sp
|
||||
0x00, 0x00, 0x00, 0x2f, 0x00, 0x00,// !
|
||||
0x00, 0x00, 0x07, 0x00, 0x07, 0x00,// "
|
||||
0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14,// #
|
||||
0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12,// $
|
||||
0x00, 0x62, 0x64, 0x08, 0x13, 0x23,// %
|
||||
0x00, 0x36, 0x49, 0x55, 0x22, 0x50,// &
|
||||
0x00, 0x00, 0x05, 0x03, 0x00, 0x00,// '
|
||||
0x00, 0x00, 0x1c, 0x22, 0x41, 0x00,// (
|
||||
0x00, 0x00, 0x41, 0x22, 0x1c, 0x00,// )
|
||||
0x00, 0x14, 0x08, 0x3E, 0x08, 0x14,// *
|
||||
0x00, 0x08, 0x08, 0x3E, 0x08, 0x08,// +
|
||||
0x00, 0x00, 0x00, 0xA0, 0x60, 0x00,// ,
|
||||
0x00, 0x08, 0x08, 0x08, 0x08, 0x08,// -
|
||||
0x00, 0x00, 0x60, 0x60, 0x00, 0x00,// .
|
||||
0x00, 0x20, 0x10, 0x08, 0x04, 0x02,// /
|
||||
0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
|
||||
0x00, 0x00, 0x42, 0x7F, 0x40, 0x00,// 1
|
||||
0x00, 0x42, 0x61, 0x51, 0x49, 0x46,// 2
|
||||
0x00, 0x21, 0x41, 0x45, 0x4B, 0x31,// 3
|
||||
0x00, 0x18, 0x14, 0x12, 0x7F, 0x10,// 4
|
||||
0x00, 0x27, 0x45, 0x45, 0x45, 0x39,// 5
|
||||
0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
|
||||
0x00, 0x01, 0x71, 0x09, 0x05, 0x03,// 7
|
||||
0x00, 0x36, 0x49, 0x49, 0x49, 0x36,// 8
|
||||
0x00, 0x06, 0x49, 0x49, 0x29, 0x1E,// 9
|
||||
0x00, 0x00, 0x36, 0x36, 0x00, 0x00,// :
|
||||
0x00, 0x00, 0x56, 0x36, 0x00, 0x00,// ;
|
||||
0x00, 0x08, 0x14, 0x22, 0x41, 0x00,// <
|
||||
0x00, 0x14, 0x14, 0x14, 0x14, 0x14,// =
|
||||
0x00, 0x00, 0x41, 0x22, 0x14, 0x08,// >
|
||||
0x00, 0x02, 0x01, 0x51, 0x09, 0x06,// ?
|
||||
0x00, 0x32, 0x49, 0x59, 0x51, 0x3E,// @
|
||||
0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C,// A
|
||||
0x00, 0x7F, 0x49, 0x49, 0x49, 0x36,// B
|
||||
0x00, 0x3E, 0x41, 0x41, 0x41, 0x22,// C
|
||||
0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C,// D
|
||||
0x00, 0x7F, 0x49, 0x49, 0x49, 0x41,// E
|
||||
0x00, 0x7F, 0x09, 0x09, 0x09, 0x01,// F
|
||||
0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A,// G
|
||||
0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F,// H
|
||||
0x00, 0x00, 0x41, 0x7F, 0x41, 0x00,// I
|
||||
0x00, 0x20, 0x40, 0x41, 0x3F, 0x01,// J
|
||||
0x00, 0x7F, 0x08, 0x14, 0x22, 0x41,// K
|
||||
0x00, 0x7F, 0x40, 0x40, 0x40, 0x40,// L
|
||||
0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F,// M
|
||||
0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F,// N
|
||||
0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E,// O
|
||||
0x00, 0x7F, 0x09, 0x09, 0x09, 0x06,// P
|
||||
0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
|
||||
0x00, 0x7F, 0x09, 0x19, 0x29, 0x46,// R
|
||||
0x00, 0x46, 0x49, 0x49, 0x49, 0x31,// S
|
||||
0x00, 0x01, 0x01, 0x7F, 0x01, 0x01,// T
|
||||
0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F,// U
|
||||
0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F,// V
|
||||
0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F,// W
|
||||
0x00, 0x63, 0x14, 0x08, 0x14, 0x63,// X
|
||||
0x00, 0x07, 0x08, 0x70, 0x08, 0x07,// Y
|
||||
0x00, 0x61, 0x51, 0x49, 0x45, 0x43,// Z
|
||||
0x00, 0x00, 0x7F, 0x41, 0x41, 0x00,// [
|
||||
0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55,// 55
|
||||
0x00, 0x00, 0x41, 0x41, 0x7F, 0x00,// ]
|
||||
0x00, 0x04, 0x02, 0x01, 0x02, 0x04,// ^
|
||||
0x00, 0x40, 0x40, 0x40, 0x40, 0x40,// _
|
||||
0x00, 0x00, 0x01, 0x02, 0x04, 0x00,// '
|
||||
0x00, 0x20, 0x54, 0x54, 0x54, 0x78,// a
|
||||
0x00, 0x7F, 0x48, 0x44, 0x44, 0x38,// b
|
||||
0x00, 0x38, 0x44, 0x44, 0x44, 0x20,// c
|
||||
0x00, 0x38, 0x44, 0x44, 0x48, 0x7F,// d
|
||||
0x00, 0x38, 0x54, 0x54, 0x54, 0x18,// e
|
||||
0x00, 0x08, 0x7E, 0x09, 0x01, 0x02,// f
|
||||
0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C,// g
|
||||
0x00, 0x7F, 0x08, 0x04, 0x04, 0x78,// h
|
||||
0x00, 0x00, 0x44, 0x7D, 0x40, 0x00,// i
|
||||
0x00, 0x40, 0x80, 0x84, 0x7D, 0x00,// j
|
||||
0x00, 0x7F, 0x10, 0x28, 0x44, 0x00,// k
|
||||
0x00, 0x00, 0x41, 0x7F, 0x40, 0x00,// l
|
||||
0x00, 0x7C, 0x04, 0x18, 0x04, 0x78,// m
|
||||
0x00, 0x7C, 0x08, 0x04, 0x04, 0x78,// n
|
||||
0x00, 0x38, 0x44, 0x44, 0x44, 0x38,// o
|
||||
0x00, 0xFC, 0x24, 0x24, 0x24, 0x18,// p
|
||||
0x00, 0x18, 0x24, 0x24, 0x18, 0xFC,// q
|
||||
0x00, 0x7C, 0x08, 0x04, 0x04, 0x08,// r
|
||||
0x00, 0x48, 0x54, 0x54, 0x54, 0x20,// s
|
||||
0x00, 0x04, 0x3F, 0x44, 0x40, 0x20,// t
|
||||
0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C,// u
|
||||
0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C,// v
|
||||
0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C,// w
|
||||
0x00, 0x44, 0x28, 0x10, 0x28, 0x44,// x
|
||||
0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,// y
|
||||
0x00, 0x44, 0x64, 0x54, 0x4C, 0x44,// z
|
||||
0x14, 0x14, 0x14, 0x14, 0x14, 0x14,// horiz lines
|
||||
};
|
||||
/****************************************8*16քֳ֣************************************/
|
||||
unsigned char F8X16[] = {
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
|
||||
0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
|
||||
0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
|
||||
0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
|
||||
0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
|
||||
0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
|
||||
0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
|
||||
0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
|
||||
0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
|
||||
0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
|
||||
0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
|
||||
0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
|
||||
0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
|
||||
0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
|
||||
0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
|
||||
0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
|
||||
0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
|
||||
0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
|
||||
0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
|
||||
0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
|
||||
0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
|
||||
0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
|
||||
0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
|
||||
0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
|
||||
0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
|
||||
0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
|
||||
0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
|
||||
0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
|
||||
0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
|
||||
0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
|
||||
0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
|
||||
0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
|
||||
0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
|
||||
0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
|
||||
0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
|
||||
0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
|
||||
0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
|
||||
0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
|
||||
0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
|
||||
0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
|
||||
0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
|
||||
0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
|
||||
0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
|
||||
0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
|
||||
0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
|
||||
0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
|
||||
0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
|
||||
0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
|
||||
0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
|
||||
0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
|
||||
0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
|
||||
0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
|
||||
0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
|
||||
0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
|
||||
0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
|
||||
0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
|
||||
0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
|
||||
0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
|
||||
0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
|
||||
0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
|
||||
0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
|
||||
0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
|
||||
0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
|
||||
0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
|
||||
0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
|
||||
0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
|
||||
0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
|
||||
0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
|
||||
0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
|
||||
0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
|
||||
0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
|
||||
0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
|
||||
0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
|
||||
0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
|
||||
0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
|
||||
0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
|
||||
0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
|
||||
0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
|
||||
0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
|
||||
0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
|
||||
0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
|
||||
0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
|
||||
0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
|
||||
0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
|
||||
0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
|
||||
0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
|
||||
};
|
||||
|
||||
unsigned char BMP1[] = {
|
||||
0x00,0x03,0x05,0x09,0x11,0xFF,0x11,0x89,0x05,0xC3,0x00,0xE0,0x00,0xF0,0x00,0xF8,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x28,0xFF,0x11,0xAA,0x44,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x01,0x38,0x44,0x82,0x92,
|
||||
0x92,0x74,0x01,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x44,0xFF,0x01,0x7D,
|
||||
0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x7D,0x01,0xFF,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,
|
||||
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x3F,0x03,0x03,
|
||||
0xF3,0x13,0x11,0x11,0x11,0x11,0x11,0x11,0x01,0xF1,0x11,0x61,0x81,0x01,0x01,0x01,
|
||||
0x81,0x61,0x11,0xF1,0x01,0x01,0x01,0x01,0x41,0x41,0xF1,0x01,0x01,0x01,0x01,0x01,
|
||||
0xC1,0x21,0x11,0x11,0x11,0x11,0x21,0xC1,0x01,0x01,0x01,0x01,0x41,0x41,0xF1,0x01,
|
||||
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x11,0x11,0x11,0x11,0x11,0xD3,0x33,
|
||||
0x03,0x03,0x3F,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xE0,0x00,0x00,
|
||||
0x7F,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x7F,0x00,0x00,0x01,0x06,0x18,0x06,
|
||||
0x01,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x40,0x40,0x7F,0x40,0x40,0x00,0x00,0x00,
|
||||
0x1F,0x20,0x40,0x40,0x40,0x40,0x20,0x1F,0x00,0x00,0x00,0x00,0x40,0x40,0x7F,0x40,
|
||||
0x40,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x40,0x30,0x0C,0x03,0x00,0x00,
|
||||
0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x06,
|
||||
0x06,0x06,0x04,0x04,0x04,0x84,0x44,0x44,0x44,0x84,0x04,0x04,0x84,0x44,0x44,0x44,
|
||||
0x84,0x04,0x04,0x04,0x84,0xC4,0x04,0x04,0x04,0x04,0x84,0x44,0x44,0x44,0x84,0x04,
|
||||
0x04,0x04,0x04,0x04,0x84,0x44,0x44,0x44,0x84,0x04,0x04,0x04,0x04,0x04,0x84,0x44,
|
||||
0x44,0x44,0x84,0x04,0x04,0x84,0x44,0x44,0x44,0x84,0x04,0x04,0x04,0x04,0x06,0x06,
|
||||
0x06,0x06,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x10,0x18,0x14,0x12,0x11,0x00,0x00,0x0F,0x10,0x10,0x10,
|
||||
0x0F,0x00,0x00,0x00,0x10,0x1F,0x10,0x00,0x00,0x00,0x08,0x10,0x12,0x12,0x0D,0x00,
|
||||
0x00,0x18,0x00,0x00,0x0D,0x12,0x12,0x12,0x0D,0x00,0x00,0x18,0x00,0x00,0x10,0x18,
|
||||
0x14,0x12,0x11,0x00,0x00,0x10,0x18,0x14,0x12,0x11,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,
|
||||
0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x7F,0x03,0x0C,0x30,0x0C,0x03,0x7F,0x00,0x00,0x38,0x54,0x54,0x58,0x00,0x00,
|
||||
0x7C,0x04,0x04,0x78,0x00,0x00,0x3C,0x40,0x40,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xAA,0xAA,0xAA,
|
||||
0x28,0x08,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x03,0x0C,0x30,0x0C,0x03,0x7F,
|
||||
0x00,0x00,0x26,0x49,0x49,0x49,0x32,0x00,0x00,0x7F,0x02,0x04,0x08,0x10,0x7F,0x00,/*"D:\ٲЭ\show1.bmp",0*/
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
|
||||
#include "NUC100Series.h"
|
||||
#include <stdio.h>
|
||||
|
||||
int OLED_WriteReg( char RegAddr, char pucDATD_AA)
|
||||
{
|
||||
int i=0;
|
||||
|
||||
while(i<32) i++;
|
||||
|
||||
I2C_START(I2C0); //Æô¶¯
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x08)
|
||||
{
|
||||
printf("I2CD_STArt write fail,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
//½øÈë¶Áд¿ØÖƲÙ×÷
|
||||
I2C_SET_DATA(I2C0,0xd0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0)!= 0x18)
|
||||
{
|
||||
printf("I2C write ADW fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
//дÈë¶ÁµØÖ·
|
||||
I2C_SET_DATA(I2C0,RegAddr);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x28)
|
||||
{
|
||||
printf("I2C write reg addr fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
//дÈëÊý¾Ý
|
||||
I2C_SET_DATA(I2C0,pucDATD_AA);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x28)
|
||||
{
|
||||
printf("I2C write control fail\r\n");
|
||||
while (1);
|
||||
}
|
||||
|
||||
//Í£Ö¹
|
||||
I2C_Trigger(I2C0,0,1,1,0);
|
||||
|
||||
|
||||
//printf("I2C write ok\r\n");
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
int OLED_WriteAddr()
|
||||
{
|
||||
if (I2C_GET_STATUS(I2C0) != 0x08)
|
||||
{
|
||||
printf("I2CD_STArt write add fail,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
//½øÈë¶Áд¿ØÖƲÙ×÷
|
||||
I2C_SET_DATA(I2C0,0xd0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0)!= 0x18)
|
||||
{
|
||||
printf("I2C write ADW fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int OLED_WriteACK(char cDat)
|
||||
{
|
||||
if((I2C_GET_STATUS(I2C0) != 0x18)&&(I2C_GET_STATUS(I2C0) != 0x28))
|
||||
{
|
||||
printf("I2C OLED_WriteAddrAck STATUS error \r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
//дÈë¶ÁµØÖ·
|
||||
I2C_SET_DATA(I2C0,cDat);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0)!= 0x28)
|
||||
{
|
||||
printf("OLED_WriteAddrAck fail ACK no recv\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
char OLED_ReadReg( int unAddr/*, int unLength*/)
|
||||
{
|
||||
char ret;
|
||||
int i=0;
|
||||
|
||||
while(i<32) i++;
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
|
||||
I2C_START(I2C0); //Æô¶¯
|
||||
//Æô¶¯
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if(I2C_GET_STATUS(I2C0) != 0x08)
|
||||
{
|
||||
printf("I2CD_STArt read reg fail,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
|
||||
//½øÈë¶Áд¿ØÖƲÙ×÷
|
||||
I2C_SET_DATA(I2C0,0xd0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x018)
|
||||
{
|
||||
printf("status fault shoube be 0x018 ,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
//дÈë¶ÁµØÖ·
|
||||
I2C_SET_DATA(I2C0,unAddr);
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0)!= 0x28)
|
||||
{
|
||||
printf("I2C write reg addr fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// ÖØÐÂÆô¶¯
|
||||
|
||||
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_Trigger(I2C0,1,0,0,0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x10)
|
||||
{
|
||||
printf("I2C repeated D_STArt fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
|
||||
//½øÈë¶Á²Ù×÷
|
||||
I2C_SET_DATA(I2C0,0xd0 | 1);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x40)
|
||||
{
|
||||
printf("I2C write control fail\r\n");
|
||||
while (1);
|
||||
}
|
||||
//¶ÁÈ¡Êý¾Ý
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x58)
|
||||
{
|
||||
printf("I2C read fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
ret = I2C_GET_DATA(I2C0);
|
||||
I2C_Trigger(I2C0,0,1,1,0);
|
||||
|
||||
// I2C_WAIT_READY(I2C0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int OLED_ReadBuf( int unAddr, char *pucDATD_AA, int unLength)
|
||||
{
|
||||
char ret;
|
||||
int i=0;
|
||||
while(i<32) i++;
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_START(I2C0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if(I2C_GET_STATUS(I2C0) != 0x08)
|
||||
{
|
||||
printf("I2CD_STArt fail,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
|
||||
I2C_SET_DATA(I2C0,0xd0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x18)
|
||||
{
|
||||
printf("I2CD_STArt fail,I2D_STATUS %02X\r\n",I2C_GET_STATUS(I2C0));
|
||||
return FALSE;
|
||||
}
|
||||
I2C_SET_DATA(I2C0,unAddr);
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0)!= 0x28)
|
||||
{
|
||||
printf("I2C write reg addr fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_Trigger(I2C0,1,0,0,0);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x10)
|
||||
{
|
||||
printf("I2C repeated D_STArt fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
I2C_SET_DATA(I2C0,0xd0 | 1);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if (I2C_GET_STATUS(I2C0) != 0x40)
|
||||
{
|
||||
printf("I2C write control fail\r\n");
|
||||
while (1);
|
||||
}
|
||||
for(i=0;i<unLength;i++)
|
||||
{
|
||||
if(i==unLength-1)
|
||||
I2C_Trigger(I2C0,0,0,1,0);
|
||||
else
|
||||
I2C_Trigger(I2C0,0,0,1,1);
|
||||
I2C_WAIT_READY(I2C0);
|
||||
if ((I2C_GET_STATUS(I2C0) != 0x58)&&(I2C_GET_STATUS(I2C0) != 0x50))
|
||||
{
|
||||
printf("I2C read fail\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
pucDATD_AA[i] = I2C_GET_DATA(I2C0);
|
||||
}
|
||||
I2C_Trigger(I2C0,0,1,1,0);
|
||||
|
||||
// I2C_WAIT_READY(I2C0);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
#include "M451Series.h"
|
||||
#include "ssd1306.h"
|
||||
|
||||
|
||||
#define PLL_CLOCK 72000000
|
||||
|
||||
void HalInit(){
|
||||
SYS_UnlockReg();
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Init System Clock */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/* Enable Internal RC 22.1184MHz clock */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
|
||||
|
||||
/* Waiting for Internal RC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
|
||||
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
|
||||
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
|
||||
|
||||
/* Enable external XTAL 12MHz clock */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
|
||||
|
||||
/* Waiting for external XTAL clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||
|
||||
/* Set core clock as PLL_CLOCK from PLL */
|
||||
CLK_SetCoreClock(PLL_CLOCK);
|
||||
|
||||
/* Enable UART module clock */
|
||||
|
||||
/* Enable I2C0 module clock */
|
||||
CLK_EnableModuleClock(I2C0_MODULE);
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Init I/O Multi-function */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
SYS->GPD_MFPL &= ~SYS_GPD_MFPL_PD4MFP_Msk;
|
||||
SYS->GPD_MFPL |= SYS_GPD_MFPL_PD4MFP_I2C0_SDA;
|
||||
|
||||
SYS->GPD_MFPL &= ~SYS_GPD_MFPL_PD5MFP_Msk;
|
||||
SYS->GPD_MFPL |= SYS_GPD_MFPL_PD5MFP_I2C0_SCL;
|
||||
I2C_Open(I2C0,100000);
|
||||
|
||||
printf("I2C clock %d Hz\n", I2C_GetBusClockFreq(I2C0));
|
||||
|
||||
I2C_SetSlaveAddr(I2C0, 0, 0x78, 0); /* Slave Address : 0x15 */
|
||||
|
||||
SYS_LockReg();
|
||||
|
||||
//GPIO_SetMode(PB,BIT14,GPIO_PMD_INPUT);
|
||||
//GPIO_SetMode(PB,BIT9,GPIO_PMD_OUTPUT);
|
||||
|
||||
//I2C_EnableInt(I2C0);
|
||||
//NVIC_EnableIRQ(I2C0_IRQn);
|
||||
}
|
||||
|
||||
typedef void (*I2C_FUNC)(uint32_t u32Status);
|
||||
static I2C_FUNC s_I2CHandlerFn = NULL;
|
||||
volatile int muxI2C = 0;
|
||||
uint8_t g_au8TxData[3];
|
||||
uint8_t g_u8DeviceAddr = 0x50;
|
||||
uint8_t g_u8DataLen;
|
||||
volatile uint8_t g_u8EndFlag = 0;
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* I2C Tx Callback Function */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void I2C_MasterTx(uint32_t u32Status)
|
||||
{
|
||||
if(u32Status == 0x08) /* START has been transmitted */
|
||||
{
|
||||
I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1); /* Write SLA+W to Register I2CDAT */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
|
||||
}
|
||||
else if(u32Status == 0x18) /* SLA+W has been transmitted and ACK has been received */
|
||||
{
|
||||
I2C_SET_DATA(I2C0, g_au8TxData[g_u8DataLen++]);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
|
||||
}
|
||||
else if(u32Status == 0x20) /* SLA+W has been transmitted and NACK has been received */
|
||||
{
|
||||
I2C_STOP(I2C0);
|
||||
I2C_START(I2C0);
|
||||
}
|
||||
else if(u32Status == 0x28) /* DATA has been transmitted and ACK has been received */
|
||||
{
|
||||
if(g_u8DataLen != 3)
|
||||
{
|
||||
I2C_SET_DATA(I2C0, g_au8TxData[g_u8DataLen++]);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_CTL_SI);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_CTL_STO_SI);
|
||||
g_u8EndFlag = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* TO DO */
|
||||
printf("Status 0x%x is NOT processed\n", u32Status);
|
||||
}
|
||||
}
|
||||
|
||||
void I2C0_IRQHandler(void)
|
||||
{
|
||||
uint32_t u32Status;
|
||||
|
||||
u32Status = I2C_GET_STATUS(I2C0);
|
||||
|
||||
if(I2C_GET_TIMEOUT_FLAG(I2C0))
|
||||
{
|
||||
/* Clear I2C0 Timeout Flag */
|
||||
I2C_ClearTimeoutFlag(I2C0);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(s_I2CHandlerFn != NULL)
|
||||
s_I2CHandlerFn(u32Status);
|
||||
}
|
||||
}
|
||||
|
||||
int main(){
|
||||
HalInit();
|
||||
Init_LCD();
|
||||
clear_LCD();
|
||||
|
||||
print_Line(0, "NuTiny - Nano102");
|
||||
print_Line(1, "Cortex-M0 @32MHz");
|
||||
print_Line(2, "Ultra Low Power ");
|
||||
print_Line(3, "0.96 OLED 128x64");
|
||||
|
||||
print_C(0, 0, 'N');
|
||||
print_C(0, 1, 'C');
|
||||
print_C(0, 2, 'U');
|
||||
print_C(0, 3, ' ');
|
||||
while(1){
|
||||
print_C(0, 2, 'U');
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
//
|
||||
// LCD Driver: 0.96" OLED
|
||||
//
|
||||
// Interface: I2C
|
||||
// pin1: Gnd
|
||||
// pin2: Vcc
|
||||
// pin3: SCL
|
||||
// pin4: SDA
|
||||
// pin5: OUT
|
||||
// pin6: IN
|
||||
// pin7: SCK
|
||||
// pin8: CS
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <M451Series.h>
|
||||
#include "sys.h"
|
||||
#include "gpio.h"
|
||||
#include "i2c.h"
|
||||
#include "ssd1306.h"
|
||||
#include "codetab.h"
|
||||
|
||||
void OLED_SingleWrite(uint8_t index, uint8_t data)
|
||||
{
|
||||
I2C_START(LCD_I2C_PORT); //Start
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, LCD_I2C_SLA); //send slave address
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, index); //send index
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, data); //send Data
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI|I2C_CTL_STO);//Stop
|
||||
}
|
||||
|
||||
uint8_t OLED_SingleRead(uint8_t index)
|
||||
{
|
||||
uint8_t tmp;
|
||||
I2C_START(LCD_I2C_PORT); //Start
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, LCD_I2C_SLA); //send slave address+W
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, index); //send index
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_STA | I2C_CTL_SI); //Start
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_DATA(LCD_I2C_PORT, (LCD_I2C_SLA+1)); //send slave address+R
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI);
|
||||
I2C_WAIT_READY(LCD_I2C_PORT);
|
||||
//LCD_I2C_PORT->INTSTS |= I2C_INTSTS_INTSTS_Msk; //clear flag
|
||||
tmp = I2C_GET_DATA(LCD_I2C_PORT); //read data
|
||||
|
||||
I2C_SET_CONTROL_REG(LCD_I2C_PORT, I2C_CTL_SI|I2C_CTL_STO);//Stop
|
||||
return tmp;
|
||||
}
|
||||
|
||||
void oledWriteCommand(unsigned char OLED_Command)
|
||||
{
|
||||
OLED_SingleWrite(0x00, OLED_Command);
|
||||
}
|
||||
|
||||
void oledWriteData(unsigned char OLED_Data)
|
||||
{
|
||||
OLED_SingleWrite(0x40, OLED_Data);
|
||||
}
|
||||
|
||||
void Init_LCD(void)
|
||||
{
|
||||
oledWriteCommand(0xae); //display off
|
||||
oledWriteCommand(0x20); //Set Memory Addressing Mode
|
||||
oledWriteCommand(0x10); //00,Horizontal Addressing Mode;01,Vertical Addressing Mode;10,Page Addressing Mode (RESET);11,Invalid
|
||||
oledWriteCommand(0xb0); //Set Page Start Address for Page Addressing Mode,0-7
|
||||
oledWriteCommand(0xc8); //Set COM Output Scan Direction
|
||||
oledWriteCommand(0x00);//---set low column address
|
||||
oledWriteCommand(0x10);//---set high column address
|
||||
oledWriteCommand(0x40);//--set start line address
|
||||
oledWriteCommand(0x81);//--set contrast control register
|
||||
oledWriteCommand(0x7f);
|
||||
oledWriteCommand(0xa1);//--set segment re-map 0 to 127
|
||||
oledWriteCommand(0xa6);//--set normal display
|
||||
oledWriteCommand(0xa8);//--set multiplex ratio(1 to 64)
|
||||
oledWriteCommand(0x3F);//
|
||||
oledWriteCommand(0xa4);//0xa4,Output follows RAM content;0xa5,Output ignores RAM content
|
||||
oledWriteCommand(0xd3);//-set display offset
|
||||
oledWriteCommand(0x00);//-not offset
|
||||
oledWriteCommand(0xd5);//--set display clock divide ratio/oscillator frequency
|
||||
oledWriteCommand(0xf0);//--set divide ratio
|
||||
oledWriteCommand(0xd9);//--set pre-charge period
|
||||
oledWriteCommand(0x22); //
|
||||
oledWriteCommand(0xda);//--set com pins hardware configuration
|
||||
oledWriteCommand(0x12);
|
||||
oledWriteCommand(0xdb);//--set vcomh
|
||||
oledWriteCommand(0x20);//0x20,0.77xVcc
|
||||
oledWriteCommand(0x8d);//--set DC-DC enable
|
||||
oledWriteCommand(0x14);//
|
||||
oledWriteCommand(0xaf);//--turn on oled panel
|
||||
}
|
||||
|
||||
void oled_address(uint8_t column, uint8_t page)
|
||||
{
|
||||
oledWriteCommand(0xb0+page); // set page address
|
||||
oledWriteCommand(0x10 | ((column & 0xf0) >> 4)); // set column address MSB
|
||||
oledWriteCommand(0x00 | (column & 0x0f) ); // set column address LSB
|
||||
}
|
||||
|
||||
void clear_LCD(void)
|
||||
{
|
||||
int16_t x, Y;
|
||||
for (Y=0;Y<LCD_Ymax/8;Y++)
|
||||
{
|
||||
oled_address(0, Y);
|
||||
for (x=0;x<LCD_Xmax;x++)
|
||||
oledWriteData(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
void draw_LCD(unsigned char *buffer)
|
||||
{
|
||||
int16_t x, Y;
|
||||
for (Y=0;Y<8;Y++)
|
||||
{
|
||||
oled_address(0, Y);
|
||||
for (x=0;x<LCD_Xmax;x++)
|
||||
oledWriteData(buffer[x+Y*LCD_Xmax]);
|
||||
}
|
||||
}
|
||||
|
||||
void print_C(uint8_t Col, uint8_t Line, char ascii)
|
||||
{
|
||||
uint8_t j, i, tmp;
|
||||
for (j=0;j<2;j++) {
|
||||
oled_address(Col*8, Line*2+j);
|
||||
for (i=0;i<8;i++) {
|
||||
tmp=F8X16[(ascii-0x20)*16+j*8+i];
|
||||
oledWriteData(tmp);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void print_Line(uint8_t Line, char Text[])
|
||||
{
|
||||
uint8_t Col;
|
||||
for (Col=0; Col<strlen(Text); Col++)
|
||||
print_C(Col, Line, Text[Col]);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
//
|
||||
// LY096BG30 : 0.96" OLED
|
||||
//
|
||||
#ifndef __SSD_1306__
|
||||
#define __SSD_1306__
|
||||
#define LCD_I2C_SLA 0x78
|
||||
#define LCD_I2C_PORT I2C0
|
||||
|
||||
#define LCD_Xmax 128
|
||||
#define LCD_Ymax 64
|
||||
|
||||
extern void Init_LCD(void);
|
||||
extern void clear_LCD(void);
|
||||
extern void print_LCD(unsigned char *buffer);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue