141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
/****************************************************************************
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* @file MyProject.c
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* @version V1.06
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* @Date 2021/07/31-20:56:23
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* @brief NuMicro generated code file
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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/********************
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MCU:NUC120RC1DN(LQFP64)
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Base Clocks:
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HIRC:22.1184MHz
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HCLK:22.1184MHz
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PCLK:22.1184MHz
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Enabled-Module Frequencies:
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EBI=Bus Clock(HCLK):22.1184MHz
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I2S=Bus Clock(PCLK):22.1184MHz/Engine Clock:22.1184MHz
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ISP=Bus Clock(HCLK):22.1184MHz/Engine Clock:22.1184MHz
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SYSTICK=Bus Clock(HCLK):22.1184MHz/Engine Clock:11.0592MHz
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********************/
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#include "NUC100Series.h"
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void MyProject_init_ebi(void)
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{
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CLK_EnableModuleClock(EBI_MODULE);
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return;
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}
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void MyProject_deinit_ebi(void)
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{
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CLK_DisableModuleClock(EBI_MODULE);
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return;
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}
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void MyProject_init_i2s(void)
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{
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CLK_EnableModuleClock(I2S_MODULE);
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CLK_SetModuleClock(I2S_MODULE, CLK_CLKSEL2_I2S_S_HCLK, MODULE_NoMsk);
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return;
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}
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void MyProject_deinit_i2s(void)
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{
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CLK_DisableModuleClock(I2S_MODULE);
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return;
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}
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void MyProject_init_isp(void)
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{
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CLK_EnableModuleClock(ISP_MODULE);
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return;
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}
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void MyProject_deinit_isp(void)
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{
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CLK_DisableModuleClock(ISP_MODULE);
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return;
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}
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void MyProject_init_systick(void)
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{
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CLK_EnableSysTick(CLK_CLKSEL0_STCLK_S_HIRC_DIV2, 0);
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return;
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}
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void MyProject_deinit_systick(void)
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{
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CLK_DisableSysTick();
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return;
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}
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void MyProject_init_base(void)
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{
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/* If the macros do not exist in your project, please refer to the related clk.h in Header folder of the tool package */
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/* Enable clock source */
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CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
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/* Waiting for clock source ready */
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CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
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/* Set HCLK clock */
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CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
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return;
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}
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void MyProject_init(void)
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{
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init System Clock */
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/*---------------------------------------------------------------------------------------------------------*/
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//CLK->PWRCON = (CLK->PWRCON & ~(0x0000000FUL)) | 0x00000014UL;
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//CLK->PLLCON = (CLK->PLLCON & ~(0x000FFFFFUL)) | 0x0005C22EUL;
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//CLK->CLKDIV = (CLK->CLKDIV & ~(0x00FF0FFFUL)) | 0x00000000UL;
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//CLK->CLKDIV1 = (CLK->CLKDIV1 & ~(0x00FFFFFFUL)) | 0x00000000UL;
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//CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(0x0000003FUL)) | 0x0000003FUL;
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//CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(0xF37777FFUL)) | 0xFFFFFFFFUL;
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//CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(0x00030FFFUL)) | 0x000200FEUL;
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//CLK->CLKSEL3 = (CLK->CLKSEL3 & ~(0x0000003FUL)) | 0x0000003FUL;
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//CLK->AHBCLK = (CLK->AHBCLK & ~(0x0000000EUL)) | 0x0000000DUL;
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//CLK->APBCLK = (CLK->APBCLK & ~(0xF8F7F37FUL)) | 0x20000000UL;
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//CLK->APBCLK1 = (CLK->APBCLK1 & ~(0x00000007UL)) | 0x00000000UL;
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//CLK->FRQDIV = (CLK->FRQDIV & ~(0x0000001FUL)) | 0x00000000UL;
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//SysTick->CTRL = (SysTick->CTRL & ~(0x00000005UL)) | 0x00000001UL;
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/* Unlock protected registers */
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SYS_UnlockReg();
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/* Enable base clock */
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MyProject_init_base();
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/* Enable module clock and set clock source */
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MyProject_init_ebi();
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MyProject_init_i2s();
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MyProject_init_isp();
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MyProject_init_systick();
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/* Update System Core Clock */
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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return;
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}
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/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/
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