26108 lines
1003 KiB
Plaintext
26108 lines
1003 KiB
Plaintext
|
!SESSION 2022-11-24 17:06:15.530 -----------------------------------------------
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eclipse.buildId=2018.3
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java.version=1.8.0_112
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java.vendor=Oracle Corporation
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BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=zh_CN
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Command-line arguments: -os win32 -ws win32 -arch x86_64 -data L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk
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This is a continuation of log file L:\PersonalProjects\Xilinx\SpectrumAnalyzer_FFT_windows\SpectrumAnalyzer_FFT_windows.sdk\.metadata\.bak_0.log
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Created Time: 2022-11-24 17:18:30.462
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!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.462
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!MESSAGE Error
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!STACK 0
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java.lang.NullPointerException
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at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
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at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
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at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
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|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
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at java.io.OutputStream.write(OutputStream.java:75)
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|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
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!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.465
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|
!MESSAGE Error
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|
!STACK 0
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|
java.lang.NullPointerException
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|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
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|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
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|||
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|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
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|||
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|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
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|||
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|
at java.io.OutputStream.write(OutputStream.java:75)
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|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
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|||
|
|
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|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.512
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|||
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|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
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|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
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|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
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|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
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|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
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|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
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|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.514
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
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|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
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|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
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|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.566
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.569
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.619
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.621
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.672
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.674
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.730
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.732
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.786
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.788
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.979
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:30.981
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.034
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.036
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.089
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.091
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.142
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.145
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.192
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.194
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.238
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.241
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:31.269
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.000
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.040
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.043
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.070
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.828
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.830
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.860
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.968
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.971
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:32.999
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.020
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.022
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.051
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.087
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.089
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.119
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.726
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.729
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:33.758
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:34.378
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:34.380
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:34.411
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.106
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.108
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.137
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.637
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.640
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:35.670
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:36.348
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:36.352
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:36.387
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.006
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.009
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.037
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.384
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.386
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.416
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.745
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.747
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:37.777
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.457
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.459
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.508
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.555
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.556
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.556
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:38.557
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:39.960
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:39.961
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:39.961
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:39.961
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.212
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.212
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.213
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.213
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.715
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.716
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.716
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:40.717
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:41.465
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:41.469
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:41.500
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.207
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.210
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.236
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.958
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.962
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:42.990
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:43.666
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:43.669
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:43.698
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:44.791
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:44.794
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:44.835
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:44.891
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.closeConsoleOutputStream(ConsoleOutputSniffer.java:160)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.close(ConsoleOutputSniffer.java:68)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.close(ProcessClosure.java:98)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure.isAlive(ProcessClosure.java:193)
|
|||
|
|
at org.eclipse.cdt.core.CommandLauncher.waitAndRead(CommandLauncher.java:259)
|
|||
|
|
at org.eclipse.cdt.internal.core.BuildRunnerHelper.build(BuildRunnerHelper.java:273)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.invokeMake(MakeBuilder.java:219)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.build(MakeBuilder.java:108)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:735)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:206)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:246)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:301)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:304)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuildLoop(BuildManager.java:360)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:383)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.doBuild(AutoBuildJob.java:144)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.run(AutoBuildJob.java:235)
|
|||
|
|
at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.353
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.core.CommandLauncher.printCommandLine(CommandLauncher.java:287)
|
|||
|
|
at org.eclipse.cdt.core.CommandLauncher.waitAndRead(CommandLauncher.java:250)
|
|||
|
|
at org.eclipse.cdt.internal.core.BuildRunnerHelper.build(BuildRunnerHelper.java:273)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.invokeMake(MakeBuilder.java:219)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.build(MakeBuilder.java:108)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:735)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:206)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:246)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:301)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:304)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuildLoop(BuildManager.java:360)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:383)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.doBuild(AutoBuildJob.java:144)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.run(AutoBuildJob.java:235)
|
|||
|
|
at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.388
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.390
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.469
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.471
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.528
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.530
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.572
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.574
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.612
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.614
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.654
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.656
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.706
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.709
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.760
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.763
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.807
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.809
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.855
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.857
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.910
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.912
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.964
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:47.966
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.018
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.020
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.064
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.066
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.117
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.119
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.296
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.298
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.348
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.350
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.411
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.413
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.462
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.464
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.512
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.514
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:48.538
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.187
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.225
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.228
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.252
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.995
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:49.997
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.023
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.126
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.128
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.152
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.169
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.171
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.199
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.232
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.235
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.262
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.836
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.839
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:50.867
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:51.448
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:51.450
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:51.478
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.146
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.149
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.174
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.656
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.659
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:52.685
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:53.347
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:53.349
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:53.382
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:53.971
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:53.974
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.000
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.328
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.331
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.357
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.690
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.692
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:54.718
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.381
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.384
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.438
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.484
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.485
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.486
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:55.486
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:56.830
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:56.831
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:56.831
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:56.831
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.082
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.082
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.082
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.082
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.541
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.541
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.542
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:57.542
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:58.247
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:58.250
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:58.276
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:58.997
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:59.000
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:59.023
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:59.753
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:59.756
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:18:59.785
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:19:00.450
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:19:00.452
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:19:00.483
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:19:01.828
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.processLine(ConsoleOutputSniffer.java:178)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.access$0(ConsoleOutputSniffer.java:174)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.checkLine(ConsoleOutputSniffer.java:99)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.write(ConsoleOutputSniffer.java:58)
|
|||
|
|
at java.io.OutputStream.write(OutputStream.java:75)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.run(ProcessClosure.java:57)
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.cdt.core 4 0 2022-11-24 17:19:01.864
|
|||
|
|
!MESSAGE Error
|
|||
|
|
!STACK 0
|
|||
|
|
java.lang.NullPointerException
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer.closeConsoleOutputStream(ConsoleOutputSniffer.java:160)
|
|||
|
|
at org.eclipse.cdt.internal.core.ConsoleOutputSniffer$ConsoleOutputStream.close(ConsoleOutputSniffer.java:68)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure$ReaderThread.close(ProcessClosure.java:98)
|
|||
|
|
at org.eclipse.cdt.internal.core.ProcessClosure.isAlive(ProcessClosure.java:193)
|
|||
|
|
at org.eclipse.cdt.core.CommandLauncher.waitAndRead(CommandLauncher.java:259)
|
|||
|
|
at org.eclipse.cdt.internal.core.BuildRunnerHelper.build(BuildRunnerHelper.java:273)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.invokeMake(MakeBuilder.java:219)
|
|||
|
|
at org.eclipse.cdt.make.core.MakeBuilder.build(MakeBuilder.java:108)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:735)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:206)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:246)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:301)
|
|||
|
|
at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:304)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.basicBuildLoop(BuildManager.java:360)
|
|||
|
|
at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:383)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.doBuild(AutoBuildJob.java:144)
|
|||
|
|
at org.eclipse.core.internal.events.AutoBuildJob.run(AutoBuildJob.java:235)
|
|||
|
|
at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.310
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.313
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"device": "7z035",
|
|||
|
|
"family": "zynq",
|
|||
|
|
"timestamp": "Thu Nov 24 17:05:01 2022",
|
|||
|
|
"vivado_version": "2018.3",
|
|||
|
|
"part": "xc7z035ffg676-2",
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 1 0 2022-11-24 17:19:59.385
|
|||
|
|
!MESSAGE Updating toolusage
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.387
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.392
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"PCW_APU_PERIPHERAL_FREQMHZ": "666.666666",
|
|||
|
|
"PCW_DDR_HPRLPR_QUEUE_PARTITION": "HPR(0)/LPR(32)",
|
|||
|
|
"PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": "15",
|
|||
|
|
"PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_DDR_PORT0_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT1_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT2_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT3_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_FPGA0_PERIPHERAL_FREQMHZ": "100",
|
|||
|
|
"PCW_UIPARAM_DDR_BUS_WIDTH": "32 Bit",
|
|||
|
|
"PCW_UIPARAM_DDR_FREQ_MHZ": "533.333333",
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.392
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.432
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.440
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.451
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0_S_AXI_LITE": {"name": "axi_dma_0",
|
|||
|
|
"base": "0x40400000",
|
|||
|
|
"high": "0x4040FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0_S_AXI": {"name": "axi_gpio_0",
|
|||
|
|
"base": "0x41200000",
|
|||
|
|
"high": "0x4120FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1_S_AXI": {"name": "axi_gpio_1",
|
|||
|
|
"base": "0x41210000",
|
|||
|
|
"high": "0x4121FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0_S_AXI_LITE": {"name": "axi_vdma_0",
|
|||
|
|
"base": "0x43000000",
|
|||
|
|
"high": "0x4300FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0_s00_axi": {"name": "axi_dynclk_0",
|
|||
|
|
"base": "0x43C00000",
|
|||
|
|
"high": "0x43C0FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "s00_axi",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"v_tc_0_ctrl": {"name": "v_tc_0",
|
|||
|
|
"base": "0x43C10000",
|
|||
|
|
"high": "0x43C1FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "ctrl",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"name": "ps7_afi_0",
|
|||
|
|
"base": "0xF8008000",
|
|||
|
|
"high": "0xF8008FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"name": "ps7_afi_1",
|
|||
|
|
"base": "0xF8009000",
|
|||
|
|
"high": "0xF8009FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"name": "ps7_afi_2",
|
|||
|
|
"base": "0xF800A000",
|
|||
|
|
"high": "0xF800AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"name": "ps7_afi_3",
|
|||
|
|
"base": "0xF800B000",
|
|||
|
|
"high": "0xF800BFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"name": "ps7_coresight_comp_0",
|
|||
|
|
"base": "0xF8800000",
|
|||
|
|
"high": "0xF88FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"name": "ps7_ddrc_0",
|
|||
|
|
"base": "0xF8006000",
|
|||
|
|
"high": "0xF8006FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"name": "ps7_dev_cfg_0",
|
|||
|
|
"base": "0xF8007000",
|
|||
|
|
"high": "0xF80070FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"name": "ps7_dma_ns",
|
|||
|
|
"base": "0xF8004000",
|
|||
|
|
"high": "0xF8004FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"name": "ps7_dma_s",
|
|||
|
|
"base": "0xF8003000",
|
|||
|
|
"high": "0xF8003FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"name": "ps7_globaltimer_0",
|
|||
|
|
"base": "0xF8F00200",
|
|||
|
|
"high": "0xF8F002FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"name": "ps7_gpio_0",
|
|||
|
|
"base": "0xE000A000",
|
|||
|
|
"high": "0xE000AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"name": "ps7_gpv_0",
|
|||
|
|
"base": "0xF8900000",
|
|||
|
|
"high": "0xF89FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"name": "ps7_intc_dist_0",
|
|||
|
|
"base": "0xF8F01000",
|
|||
|
|
"high": "0xF8F01FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"name": "ps7_iop_bus_config_0",
|
|||
|
|
"base": "0xE0200000",
|
|||
|
|
"high": "0xE0200FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"name": "ps7_l2cachec_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"name": "ps7_ocmc_0",
|
|||
|
|
"base": "0xF800C000",
|
|||
|
|
"high": "0xF800CFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"name": "ps7_pl310_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"name": "ps7_pmu_0",
|
|||
|
|
"base": "0xF8893000",
|
|||
|
|
"high": "0xF8893FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"name": "ps7_qspi_0",
|
|||
|
|
"base": "0xE000D000",
|
|||
|
|
"high": "0xE000DFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"name": "ps7_qspi_linear_0",
|
|||
|
|
"base": "0xFC000000",
|
|||
|
|
"high": "0xFCFFFFFF",
|
|||
|
|
"size": "16777216",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "FLASH",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"name": "ps7_scuc_0",
|
|||
|
|
"base": "0xF8F00000",
|
|||
|
|
"high": "0xF8F000FC",
|
|||
|
|
"size": "253",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"name": "ps7_scugic_0",
|
|||
|
|
"base": "0xF8F00100",
|
|||
|
|
"high": "0xF8F001FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"name": "ps7_scutimer_0",
|
|||
|
|
"base": "0xF8F00600",
|
|||
|
|
"high": "0xF8F0061F",
|
|||
|
|
"size": "32",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"name": "ps7_scuwdt_0",
|
|||
|
|
"base": "0xF8F00620",
|
|||
|
|
"high": "0xF8F006FF",
|
|||
|
|
"size": "224",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"name": "ps7_sd_0",
|
|||
|
|
"base": "0xE0100000",
|
|||
|
|
"high": "0xE0100FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"name": "ps7_slcr_0",
|
|||
|
|
"base": "0xF8000000",
|
|||
|
|
"high": "0xF8000FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"name": "ps7_uart_1",
|
|||
|
|
"base": "0xE0001000",
|
|||
|
|
"high": "0xE0001FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"name": "ps7_xadc_0",
|
|||
|
|
"base": "0xF8007100",
|
|||
|
|
"high": "0xF8007120",
|
|||
|
|
"size": "33",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"name": "ps7_ddr_0",
|
|||
|
|
"base": "0x00100000",
|
|||
|
|
"high": "0x3FFFFFFF",
|
|||
|
|
"size": "1072693248",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"name": "ps7_ram_0",
|
|||
|
|
"base": "0x00000000",
|
|||
|
|
"high": "0x0002FFFF",
|
|||
|
|
"size": "196608",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"name": "ps7_ram_1",
|
|||
|
|
"base": "0xFFFF0000",
|
|||
|
|
"high": "0xFFFFFDFF",
|
|||
|
|
"size": "65024",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.453
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.455
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.455
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.457
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.457
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.458
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.459
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.478
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.479
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.480
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.481
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.483
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Result: [null, 666666687]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.483
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.486
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"ps7_cortexa9_0": {"bscan": "",
|
|||
|
|
"index": "0",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"bscan": "",
|
|||
|
|
"index": "1",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.487
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.527
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.532
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.540
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Result: [null, {"axi_dma_0_S_AXI_LITE": {"name": "axi_dma_0",
|
|||
|
|
"base": "0x40400000",
|
|||
|
|
"high": "0x4040FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0_S_AXI": {"name": "axi_gpio_0",
|
|||
|
|
"base": "0x41200000",
|
|||
|
|
"high": "0x4120FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1_S_AXI": {"name": "axi_gpio_1",
|
|||
|
|
"base": "0x41210000",
|
|||
|
|
"high": "0x4121FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0_S_AXI_LITE": {"name": "axi_vdma_0",
|
|||
|
|
"base": "0x43000000",
|
|||
|
|
"high": "0x4300FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0_s00_axi": {"name": "axi_dynclk_0",
|
|||
|
|
"base": "0x43C00000",
|
|||
|
|
"high": "0x43C0FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "s00_axi",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"v_tc_0_ctrl": {"name": "v_tc_0",
|
|||
|
|
"base": "0x43C10000",
|
|||
|
|
"high": "0x43C1FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "ctrl",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"name": "ps7_afi_0",
|
|||
|
|
"base": "0xF8008000",
|
|||
|
|
"high": "0xF8008FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"name": "ps7_afi_1",
|
|||
|
|
"base": "0xF8009000",
|
|||
|
|
"high": "0xF8009FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"name": "ps7_afi_2",
|
|||
|
|
"base": "0xF800A000",
|
|||
|
|
"high": "0xF800AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"name": "ps7_afi_3",
|
|||
|
|
"base": "0xF800B000",
|
|||
|
|
"high": "0xF800BFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"name": "ps7_coresight_comp_0",
|
|||
|
|
"base": "0xF8800000",
|
|||
|
|
"high": "0xF88FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"name": "ps7_ddrc_0",
|
|||
|
|
"base": "0xF8006000",
|
|||
|
|
"high": "0xF8006FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"name": "ps7_dev_cfg_0",
|
|||
|
|
"base": "0xF8007000",
|
|||
|
|
"high": "0xF80070FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"name": "ps7_dma_ns",
|
|||
|
|
"base": "0xF8004000",
|
|||
|
|
"high": "0xF8004FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"name": "ps7_dma_s",
|
|||
|
|
"base": "0xF8003000",
|
|||
|
|
"high": "0xF8003FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"name": "ps7_globaltimer_0",
|
|||
|
|
"base": "0xF8F00200",
|
|||
|
|
"high": "0xF8F002FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"name": "ps7_gpio_0",
|
|||
|
|
"base": "0xE000A000",
|
|||
|
|
"high": "0xE000AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"name": "ps7_gpv_0",
|
|||
|
|
"base": "0xF8900000",
|
|||
|
|
"high": "0xF89FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"name": "ps7_intc_dist_0",
|
|||
|
|
"base": "0xF8F01000",
|
|||
|
|
"high": "0xF8F01FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"name": "ps7_iop_bus_config_0",
|
|||
|
|
"base": "0xE0200000",
|
|||
|
|
"high": "0xE0200FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"name": "ps7_l2cachec_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"name": "ps7_ocmc_0",
|
|||
|
|
"base": "0xF800C000",
|
|||
|
|
"high": "0xF800CFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"name": "ps7_pl310_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"name": "ps7_pmu_0",
|
|||
|
|
"base": "0xF8893000",
|
|||
|
|
"high": "0xF8893FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"name": "ps7_qspi_0",
|
|||
|
|
"base": "0xE000D000",
|
|||
|
|
"high": "0xE000DFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"name": "ps7_qspi_linear_0",
|
|||
|
|
"base": "0xFC000000",
|
|||
|
|
"high": "0xFCFFFFFF",
|
|||
|
|
"size": "16777216",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "FLASH",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"name": "ps7_scuc_0",
|
|||
|
|
"base": "0xF8F00000",
|
|||
|
|
"high": "0xF8F000FC",
|
|||
|
|
"size": "253",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"name": "ps7_scugic_0",
|
|||
|
|
"base": "0xF8F00100",
|
|||
|
|
"high": "0xF8F001FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"name": "ps7_scutimer_0",
|
|||
|
|
"base": "0xF8F00600",
|
|||
|
|
"high": "0xF8F0061F",
|
|||
|
|
"size": "32",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"name": "ps7_scuwdt_0",
|
|||
|
|
"base": "0xF8F00620",
|
|||
|
|
"high": "0xF8F006FF",
|
|||
|
|
"size": "224",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"name": "ps7_sd_0",
|
|||
|
|
"base": "0xE0100000",
|
|||
|
|
"high": "0xE0100FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"name": "ps7_slcr_0",
|
|||
|
|
"base": "0xF8000000",
|
|||
|
|
"high": "0xF8000FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"name": "ps7_uart_1",
|
|||
|
|
"base": "0xE0001000",
|
|||
|
|
"high": "0xE0001FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"name": "ps7_xadc_0",
|
|||
|
|
"base": "0xF8007100",
|
|||
|
|
"high": "0xF8007120",
|
|||
|
|
"size": "33",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"name": "ps7_ddr_0",
|
|||
|
|
"base": "0x00100000",
|
|||
|
|
"high": "0x3FFFFFFF",
|
|||
|
|
"size": "1072693248",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"name": "ps7_ram_0",
|
|||
|
|
"base": "0x00000000",
|
|||
|
|
"high": "0x0002FFFF",
|
|||
|
|
"size": "196608",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"name": "ps7_ram_1",
|
|||
|
|
"base": "0xFFFF0000",
|
|||
|
|
"high": "0xFFFFFDFF",
|
|||
|
|
"size": "65024",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.541
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_ENABLED], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.542
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_ENABLED], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.542
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_EVENT_COUNTERS], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.544
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_EVENT_COUNTERS], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.544
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_LATENCY_COUNTERS], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.556
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_LATENCY_COUNTERS], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.557
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_COUNTER_WIDTH], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.559
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_COUNTER_WIDTH], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.559
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_FREQ], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.560
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_FREQ], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.561
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_CPU_CLK_FREQ_HZ], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.562
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_CPU_CLK_FREQ_HZ], Result: [null, 666666687]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.564
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_connected_periphs L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.566
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_connected_periphs L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, axi_dma_0 axi_dynclk_0 axi_gpio_0 axi_gpio_1 axi_vdma_0 ps7_afi_0 ps7_afi_1 ps7_afi_2 ps7_afi_3 ps7_coresight_comp_0 ps7_ddr_0 ps7_ddrc_0 ps7_dev_cfg_0 ps7_dma_ns ps7_dma_s ps7_globaltimer_0 ps7_gpio_0 ps7_gpv_0 ps7_intc_dist_0 ps7_iop_bus_config_0 ps7_l2cachec_0 ps7_ocmc_0 ps7_pl310_0 ps7_pmu_0 ps7_qspi_0 ps7_qspi_linear_0 ps7_ram_0 ps7_ram_1 ps7_scuc_0 ps7_scugic_0 ps7_scutimer_0 ps7_scuwdt_0 ps7_sd_0 ps7_slcr_0 ps7_uart_1 ps7_xadc_0 v_tc_0]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.566
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_files_on_hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf bit], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.567
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_files_on_hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf bit], Result: [null, design_1_wrapper.bit]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.568
|
|||
|
|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.571
|
|||
|
|
!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#1]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.572
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.640
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.641
|
|||
|
|
!MESSAGE XSCT Command: [version -server], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.643
|
|||
|
|
!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.643
|
|||
|
|
!MESSAGE XSCT Command: [version], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.643
|
|||
|
|
!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
|
SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
|
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.645
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.649
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.649
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.659
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.660
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.664
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.664
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.674
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.674
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.679
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.679
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.689
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.689
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.693
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.694
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.704
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.704
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.708
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.708
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.718
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.719
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.729
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.729
|
|||
|
|
!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.730
|
|||
|
|
!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.731
|
|||
|
|
!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.732
|
|||
|
|
!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.732
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.747
|
|||
|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:19:59.748
|
|||
|
|
!MESSAGE XSCT Command: [rst -system], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:00.233
|
|||
|
|
!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:00.233
|
|||
|
|
!MESSAGE XSCT Command: [after 3000], Thread: Worker-12
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.241
|
|||
|
|
!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-12
|
|||
|
|
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.256
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.263
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.263
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.273
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.274
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.285
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:03.286
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.475
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.502
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.521
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.521
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.549
|
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_0]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.549
|
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.550
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.551
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.564
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.564
|
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.807
|
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.807
|
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.812
|
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.813
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:14.814
|
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:20.444
|
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!MESSAGE XSCT Command: [disconnect tcfchan#1], Thread: Thread-111
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:20.451
|
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!MESSAGE XSCT command with result: [disconnect tcfchan#1], Result: [null, ]. Thread: Thread-111
|
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-24 17:20:21.465
|
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!MESSAGE Updating toolusage
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.467
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.475
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#2]. Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.476
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.486
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.486
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.492
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.492
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.511
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.511
|
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-1
|
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.537
|
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.537
|
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|
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-1
|
|||
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.559
|
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-1
|
|||
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.559
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.560
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#2]. Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.561
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.565
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.565
|
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!MESSAGE XSCT Command: [version -server], Thread: Worker-1
|
|||
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.566
|
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.566
|
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!MESSAGE XSCT Command: [version], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.567
|
|||
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
|
SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
|
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.567
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.571
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.571
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.581
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.581
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.585
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.585
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.595
|
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.596
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.600
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.600
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.610
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.610
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.614
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.614
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.625
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.625
|
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|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.629
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.629
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.639
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.639
|
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|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.643
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.643
|
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|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.653
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.654
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.670
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.671
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.688
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.688
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.690
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.690
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.703
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:21.704
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.970
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_2]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.970
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.972
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.972
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.985
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.985
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!MESSAGE XSCT Command: [stop], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.986
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:22.987
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.278
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.278
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.291
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.291
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
|
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.304
|
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|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.304
|
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-1
|
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.355
|
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.355
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.369
|
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|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:23.369
|
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.543
|
|||
|
|
!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.543
|
|||
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-1
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.544
|
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.585
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
|
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.632
|
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|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.633
|
|||
|
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!MESSAGE XSCT Command: [con], Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:20:24.641
|
|||
|
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-1
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:33:44.712
|
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|
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!MESSAGE XSCT Command: [disconnect tcfchan#2], Thread: Thread-165
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:33:44.714
|
|||
|
|
!MESSAGE XSCT command with result: [disconnect tcfchan#2], Result: [null, ]. Thread: Thread-165
|
|||
|
|
!SESSION 2022-11-24 17:35:07.994 -----------------------------------------------
|
|||
|
|
eclipse.buildId=2018.3
|
|||
|
|
java.version=1.8.0_112
|
|||
|
|
java.vendor=Oracle Corporation
|
|||
|
|
BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=zh_CN
|
|||
|
|
Command-line arguments: -os win32 -ws win32 -arch x86_64 -data L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk
|
|||
|
|
|
|||
|
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!ENTRY org.eclipse.ui 2 0 2022-11-24 17:35:15.202
|
|||
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!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-24 17:35:15.202
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
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|
|||
|
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!ENTRY org.eclipse.ui 2 0 2022-11-24 17:35:15.592
|
|||
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!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-24 17:35:15.592
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:21.589
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::init_repo], Thread: Worker-2
|
|||
|
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:21.589
|
|||
|
|
!MESSAGE XSCT Command: [set sdk::sdk_chan tcfchan#0], Thread: Thread-16
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:21.593
|
|||
|
|
!MESSAGE XSCT command with result: [set sdk::sdk_chan tcfchan#0], Result: [null, tcfchan#0]. Thread: Thread-16
|
|||
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:21.594
|
|||
|
|
!MESSAGE XSCT Command: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Thread: Thread-16
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:23.161
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::init_repo], Result: [null, ]. Thread: Worker-2
|
|||
|
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:23.161
|
|||
|
|
!MESSAGE XSCT command with result: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Result: [null, ]. Thread: Thread-16
|
|||
|
|
|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:23.171
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-5
|
|||
|
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:26.002
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, ]. Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.518
|
|||
|
|
!MESSAGE XSCT Command: [ ::hsi::utils::set_current_hw_sw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss ], Thread: main
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.521
|
|||
|
|
!MESSAGE XSCT command with result: [ ::hsi::utils::set_current_hw_sw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss ], Result: [null, ]. Thread: main
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.522
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_sw_details -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss], Thread: main
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.524
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_sw_details -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss], Result: [null, {"procname": "ps7_cortexa9_0",
|
|||
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"osname": "standalone",
|
|||
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|
"osver": "6.8",
|
|||
|
|
}]. Thread: main
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.526
|
|||
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|
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: main
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.536
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"adc_read_0": {"hier_name": "adc_read_0",
|
|||
|
|
"type": "adc_read",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dma_0": {"hier_name": "axi_dma_0",
|
|||
|
|
"type": "axi_dma",
|
|||
|
|
"version": "7.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {"hier_name": "axi_dynclk_0",
|
|||
|
|
"type": "axi_dynclk",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0": {"hier_name": "axi_gpio_0",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"hier_name": "axi_gpio_1",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_smc": {"hier_name": "axi_smc",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_smc1": {"hier_name": "axi_smc1",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"hier_name": "axi_vdma_0",
|
|||
|
|
"type": "axi_vdma",
|
|||
|
|
"version": "6.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"clk_wiz_0": {"hier_name": "clk_wiz_0",
|
|||
|
|
"type": "clk_wiz",
|
|||
|
|
"version": "6.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"direct_fft_0": {"hier_name": "direct_fft_0",
|
|||
|
|
"type": "direct_fft",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"key_ec11_0": {"hier_name": "key_ec11_0",
|
|||
|
|
"type": "key_ec11",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"processing_system7_0": {"hier_name": "processing_system7_0",
|
|||
|
|
"type": "processing_system7",
|
|||
|
|
"version": "5.5",
|
|||
|
|
"ip_type": "",
|
|||
|
|
},
|
|||
|
|
"ps7_0_axi_periph": {"hier_name": "ps7_0_axi_periph",
|
|||
|
|
"type": "axi_interconnect",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"rgb2dvi_0": {"hier_name": "rgb2dvi_0",
|
|||
|
|
"type": "rgb2dvi",
|
|||
|
|
"version": "1.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_100M": {"hier_name": "rst_ps7_0_100M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_142M": {"hier_name": "rst_ps7_0_142M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_250M": {"hier_name": "rst_ps7_0_250M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0": {"hier_name": "system_ila_0",
|
|||
|
|
"type": "system_ila",
|
|||
|
|
"version": "1.1",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"util_vector_logic_0": {"hier_name": "util_vector_logic_0",
|
|||
|
|
"type": "util_vector_logic",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_axi4s_vid_out_0": {"hier_name": "v_axi4s_vid_out_0",
|
|||
|
|
"type": "v_axi4s_vid_out",
|
|||
|
|
"version": "4.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_tc_0": {"hier_name": "v_tc_0",
|
|||
|
|
"type": "v_tc",
|
|||
|
|
"version": "6.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"window_0": {"hier_name": "window_0",
|
|||
|
|
"type": "window",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"xlconcat_0": {"hier_name": "xlconcat_0",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_clockc_0": {"hier_name": "ps7_clockc_0",
|
|||
|
|
"type": "ps7_clockc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"hier_name": "ps7_uart_1",
|
|||
|
|
"type": "ps7_uart",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"hier_name": "ps7_pl310_0",
|
|||
|
|
"type": "ps7_pl310",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"hier_name": "ps7_pmu_0",
|
|||
|
|
"type": "ps7_pmu",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"hier_name": "ps7_qspi_0",
|
|||
|
|
"type": "ps7_qspi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"hier_name": "ps7_qspi_linear_0",
|
|||
|
|
"type": "ps7_qspi_linear",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_axi_interconnect_0": {"hier_name": "ps7_axi_interconnect_0",
|
|||
|
|
"type": "ps7_axi_interconnect",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_0": {"hier_name": "ps7_cortexa9_0",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"hier_name": "ps7_cortexa9_1",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"hier_name": "ps7_ddr_0",
|
|||
|
|
"type": "ps7_ddr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"hier_name": "ps7_sd_0",
|
|||
|
|
"type": "ps7_sdio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"hier_name": "ps7_gpio_0",
|
|||
|
|
"type": "ps7_gpio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"hier_name": "ps7_ddrc_0",
|
|||
|
|
"type": "ps7_ddrc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"hier_name": "ps7_dev_cfg_0",
|
|||
|
|
"type": "ps7_dev_cfg",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"hier_name": "ps7_xadc_0",
|
|||
|
|
"type": "ps7_xadc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"hier_name": "ps7_ocmc_0",
|
|||
|
|
"type": "ps7_ocmc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"hier_name": "ps7_coresight_comp_0",
|
|||
|
|
"type": "ps7_coresight_comp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"hier_name": "ps7_gpv_0",
|
|||
|
|
"type": "ps7_gpv",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"hier_name": "ps7_scuc_0",
|
|||
|
|
"type": "ps7_scuc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"hier_name": "ps7_globaltimer_0",
|
|||
|
|
"type": "ps7_globaltimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"hier_name": "ps7_intc_dist_0",
|
|||
|
|
"type": "ps7_intc_dist",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"hier_name": "ps7_l2cachec_0",
|
|||
|
|
"type": "ps7_l2cachec",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"hier_name": "ps7_dma_s",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"hier_name": "ps7_iop_bus_config_0",
|
|||
|
|
"type": "ps7_iop_bus_config",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"hier_name": "ps7_ram_0",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"hier_name": "ps7_ram_1",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"hier_name": "ps7_scugic_0",
|
|||
|
|
"type": "ps7_scugic",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "INTERRUPT_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"hier_name": "ps7_scutimer_0",
|
|||
|
|
"type": "ps7_scutimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"hier_name": "ps7_scuwdt_0",
|
|||
|
|
"type": "ps7_scuwdt",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"hier_name": "ps7_slcr_0",
|
|||
|
|
"type": "ps7_slcr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"hier_name": "ps7_dma_ns",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"hier_name": "ps7_afi_0",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"hier_name": "ps7_afi_1",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"hier_name": "ps7_afi_2",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"hier_name": "ps7_afi_3",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_m_axi_gp0": {"hier_name": "ps7_m_axi_gp0",
|
|||
|
|
"type": "ps7_m_axi_gp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_g_inst": {"hier_name": "system_ila_0/system_ila_0_g_inst",
|
|||
|
|
"type": "gigantic_mux",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_ila_lib": {"hier_name": "system_ila_0/system_ila_0_ila_lib",
|
|||
|
|
"type": "ila",
|
|||
|
|
"version": "6.2",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_ar": {"hier_name": "system_ila_0/system_ila_0_slot_0_ar",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_aw": {"hier_name": "system_ila_0/system_ila_0_slot_0_aw",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_b": {"hier_name": "system_ila_0/system_ila_0_slot_0_b",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_r": {"hier_name": "system_ila_0/system_ila_0_slot_0_r",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_w": {"hier_name": "system_ila_0/system_ila_0_slot_0_w",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
}]. Thread: main
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.538
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: main
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.540
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"device": "7z035",
|
|||
|
|
"family": "zynq",
|
|||
|
|
"timestamp": "Thu Nov 24 17:05:01 2022",
|
|||
|
|
"vivado_version": "2018.3",
|
|||
|
|
"part": "xc7z035ffg676-2",
|
|||
|
|
}]. Thread: main
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.541
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::closesw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss], Thread: main
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-24 17:35:35.542
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::closesw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/FSBL_bsp/system.mss], Result: [null, ]. Thread: main
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 1 0 2022-11-24 17:35:37.213
|
|||
|
|
!MESSAGE Updating toolusage
|
|||
|
|
!SESSION 2022-11-25 21:00:38.434 -----------------------------------------------
|
|||
|
|
eclipse.buildId=2018.3
|
|||
|
|
java.version=1.8.0_112
|
|||
|
|
java.vendor=Oracle Corporation
|
|||
|
|
BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=zh_CN
|
|||
|
|
Command-line arguments: -os win32 -ws win32 -arch x86_64 -data L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.ui 2 0 2022-11-25 21:00:46.324
|
|||
|
|
!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-25 21:00:46.324
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.ui 2 0 2022-11-25 21:00:46.779
|
|||
|
|
!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-25 21:00:46.779
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:52.472
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::init_repo], Thread: Worker-0
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:52.472
|
|||
|
|
!MESSAGE XSCT Command: [set sdk::sdk_chan tcfchan#0], Thread: Thread-16
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:54.164
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::init_repo], Result: [null, ]. Thread: Worker-0
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:54.165
|
|||
|
|
!MESSAGE XSCT command with result: [set sdk::sdk_chan tcfchan#0], Result: [null, tcfchan#0]. Thread: Thread-16
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:54.166
|
|||
|
|
!MESSAGE XSCT Command: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Thread: Thread-16
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:54.167
|
|||
|
|
!MESSAGE XSCT command with result: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Result: [null, ]. Thread: Thread-16
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:54.180
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-3
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:00:57.868
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, ]. Thread: Worker-3
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.769
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.771
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"device": "7z035",
|
|||
|
|
"family": "zynq",
|
|||
|
|
"timestamp": "Thu Nov 24 17:05:01 2022",
|
|||
|
|
"vivado_version": "2018.3",
|
|||
|
|
"part": "xc7z035ffg676-2",
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:09:04.838
|
|||
|
|
!MESSAGE Updating toolusage
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.838
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.846
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"adc_read_0": {"hier_name": "adc_read_0",
|
|||
|
|
"type": "adc_read",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dma_0": {"hier_name": "axi_dma_0",
|
|||
|
|
"type": "axi_dma",
|
|||
|
|
"version": "7.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {"hier_name": "axi_dynclk_0",
|
|||
|
|
"type": "axi_dynclk",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0": {"hier_name": "axi_gpio_0",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"hier_name": "axi_gpio_1",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_smc": {"hier_name": "axi_smc",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_smc1": {"hier_name": "axi_smc1",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"hier_name": "axi_vdma_0",
|
|||
|
|
"type": "axi_vdma",
|
|||
|
|
"version": "6.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"clk_wiz_0": {"hier_name": "clk_wiz_0",
|
|||
|
|
"type": "clk_wiz",
|
|||
|
|
"version": "6.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"direct_fft_0": {"hier_name": "direct_fft_0",
|
|||
|
|
"type": "direct_fft",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"key_ec11_0": {"hier_name": "key_ec11_0",
|
|||
|
|
"type": "key_ec11",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"processing_system7_0": {"hier_name": "processing_system7_0",
|
|||
|
|
"type": "processing_system7",
|
|||
|
|
"version": "5.5",
|
|||
|
|
"ip_type": "",
|
|||
|
|
},
|
|||
|
|
"ps7_0_axi_periph": {"hier_name": "ps7_0_axi_periph",
|
|||
|
|
"type": "axi_interconnect",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"rgb2dvi_0": {"hier_name": "rgb2dvi_0",
|
|||
|
|
"type": "rgb2dvi",
|
|||
|
|
"version": "1.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_100M": {"hier_name": "rst_ps7_0_100M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_142M": {"hier_name": "rst_ps7_0_142M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_250M": {"hier_name": "rst_ps7_0_250M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0": {"hier_name": "system_ila_0",
|
|||
|
|
"type": "system_ila",
|
|||
|
|
"version": "1.1",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"util_vector_logic_0": {"hier_name": "util_vector_logic_0",
|
|||
|
|
"type": "util_vector_logic",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_axi4s_vid_out_0": {"hier_name": "v_axi4s_vid_out_0",
|
|||
|
|
"type": "v_axi4s_vid_out",
|
|||
|
|
"version": "4.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_tc_0": {"hier_name": "v_tc_0",
|
|||
|
|
"type": "v_tc",
|
|||
|
|
"version": "6.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"window_0": {"hier_name": "window_0",
|
|||
|
|
"type": "window",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"xlconcat_0": {"hier_name": "xlconcat_0",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_clockc_0": {"hier_name": "ps7_clockc_0",
|
|||
|
|
"type": "ps7_clockc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"hier_name": "ps7_uart_1",
|
|||
|
|
"type": "ps7_uart",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"hier_name": "ps7_pl310_0",
|
|||
|
|
"type": "ps7_pl310",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"hier_name": "ps7_pmu_0",
|
|||
|
|
"type": "ps7_pmu",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"hier_name": "ps7_qspi_0",
|
|||
|
|
"type": "ps7_qspi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"hier_name": "ps7_qspi_linear_0",
|
|||
|
|
"type": "ps7_qspi_linear",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_axi_interconnect_0": {"hier_name": "ps7_axi_interconnect_0",
|
|||
|
|
"type": "ps7_axi_interconnect",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_0": {"hier_name": "ps7_cortexa9_0",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"hier_name": "ps7_cortexa9_1",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"hier_name": "ps7_ddr_0",
|
|||
|
|
"type": "ps7_ddr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"hier_name": "ps7_sd_0",
|
|||
|
|
"type": "ps7_sdio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"hier_name": "ps7_gpio_0",
|
|||
|
|
"type": "ps7_gpio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"hier_name": "ps7_ddrc_0",
|
|||
|
|
"type": "ps7_ddrc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"hier_name": "ps7_dev_cfg_0",
|
|||
|
|
"type": "ps7_dev_cfg",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"hier_name": "ps7_xadc_0",
|
|||
|
|
"type": "ps7_xadc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"hier_name": "ps7_ocmc_0",
|
|||
|
|
"type": "ps7_ocmc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"hier_name": "ps7_coresight_comp_0",
|
|||
|
|
"type": "ps7_coresight_comp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"hier_name": "ps7_gpv_0",
|
|||
|
|
"type": "ps7_gpv",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"hier_name": "ps7_scuc_0",
|
|||
|
|
"type": "ps7_scuc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"hier_name": "ps7_globaltimer_0",
|
|||
|
|
"type": "ps7_globaltimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"hier_name": "ps7_intc_dist_0",
|
|||
|
|
"type": "ps7_intc_dist",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"hier_name": "ps7_l2cachec_0",
|
|||
|
|
"type": "ps7_l2cachec",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"hier_name": "ps7_dma_s",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"hier_name": "ps7_iop_bus_config_0",
|
|||
|
|
"type": "ps7_iop_bus_config",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"hier_name": "ps7_ram_0",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"hier_name": "ps7_ram_1",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"hier_name": "ps7_scugic_0",
|
|||
|
|
"type": "ps7_scugic",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "INTERRUPT_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"hier_name": "ps7_scutimer_0",
|
|||
|
|
"type": "ps7_scutimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"hier_name": "ps7_scuwdt_0",
|
|||
|
|
"type": "ps7_scuwdt",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"hier_name": "ps7_slcr_0",
|
|||
|
|
"type": "ps7_slcr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"hier_name": "ps7_dma_ns",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"hier_name": "ps7_afi_0",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"hier_name": "ps7_afi_1",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"hier_name": "ps7_afi_2",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"hier_name": "ps7_afi_3",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_m_axi_gp0": {"hier_name": "ps7_m_axi_gp0",
|
|||
|
|
"type": "ps7_m_axi_gp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_g_inst": {"hier_name": "system_ila_0/system_ila_0_g_inst",
|
|||
|
|
"type": "gigantic_mux",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_ila_lib": {"hier_name": "system_ila_0/system_ila_0_ila_lib",
|
|||
|
|
"type": "ila",
|
|||
|
|
"version": "6.2",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_ar": {"hier_name": "system_ila_0/system_ila_0_slot_0_ar",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_aw": {"hier_name": "system_ila_0/system_ila_0_slot_0_aw",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_b": {"hier_name": "system_ila_0/system_ila_0_slot_0_b",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_r": {"hier_name": "system_ila_0/system_ila_0_slot_0_r",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_w": {"hier_name": "system_ila_0/system_ila_0_slot_0_w",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.850
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.854
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"PCW_APU_PERIPHERAL_FREQMHZ": "666.666666",
|
|||
|
|
"PCW_DDR_HPRLPR_QUEUE_PARTITION": "HPR(0)/LPR(32)",
|
|||
|
|
"PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": "15",
|
|||
|
|
"PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_DDR_PORT0_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT1_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT2_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT3_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_FPGA0_PERIPHERAL_FREQMHZ": "100",
|
|||
|
|
"PCW_UIPARAM_DDR_BUS_WIDTH": "32 Bit",
|
|||
|
|
"PCW_UIPARAM_DDR_FREQ_MHZ": "533.333333",
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.854
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.893
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.899
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.910
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0_S_AXI_LITE": {"name": "axi_dma_0",
|
|||
|
|
"base": "0x40400000",
|
|||
|
|
"high": "0x4040FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0_S_AXI": {"name": "axi_gpio_0",
|
|||
|
|
"base": "0x41200000",
|
|||
|
|
"high": "0x4120FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1_S_AXI": {"name": "axi_gpio_1",
|
|||
|
|
"base": "0x41210000",
|
|||
|
|
"high": "0x4121FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0_S_AXI_LITE": {"name": "axi_vdma_0",
|
|||
|
|
"base": "0x43000000",
|
|||
|
|
"high": "0x4300FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0_s00_axi": {"name": "axi_dynclk_0",
|
|||
|
|
"base": "0x43C00000",
|
|||
|
|
"high": "0x43C0FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "s00_axi",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"v_tc_0_ctrl": {"name": "v_tc_0",
|
|||
|
|
"base": "0x43C10000",
|
|||
|
|
"high": "0x43C1FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "ctrl",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"name": "ps7_afi_0",
|
|||
|
|
"base": "0xF8008000",
|
|||
|
|
"high": "0xF8008FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"name": "ps7_afi_1",
|
|||
|
|
"base": "0xF8009000",
|
|||
|
|
"high": "0xF8009FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"name": "ps7_afi_2",
|
|||
|
|
"base": "0xF800A000",
|
|||
|
|
"high": "0xF800AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"name": "ps7_afi_3",
|
|||
|
|
"base": "0xF800B000",
|
|||
|
|
"high": "0xF800BFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"name": "ps7_coresight_comp_0",
|
|||
|
|
"base": "0xF8800000",
|
|||
|
|
"high": "0xF88FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"name": "ps7_ddrc_0",
|
|||
|
|
"base": "0xF8006000",
|
|||
|
|
"high": "0xF8006FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"name": "ps7_dev_cfg_0",
|
|||
|
|
"base": "0xF8007000",
|
|||
|
|
"high": "0xF80070FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"name": "ps7_dma_ns",
|
|||
|
|
"base": "0xF8004000",
|
|||
|
|
"high": "0xF8004FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"name": "ps7_dma_s",
|
|||
|
|
"base": "0xF8003000",
|
|||
|
|
"high": "0xF8003FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"name": "ps7_globaltimer_0",
|
|||
|
|
"base": "0xF8F00200",
|
|||
|
|
"high": "0xF8F002FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"name": "ps7_gpio_0",
|
|||
|
|
"base": "0xE000A000",
|
|||
|
|
"high": "0xE000AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"name": "ps7_gpv_0",
|
|||
|
|
"base": "0xF8900000",
|
|||
|
|
"high": "0xF89FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"name": "ps7_intc_dist_0",
|
|||
|
|
"base": "0xF8F01000",
|
|||
|
|
"high": "0xF8F01FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"name": "ps7_iop_bus_config_0",
|
|||
|
|
"base": "0xE0200000",
|
|||
|
|
"high": "0xE0200FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"name": "ps7_l2cachec_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"name": "ps7_ocmc_0",
|
|||
|
|
"base": "0xF800C000",
|
|||
|
|
"high": "0xF800CFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"name": "ps7_pl310_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"name": "ps7_pmu_0",
|
|||
|
|
"base": "0xF8893000",
|
|||
|
|
"high": "0xF8893FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"name": "ps7_qspi_0",
|
|||
|
|
"base": "0xE000D000",
|
|||
|
|
"high": "0xE000DFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"name": "ps7_qspi_linear_0",
|
|||
|
|
"base": "0xFC000000",
|
|||
|
|
"high": "0xFCFFFFFF",
|
|||
|
|
"size": "16777216",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "FLASH",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"name": "ps7_scuc_0",
|
|||
|
|
"base": "0xF8F00000",
|
|||
|
|
"high": "0xF8F000FC",
|
|||
|
|
"size": "253",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"name": "ps7_scugic_0",
|
|||
|
|
"base": "0xF8F00100",
|
|||
|
|
"high": "0xF8F001FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"name": "ps7_scutimer_0",
|
|||
|
|
"base": "0xF8F00600",
|
|||
|
|
"high": "0xF8F0061F",
|
|||
|
|
"size": "32",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"name": "ps7_scuwdt_0",
|
|||
|
|
"base": "0xF8F00620",
|
|||
|
|
"high": "0xF8F006FF",
|
|||
|
|
"size": "224",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"name": "ps7_sd_0",
|
|||
|
|
"base": "0xE0100000",
|
|||
|
|
"high": "0xE0100FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"name": "ps7_slcr_0",
|
|||
|
|
"base": "0xF8000000",
|
|||
|
|
"high": "0xF8000FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"name": "ps7_uart_1",
|
|||
|
|
"base": "0xE0001000",
|
|||
|
|
"high": "0xE0001FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"name": "ps7_xadc_0",
|
|||
|
|
"base": "0xF8007100",
|
|||
|
|
"high": "0xF8007120",
|
|||
|
|
"size": "33",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"name": "ps7_ddr_0",
|
|||
|
|
"base": "0x00100000",
|
|||
|
|
"high": "0x3FFFFFFF",
|
|||
|
|
"size": "1072693248",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"name": "ps7_ram_0",
|
|||
|
|
"base": "0x00000000",
|
|||
|
|
"high": "0x0002FFFF",
|
|||
|
|
"size": "196608",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"name": "ps7_ram_1",
|
|||
|
|
"base": "0xFFFF0000",
|
|||
|
|
"high": "0xFFFFFDFF",
|
|||
|
|
"size": "65024",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.911
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.913
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.913
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.915
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.915
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.917
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.918
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.919
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.920
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.933
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.934
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.936
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Result: [null, 666666687]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.937
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.939
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"ps7_cortexa9_0": {"bscan": "",
|
|||
|
|
"index": "0",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"bscan": "",
|
|||
|
|
"index": "1",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.940
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.979
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.984
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.993
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Result: [null, {"axi_dma_0_S_AXI_LITE": {"name": "axi_dma_0",
|
|||
|
|
"base": "0x40400000",
|
|||
|
|
"high": "0x4040FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0_S_AXI": {"name": "axi_gpio_0",
|
|||
|
|
"base": "0x41200000",
|
|||
|
|
"high": "0x4120FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1_S_AXI": {"name": "axi_gpio_1",
|
|||
|
|
"base": "0x41210000",
|
|||
|
|
"high": "0x4121FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0_S_AXI_LITE": {"name": "axi_vdma_0",
|
|||
|
|
"base": "0x43000000",
|
|||
|
|
"high": "0x4300FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0_s00_axi": {"name": "axi_dynclk_0",
|
|||
|
|
"base": "0x43C00000",
|
|||
|
|
"high": "0x43C0FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "s00_axi",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"v_tc_0_ctrl": {"name": "v_tc_0",
|
|||
|
|
"base": "0x43C10000",
|
|||
|
|
"high": "0x43C1FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "ctrl",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"name": "ps7_afi_0",
|
|||
|
|
"base": "0xF8008000",
|
|||
|
|
"high": "0xF8008FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"name": "ps7_afi_1",
|
|||
|
|
"base": "0xF8009000",
|
|||
|
|
"high": "0xF8009FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"name": "ps7_afi_2",
|
|||
|
|
"base": "0xF800A000",
|
|||
|
|
"high": "0xF800AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"name": "ps7_afi_3",
|
|||
|
|
"base": "0xF800B000",
|
|||
|
|
"high": "0xF800BFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"name": "ps7_coresight_comp_0",
|
|||
|
|
"base": "0xF8800000",
|
|||
|
|
"high": "0xF88FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"name": "ps7_ddrc_0",
|
|||
|
|
"base": "0xF8006000",
|
|||
|
|
"high": "0xF8006FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"name": "ps7_dev_cfg_0",
|
|||
|
|
"base": "0xF8007000",
|
|||
|
|
"high": "0xF80070FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"name": "ps7_dma_ns",
|
|||
|
|
"base": "0xF8004000",
|
|||
|
|
"high": "0xF8004FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"name": "ps7_dma_s",
|
|||
|
|
"base": "0xF8003000",
|
|||
|
|
"high": "0xF8003FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"name": "ps7_globaltimer_0",
|
|||
|
|
"base": "0xF8F00200",
|
|||
|
|
"high": "0xF8F002FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"name": "ps7_gpio_0",
|
|||
|
|
"base": "0xE000A000",
|
|||
|
|
"high": "0xE000AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"name": "ps7_gpv_0",
|
|||
|
|
"base": "0xF8900000",
|
|||
|
|
"high": "0xF89FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"name": "ps7_intc_dist_0",
|
|||
|
|
"base": "0xF8F01000",
|
|||
|
|
"high": "0xF8F01FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"name": "ps7_iop_bus_config_0",
|
|||
|
|
"base": "0xE0200000",
|
|||
|
|
"high": "0xE0200FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"name": "ps7_l2cachec_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"name": "ps7_ocmc_0",
|
|||
|
|
"base": "0xF800C000",
|
|||
|
|
"high": "0xF800CFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"name": "ps7_pl310_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"name": "ps7_pmu_0",
|
|||
|
|
"base": "0xF8893000",
|
|||
|
|
"high": "0xF8893FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"name": "ps7_qspi_0",
|
|||
|
|
"base": "0xE000D000",
|
|||
|
|
"high": "0xE000DFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"name": "ps7_qspi_linear_0",
|
|||
|
|
"base": "0xFC000000",
|
|||
|
|
"high": "0xFCFFFFFF",
|
|||
|
|
"size": "16777216",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "FLASH",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"name": "ps7_scuc_0",
|
|||
|
|
"base": "0xF8F00000",
|
|||
|
|
"high": "0xF8F000FC",
|
|||
|
|
"size": "253",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"name": "ps7_scugic_0",
|
|||
|
|
"base": "0xF8F00100",
|
|||
|
|
"high": "0xF8F001FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"name": "ps7_scutimer_0",
|
|||
|
|
"base": "0xF8F00600",
|
|||
|
|
"high": "0xF8F0061F",
|
|||
|
|
"size": "32",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"name": "ps7_scuwdt_0",
|
|||
|
|
"base": "0xF8F00620",
|
|||
|
|
"high": "0xF8F006FF",
|
|||
|
|
"size": "224",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"name": "ps7_sd_0",
|
|||
|
|
"base": "0xE0100000",
|
|||
|
|
"high": "0xE0100FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"name": "ps7_slcr_0",
|
|||
|
|
"base": "0xF8000000",
|
|||
|
|
"high": "0xF8000FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"name": "ps7_uart_1",
|
|||
|
|
"base": "0xE0001000",
|
|||
|
|
"high": "0xE0001FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"name": "ps7_xadc_0",
|
|||
|
|
"base": "0xF8007100",
|
|||
|
|
"high": "0xF8007120",
|
|||
|
|
"size": "33",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"name": "ps7_ddr_0",
|
|||
|
|
"base": "0x00100000",
|
|||
|
|
"high": "0x3FFFFFFF",
|
|||
|
|
"size": "1072693248",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"name": "ps7_ram_0",
|
|||
|
|
"base": "0x00000000",
|
|||
|
|
"high": "0x0002FFFF",
|
|||
|
|
"size": "196608",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"name": "ps7_ram_1",
|
|||
|
|
"base": "0xFFFF0000",
|
|||
|
|
"high": "0xFFFFFDFF",
|
|||
|
|
"size": "65024",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.994
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_ENABLED], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.995
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_ENABLED], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.996
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_EVENT_COUNTERS], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.998
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_EVENT_COUNTERS], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:04.998
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_LATENCY_COUNTERS], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.000
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_LATENCY_COUNTERS], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.000
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_COUNTER_WIDTH], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.001
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_DEBUG_COUNTER_WIDTH], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.001
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_FREQ], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.012
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_FREQ], Result: [null, ]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.013
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_CPU_CLK_FREQ_HZ], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.015
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1 C_CPU_CLK_FREQ_HZ], Result: [null, 666666687]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.017
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_connected_periphs L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.018
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_connected_periphs L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, axi_dma_0 axi_dynclk_0 axi_gpio_0 axi_gpio_1 axi_vdma_0 ps7_afi_0 ps7_afi_1 ps7_afi_2 ps7_afi_3 ps7_coresight_comp_0 ps7_ddr_0 ps7_ddrc_0 ps7_dev_cfg_0 ps7_dma_ns ps7_dma_s ps7_globaltimer_0 ps7_gpio_0 ps7_gpv_0 ps7_intc_dist_0 ps7_iop_bus_config_0 ps7_l2cachec_0 ps7_ocmc_0 ps7_pl310_0 ps7_pmu_0 ps7_qspi_0 ps7_qspi_linear_0 ps7_ram_0 ps7_ram_1 ps7_scuc_0 ps7_scugic_0 ps7_scutimer_0 ps7_scuwdt_0 ps7_sd_0 ps7_slcr_0 ps7_uart_1 ps7_xadc_0 v_tc_0]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.019
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_files_on_hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf bit], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.021
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_files_on_hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf bit], Result: [null, design_1_wrapper.bit]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.021
|
|||
|
|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.025
|
|||
|
|
!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#1]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.026
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.316
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.317
|
|||
|
|
!MESSAGE XSCT Command: [version -server], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.318
|
|||
|
|
!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.318
|
|||
|
|
!MESSAGE XSCT Command: [version], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.319
|
|||
|
|
!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
|
SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
|
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.321
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.324
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.325
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.334
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.334
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.338
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.338
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.348
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.348
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.352
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.352
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.361
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.362
|
|||
|
|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.365
|
|||
|
|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.366
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.375
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.375
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.379
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1 Digilent JTAG-HS3 210299539789]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.379
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.388
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.388
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.398
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.398
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.399
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.399
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.406
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.406
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.421
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.421
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.912
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:05.913
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.916
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.945
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.958
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.958
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.969
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.970
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.981
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:08.982
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.170
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.195
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.210
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.215
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.258
|
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.259
|
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.261
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-4
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.261
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.274
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.274
|
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-4
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.464
|
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.464
|
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.469
|
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.469
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:09:20.470
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-4
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:16.775
|
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!MESSAGE XSCT Command: [disconnect tcfchan#1], Thread: Thread-125
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:16.783
|
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!MESSAGE XSCT command with result: [disconnect tcfchan#1], Result: [null, ]. Thread: Thread-125
|
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:10:17.825
|
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!MESSAGE Updating toolusage
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.827
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.833
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#2]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.834
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.844
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.845
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.851
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.851
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.869
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
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|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.870
|
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.908
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.908
|
|||
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-12
|
|||
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.933
|
|||
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.933
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.934
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|||
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#2]. Thread: Worker-12
|
|||
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.935
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.939
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.939
|
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!MESSAGE XSCT Command: [version -server], Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.940
|
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.940
|
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!MESSAGE XSCT Command: [version], Thread: Worker-12
|
|||
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.940
|
|||
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.941
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.945
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.946
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.956
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.956
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.960
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.961
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.971
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.972
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.977
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.977
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.987
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.987
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.991
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:17.991
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.001
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.001
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.005
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.005
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.015
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.015
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.019
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.019
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.029
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.029
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.039
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.039
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.046
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.046
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.048
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.048
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.060
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:18.060
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.541
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_0]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.541
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.542
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.543
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.555
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.555
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!MESSAGE XSCT Command: [stop], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.556
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.557
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.764
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.764
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.768
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.768
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.780
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.781
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.888
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.889
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.924
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:19.925
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.163
|
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.164
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.168
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.218
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.269
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.270
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!MESSAGE XSCT Command: [con], Thread: Worker-12
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:10:21.278
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-12
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:45.388
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!MESSAGE XSCT Command: [disconnect tcfchan#2], Thread: Thread-182
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:45.402
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!MESSAGE XSCT command with result: [disconnect tcfchan#2], Result: [null, ]. Thread: Thread-182
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:12:46.411
|
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!MESSAGE Updating toolusage
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.412
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.416
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#3]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.417
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.435
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.435
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!MESSAGE XSCT Command: [version -server], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.436
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.437
|
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!MESSAGE XSCT Command: [version], Thread: Worker-10
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.437
|
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.438
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.442
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.442
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.453
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-10
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.453
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.457
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.457
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.468
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.469
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.473
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.473
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.484
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.484
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.488
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.489
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.499
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.499
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.504
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.504
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.514
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.514
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.524
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.525
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.525
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.526
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.527
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.527
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.545
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:46.545
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:47.062
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:47.063
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.079
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-10
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.096
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.104
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.105
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.122
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.123
|
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.139
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:12:50.139
|
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:01.325
|
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:01.349
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:01.374
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:01.375
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.677
|
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_1]. Thread: Worker-10
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.678
|
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.679
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.680
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.692
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-10
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.693
|
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-10
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.854
|
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.854
|
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-10
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.859
|
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-10
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.859
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-10
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:02.860
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-10
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:05.337
|
|||
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!MESSAGE XSCT Command: [disconnect tcfchan#3], Thread: Thread-225
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:05.340
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!MESSAGE XSCT command with result: [disconnect tcfchan#3], Result: [null, ]. Thread: Thread-225
|
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:13:06.341
|
|||
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|
!MESSAGE Updating toolusage
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.342
|
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|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-11
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.348
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#4]. Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.349
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.360
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.360
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.366
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.366
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.382
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.383
|
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.410
|
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.410
|
|||
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.435
|
|||
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.435
|
|||
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-11
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.436
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#4]. Thread: Worker-11
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.437
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.441
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.441
|
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!MESSAGE XSCT Command: [version -server], Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.442
|
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.442
|
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!MESSAGE XSCT Command: [version], Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.443
|
|||
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
|
SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
|
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.443
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.447
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.447
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.458
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.458
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.462
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.463
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.473
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.474
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.478
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.478
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.488
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.489
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.493
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.493
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.503
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.503
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.508
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.508
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.518
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.518
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.522
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.522
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.532
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.532
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.542
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.542
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.548
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.548
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.550
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.550
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.563
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:06.563
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.833
|
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_2]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.833
|
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.834
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.834
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.846
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.847
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!MESSAGE XSCT Command: [stop], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.848
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:07.848
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.037
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.038
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.043
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.043
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.056
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.056
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.103
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.104
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.116
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:08.117
|
|||
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|
!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.351
|
|||
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-11
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.352
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-11
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.353
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.454
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.500
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.500
|
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!MESSAGE XSCT Command: [con], Thread: Worker-11
|
|||
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:13:09.509
|
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:16.903
|
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!MESSAGE XSCT Command: [disconnect tcfchan#4], Thread: Thread-282
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:16.908
|
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!MESSAGE XSCT command with result: [disconnect tcfchan#4], Result: [null, ]. Thread: Thread-282
|
|||
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:15:17.909
|
|||
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!MESSAGE Updating toolusage
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.911
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-13
|
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.918
|
|||
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#5]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.919
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.930
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.930
|
|||
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!MESSAGE XSCT Command: [version -server], Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.932
|
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-13
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.932
|
|||
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|
!MESSAGE XSCT Command: [version], Thread: Worker-13
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.932
|
|||
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
|
SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
|
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-13
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.933
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.938
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.939
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.957
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.957
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.962
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.962
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.972
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.973
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.977
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.977
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.987
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.987
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.991
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:17.991
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.002
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.002
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.006
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.006
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.015
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.016
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.027
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.027
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.028
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.028
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.030
|
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-13
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.030
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.048
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.049
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.573
|
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:18.574
|
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.578
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.596
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.604
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.605
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.622
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.623
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.634
|
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:21.635
|
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:32.813
|
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:32.841
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:32.860
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-13
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:32.860
|
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|
|
!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-13
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.146
|
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_3]. Thread: Worker-13
|
|||
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.147
|
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|
!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.148
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-13
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.148
|
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|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-13
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.160
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-13
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.160
|
|||
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|
!MESSAGE XSCT Command: [ps7_init], Thread: Worker-13
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.445
|
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.445
|
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.450
|
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-13
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.450
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:34.451
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-13
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:43.226
|
|||
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!MESSAGE XSCT Command: [disconnect tcfchan#5], Thread: Thread-325
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:43.229
|
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!MESSAGE XSCT command with result: [disconnect tcfchan#5], Result: [null, ]. Thread: Thread-325
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:15:44.228
|
|||
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!MESSAGE Updating toolusage
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.228
|
|||
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|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.231
|
|||
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#6]. Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.231
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.239
|
|||
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|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.239
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.243
|
|||
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|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.243
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.252
|
|||
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
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|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.252
|
|||
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|
!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.270
|
|||
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|
!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.271
|
|||
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.293
|
|||
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.293
|
|||
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|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.294
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#6]. Thread: Worker-5
|
|||
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|
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.294
|
|||
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|
!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.298
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.298
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-5
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.303
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.312
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.313
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.318
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.319
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.329
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.330
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.334
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.334
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.344
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.344
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.348
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.348
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.357
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.358
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.361
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.362
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.372
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.372
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.376
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.376
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.386
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.386
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.397
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.397
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.398
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.398
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.399
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.400
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.412
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:44.412
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.678
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_4]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.678
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.679
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.679
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.692
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.692
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!MESSAGE XSCT Command: [stop], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.694
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.694
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.908
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.908
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.913
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.913
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.925
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.926
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.983
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.983
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.997
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:45.997
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.218
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.218
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.219
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.334
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.401
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.401
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!MESSAGE XSCT Command: [con], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:15:47.407
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:11.799
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!MESSAGE XSCT Command: [disconnect tcfchan#6], Thread: Thread-384
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:11.801
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!MESSAGE XSCT command with result: [disconnect tcfchan#6], Result: [null, ]. Thread: Thread-384
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:18:12.804
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!MESSAGE Updating toolusage
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.806
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.813
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#7]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.814
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.826
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.827
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!MESSAGE XSCT Command: [version -server], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.840
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.840
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!MESSAGE XSCT Command: [version], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.841
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.841
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.847
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.847
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.863
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.864
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.869
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.869
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.879
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.880
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.885
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.885
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.895
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.896
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.900
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.901
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.910
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.910
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.914
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.914
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.924
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.924
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.935
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.935
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.936
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.936
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.938
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.938
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.956
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:12.956
|
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-5
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:13.467
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:13.468
|
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.477
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.494
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.502
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.502
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.520
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.521
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.532
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:16.532
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:27.712
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:27.741
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:27.760
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:27.760
|
|||
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|
!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.167
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_5]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.168
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-5
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.169
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.169
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.182
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.183
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-5
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.341
|
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.341
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-5
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.355
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.355
|
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:29.356
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:37.699
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!MESSAGE XSCT Command: [disconnect tcfchan#7], Thread: Thread-427
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:37.701
|
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!MESSAGE XSCT command with result: [disconnect tcfchan#7], Result: [null, ]. Thread: Thread-427
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:18:38.703
|
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!MESSAGE Updating toolusage
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.705
|
|||
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|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.712
|
|||
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#8]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.713
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.754
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.754
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.761
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.761
|
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.779
|
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|
!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
|||
|
|
3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.779
|
|||
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.798
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.799
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.860
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.860
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.861
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#8]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.861
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.865
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.865
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!MESSAGE XSCT Command: [version -server], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.866
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.866
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!MESSAGE XSCT Command: [version], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.867
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.867
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.871
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.871
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.880
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.880
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.885
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.885
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.894
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.895
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.899
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.903
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.916
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.916
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.921
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.921
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.932
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.933
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.936
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.937
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.948
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.948
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.951
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.952
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.961
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.961
|
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.971
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.971
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.972
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.972
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.973
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.974
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.986
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:38.987
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.220
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_6]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.220
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.221
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.221
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.233
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.234
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!MESSAGE XSCT Command: [stop], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.235
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.235
|
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.427
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.428
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.433
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.433
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.445
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.445
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.528
|
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.529
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.542
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:40.542
|
|||
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.754
|
|||
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.754
|
|||
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.755
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.847
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.897
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.897
|
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!MESSAGE XSCT Command: [con], Thread: Worker-1
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:18:41.901
|
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:22:59.372
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.373
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.380
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.391
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.391
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.402
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.402
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.403
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.403
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.409
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.409
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.424
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.424
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.429
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.429
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.439
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.440
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.446
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.446
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.456
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.457
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.462
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.462
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.471
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.471
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.475
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.476
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.486
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.486
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.497
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.497
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.498
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.499
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.500
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.501
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.519
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:22:59.519
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:00.034
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:00.035
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.038
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.056
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.064
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.065
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.082
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.082
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.094
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:03.094
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:14.276
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:14.298
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:14.318
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:14.318
|
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.746
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_7]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.746
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.748
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.748
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-1
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.760
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.760
|
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.928
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.928
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-1
|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.932
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.933
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:15.934
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-1
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:18.789
|
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!MESSAGE XSCT Command: [disconnect tcfchan#9], Thread: Thread-529
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:18.792
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!MESSAGE XSCT command with result: [disconnect tcfchan#9], Result: [null, ]. Thread: Thread-529
|
|||
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:23:19.794
|
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!MESSAGE Updating toolusage
|
|||
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|
|||
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.795
|
|||
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|
!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-15
|
|||
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.803
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#10]. Thread: Worker-15
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.803
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.814
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.815
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.821
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.821
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.832
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.832
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.861
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.861
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.888
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.888
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.889
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#10]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.890
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.893
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.894
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!MESSAGE XSCT Command: [version -server], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.895
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.895
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!MESSAGE XSCT Command: [version], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.896
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.896
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.900
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.901
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.911
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.911
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.916
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.916
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.926
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.926
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.930
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.930
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.939
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.940
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.944
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.944
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.955
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.955
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.960
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.960
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.970
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.970
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.974
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.974
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.984
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.984
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.994
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.994
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.999
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:19.999
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:20.000
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:20.001
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:20.014
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:20.014
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.270
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_8]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.270
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.271
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.271
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.284
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.284
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!MESSAGE XSCT Command: [stop], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.285
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.286
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-15
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.521
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.521
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.527
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.527
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.542
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.543
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!MESSAGE XSCT Command: [rst -processor], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.583
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-15
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.583
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.596
|
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:21.596
|
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-15
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:23:22.951
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.075
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.089
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.090
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.091
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.091
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.095
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.095
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.106
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.106
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.111
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.111
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.121
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.121
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.125
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.125
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.134
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.135
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.139
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.139
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.149
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.149
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.153
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.154
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.163
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.163
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.173
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.174
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.187
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.187
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.189
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.189
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.206
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.207
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.704
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:35.705
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.719
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.737
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.747
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.747
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.759
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.759
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.770
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:38.770
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:49.957
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:49.982
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:50.006
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:50.006
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.379
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_9]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.380
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.381
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.381
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.393
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.394
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.604
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.604
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.628
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-11
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:51.630
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:54.269
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:54.271
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:26:55.277
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.278
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.287
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.287
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.299
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.299
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.305
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.305
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.317
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.317
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.334
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.335
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.358
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.358
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.359
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#12]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.359
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.363
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.363
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!MESSAGE XSCT Command: [version -server], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.364
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.364
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!MESSAGE XSCT Command: [version], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.365
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.365
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.368
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.368
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.379
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.379
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.383
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.383
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.393
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.393
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.397
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.397
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.406
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.406
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.411
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.411
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.420
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.421
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.424
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.424
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.434
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.434
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.438
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.438
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.447
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.448
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.458
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.459
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.459
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.460
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.461
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.462
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.474
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:55.474
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.834
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_10]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.834
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.836
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.836
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.848
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.848
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!MESSAGE XSCT Command: [stop], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.849
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!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:56.849
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.036
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.037
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.041
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.041
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.054
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.054
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.158
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!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-15
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.174
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:57.174
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.370
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.370
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.377
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.467
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.519
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.519
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!MESSAGE XSCT Command: [con], Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:26:58.532
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-15
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:26.267
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!MESSAGE XSCT Command: [disconnect tcfchan#12], Thread: Thread-693
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:26.269
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!MESSAGE XSCT command with result: [disconnect tcfchan#12], Result: [null, ]. Thread: Thread-693
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:38:27.290
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!MESSAGE Updating toolusage
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.291
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.298
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#13]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.298
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.319
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.319
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!MESSAGE XSCT Command: [version -server], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.320
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.320
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!MESSAGE XSCT Command: [version], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.321
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.322
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.326
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.326
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.337
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.337
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.342
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.342
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.352
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.352
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.357
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.357
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.367
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.367
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.371
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.371
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.381
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.381
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.386
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.386
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.395
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.395
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.405
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.405
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.406
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.406
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.408
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.408
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.426
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.426
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.912
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:27.912
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.919
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.934
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.958
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.958
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.968
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.969
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.978
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:30.979
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:42.164
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:42.189
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:42.208
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:42.209
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.573
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_11]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.574
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.575
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.575
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.587
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.587
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.754
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.755
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.760
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.760
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:43.761
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:48.846
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!MESSAGE XSCT Command: [disconnect tcfchan#13], Thread: Thread-736
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:48.848
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!MESSAGE XSCT command with result: [disconnect tcfchan#13], Result: [null, ]. Thread: Thread-736
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:38:49.867
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!MESSAGE Updating toolusage
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.869
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.877
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#14]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.877
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.889
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.889
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.895
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.895
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.913
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.913
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.932
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.932
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.962
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.962
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.963
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#14]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.964
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.967
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.968
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!MESSAGE XSCT Command: [version -server], Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.968
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.969
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!MESSAGE XSCT Command: [version], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.969
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.969
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.974
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.974
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.983
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.983
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.987
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.988
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.999
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:49.999
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.003
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.004
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.014
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.014
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.018
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.018
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.028
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.028
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.032
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.032
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.042
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.042
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.046
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.046
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.056
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.056
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.066
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.066
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.067
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.067
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.068
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.069
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.081
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:50.081
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.385
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_12]. Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.386
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.387
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.387
|
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-0
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.399
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.400
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.402
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.402
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.560
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.560
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.575
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.575
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.587
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.588
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.621
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.621
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.634
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:51.634
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!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:52.886
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!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:52.887
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:52.889
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:52.954
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:53.008
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:53.008
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!MESSAGE XSCT Command: [con], Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:38:53.013
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!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-0
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:14.455
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!MESSAGE XSCT Command: [disconnect tcfchan#14], Thread: Thread-792
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:14.457
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!MESSAGE XSCT command with result: [disconnect tcfchan#14], Result: [null, ]. Thread: Thread-792
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:40:15.460
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!MESSAGE Updating toolusage
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.461
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.467
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#15]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.468
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.483
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.484
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!MESSAGE XSCT Command: [version -server], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.496
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.496
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!MESSAGE XSCT Command: [version], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.497
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.497
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.503
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.503
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.514
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.514
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.518
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.518
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.528
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.528
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.532
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.532
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.542
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.542
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.546
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.546
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.556
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.556
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.559
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.559
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.568
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.569
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.579
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.579
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.580
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.580
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.582
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.582
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.599
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:15.599
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!MESSAGE XSCT Command: [rst -system], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:16.093
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!MESSAGE XSCT command with result: [rst -system], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:16.094
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!MESSAGE XSCT Command: [after 3000], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.107
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!MESSAGE XSCT command with result: [after 3000], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.125
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.133
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.133
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.144
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.144
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.155
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:19.156
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!MESSAGE XSCT Command: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Thread: ModalContext
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:30.338
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!MESSAGE XSCT command with result: [fpga -file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit], Result: [null, ]. Thread: ModalContext
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:30.362
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:30.385
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:30.386
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.682
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!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_13]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.682
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.684
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.684
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.703
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.704
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!MESSAGE XSCT Command: [ps7_init], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.863
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!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.863
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!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.869
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!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.869
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!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:31.870
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!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-17
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:34.438
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!MESSAGE XSCT Command: [disconnect tcfchan#15], Thread: Thread-835
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:34.440
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!MESSAGE XSCT command with result: [disconnect tcfchan#15], Result: [null, ]. Thread: Thread-835
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!ENTRY com.xilinx.sdk.utils 1 0 2022-11-25 21:40:35.454
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!MESSAGE Updating toolusage
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.454
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.458
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#16]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.458
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.468
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.469
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.473
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.473
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.483
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
|
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.484
|
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!MESSAGE XSCT Command: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.502
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!MESSAGE XSCT command with result: [targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==0} -index 1], Result: [null, ]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.503
|
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!MESSAGE XSCT Command: [fpga -state], Thread: Worker-5
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.520
|
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!MESSAGE XSCT command with result: [fpga -state], Result: [null, FPGA is configured]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.520
|
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!MESSAGE XSCT Command: [connect -url tcp:127.0.0.1:3121], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.521
|
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!MESSAGE XSCT command with result: [connect -url tcp:127.0.0.1:3121], Result: [null, tcfchan#16]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.521
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.525
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.525
|
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!MESSAGE XSCT Command: [version -server], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.525
|
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!MESSAGE XSCT command with result: [version -server], Result: [null, 2018.3]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.526
|
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!MESSAGE XSCT Command: [version], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.526
|
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!MESSAGE XSCT command with result: [version], Result: [null, xsct 2018.3
|
|||
|
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SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|||
|
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.]. Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.526
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.530
|
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.530
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.540
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.540
|
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.544
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.544
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.554
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.555
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.559
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.559
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.570
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.570
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.574
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.574
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.584
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.584
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.588
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.588
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.597
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.597
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!MESSAGE XSCT Command: [jtag targets -filter {level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.601
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!MESSAGE XSCT command with result: [jtag targets -filter {level == 0}], Result: [null, 1* Digilent JTAG-HS3 210299539789]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.601
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!MESSAGE XSCT Command: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.610
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!MESSAGE XSCT command with result: [jtag targets -filter {jtag_cable_name =~ "Digilent JTAG-HS3 210299539789" && level==1}], Result: [null, 2 arm_dap (idcode 4ba00477 irlen 4)
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3 xc7z035 (idcode 23732093 irlen 6 fpga)]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.611
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!MESSAGE XSCT Command: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.620
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!MESSAGE XSCT command with result: [jtag targets -set -filter {name =~ "Digilent JTAG-HS3 210299539789" && level == 0}], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.620
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!MESSAGE XSCT Command: [jtag frequency], Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.621
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!MESSAGE XSCT command with result: [jtag frequency], Result: [null, 10000000]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.621
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!MESSAGE XSCT Command: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.622
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!MESSAGE XSCT command with result: [source L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.623
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!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.655
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!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:35.656
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!MESSAGE XSCT Command: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Thread: Worker-5
|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.883
|
|||
|
|
!MESSAGE XSCT command with result: [loadhw -hw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]], Result: [null, design_1_wrapper_14]. Thread: Worker-5
|
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|
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|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.883
|
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!MESSAGE XSCT Command: [configparams force-mem-access 1], Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.884
|
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!MESSAGE XSCT command with result: [configparams force-mem-access 1], Result: [null, ]. Thread: Worker-5
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.884
|
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|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
|||
|
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.897
|
|||
|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.897
|
|||
|
|
!MESSAGE XSCT Command: [stop], Thread: Worker-5
|
|||
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|
|||
|
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!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.898
|
|||
|
|
!MESSAGE XSCT command with result: [stop], Result: [null, ]. Thread: Worker-5
|
|||
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:36.898
|
|||
|
|
!MESSAGE XSCT Command: [ps7_init], Thread: Worker-5
|
|||
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.093
|
|||
|
|
!MESSAGE XSCT command with result: [ps7_init], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.093
|
|||
|
|
!MESSAGE XSCT Command: [ps7_post_config], Thread: Worker-5
|
|||
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.098
|
|||
|
|
!MESSAGE XSCT command with result: [ps7_post_config], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.098
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.111
|
|||
|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
|
|||
|
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|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.111
|
|||
|
|
!MESSAGE XSCT Command: [rst -processor], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.191
|
|||
|
|
!MESSAGE XSCT command with result: [rst -processor], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.191
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.205
|
|||
|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:37.205
|
|||
|
|
!MESSAGE XSCT Command: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.456
|
|||
|
|
!MESSAGE XSCT command with result: [dow L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/spectrum/Debug/spectrum.elf], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.456
|
|||
|
|
!MESSAGE XSCT Command: [configparams force-mem-access 0], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.463
|
|||
|
|
!MESSAGE XSCT command with result: [configparams force-mem-access 0], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.519
|
|||
|
|
!MESSAGE XSCT Command: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.570
|
|||
|
|
!MESSAGE XSCT command with result: [targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS3 210299539789"} -index 0], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.570
|
|||
|
|
!MESSAGE XSCT Command: [con], Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 21:40:38.576
|
|||
|
|
!MESSAGE XSCT command with result: [con], Result: [null, ]. Thread: Worker-5
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 22:00:00.605
|
|||
|
|
!MESSAGE XSCT Command: [disconnect tcfchan#16], Thread: Thread-894
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-25 22:00:00.609
|
|||
|
|
!MESSAGE XSCT command with result: [disconnect tcfchan#16], Result: [null, ]. Thread: Thread-894
|
|||
|
|
!SESSION 2022-11-26 21:06:16.987 -----------------------------------------------
|
|||
|
|
eclipse.buildId=2018.3
|
|||
|
|
java.version=1.8.0_112
|
|||
|
|
java.vendor=Oracle Corporation
|
|||
|
|
BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=zh_CN
|
|||
|
|
Command-line arguments: -os win32 -ws win32 -arch x86_64 -data L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.ui 2 0 2022-11-26 21:06:24.808
|
|||
|
|
!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-26 21:06:24.808
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
|
|
|
|||
|
|
!ENTRY org.eclipse.ui 2 0 2022-11-26 21:06:25.296
|
|||
|
|
!MESSAGE Warnings while parsing the commands from the 'org.eclipse.ui.commands' and 'org.eclipse.ui.actionDefinitions' extension points.
|
|||
|
|
!SUBENTRY 1 org.eclipse.ui 2 0 2022-11-26 21:06:25.296
|
|||
|
|
!MESSAGE Commands should really have a category: plug-in='com.xilinx.sdk.appwiz', id='com.xilinx.sdk.app.commands.ChangeAtfBuiltReferences', categoryId='com.xilinx.sdk.app.commands.category'
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:30.811
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::init_repo], Thread: Worker-1
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:30.811
|
|||
|
|
!MESSAGE XSCT Command: [set sdk::sdk_chan tcfchan#0], Thread: Thread-17
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:32.531
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::init_repo], Result: [null, ]. Thread: Worker-1
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:32.532
|
|||
|
|
!MESSAGE XSCT command with result: [set sdk::sdk_chan tcfchan#0], Result: [null, tcfchan#0]. Thread: Thread-17
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:32.532
|
|||
|
|
!MESSAGE XSCT Command: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Thread: Thread-17
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:32.534
|
|||
|
|
!MESSAGE XSCT command with result: [setws L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk], Result: [null, ]. Thread: Thread-17
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:32.549
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-0
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:06:35.859
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::openhw L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, ]. Thread: Worker-0
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.773
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.776
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_design_properties -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"device": "7z035",
|
|||
|
|
"family": "zynq",
|
|||
|
|
"timestamp": "Thu Nov 24 17:05:01 2022",
|
|||
|
|
"vivado_version": "2018.3",
|
|||
|
|
"part": "xc7z035ffg676-2",
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 1 0 2022-11-26 21:07:29.848
|
|||
|
|
!MESSAGE Updating toolusage
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.849
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.867
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_periphs -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"adc_read_0": {"hier_name": "adc_read_0",
|
|||
|
|
"type": "adc_read",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dma_0": {"hier_name": "axi_dma_0",
|
|||
|
|
"type": "axi_dma",
|
|||
|
|
"version": "7.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {"hier_name": "axi_dynclk_0",
|
|||
|
|
"type": "axi_dynclk",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0": {"hier_name": "axi_gpio_0",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"hier_name": "axi_gpio_1",
|
|||
|
|
"type": "axi_gpio",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"axi_smc": {"hier_name": "axi_smc",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_smc1": {"hier_name": "axi_smc1",
|
|||
|
|
"type": "smartconnect",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"hier_name": "axi_vdma_0",
|
|||
|
|
"type": "axi_vdma",
|
|||
|
|
"version": "6.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"clk_wiz_0": {"hier_name": "clk_wiz_0",
|
|||
|
|
"type": "clk_wiz",
|
|||
|
|
"version": "6.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"direct_fft_0": {"hier_name": "direct_fft_0",
|
|||
|
|
"type": "direct_fft",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"key_ec11_0": {"hier_name": "key_ec11_0",
|
|||
|
|
"type": "key_ec11",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"processing_system7_0": {"hier_name": "processing_system7_0",
|
|||
|
|
"type": "processing_system7",
|
|||
|
|
"version": "5.5",
|
|||
|
|
"ip_type": "",
|
|||
|
|
},
|
|||
|
|
"ps7_0_axi_periph": {"hier_name": "ps7_0_axi_periph",
|
|||
|
|
"type": "axi_interconnect",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"rgb2dvi_0": {"hier_name": "rgb2dvi_0",
|
|||
|
|
"type": "rgb2dvi",
|
|||
|
|
"version": "1.3",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_100M": {"hier_name": "rst_ps7_0_100M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_142M": {"hier_name": "rst_ps7_0_142M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"rst_ps7_0_250M": {"hier_name": "rst_ps7_0_250M",
|
|||
|
|
"type": "proc_sys_reset",
|
|||
|
|
"version": "5.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0": {"hier_name": "system_ila_0",
|
|||
|
|
"type": "system_ila",
|
|||
|
|
"version": "1.1",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"util_vector_logic_0": {"hier_name": "util_vector_logic_0",
|
|||
|
|
"type": "util_vector_logic",
|
|||
|
|
"version": "2.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_axi4s_vid_out_0": {"hier_name": "v_axi4s_vid_out_0",
|
|||
|
|
"type": "v_axi4s_vid_out",
|
|||
|
|
"version": "4.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"v_tc_0": {"hier_name": "v_tc_0",
|
|||
|
|
"type": "v_tc",
|
|||
|
|
"version": "6.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"window_0": {"hier_name": "window_0",
|
|||
|
|
"type": "window",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"xlconcat_0": {"hier_name": "xlconcat_0",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_clockc_0": {"hier_name": "ps7_clockc_0",
|
|||
|
|
"type": "ps7_clockc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"hier_name": "ps7_uart_1",
|
|||
|
|
"type": "ps7_uart",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"hier_name": "ps7_pl310_0",
|
|||
|
|
"type": "ps7_pl310",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"hier_name": "ps7_pmu_0",
|
|||
|
|
"type": "ps7_pmu",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"hier_name": "ps7_qspi_0",
|
|||
|
|
"type": "ps7_qspi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"hier_name": "ps7_qspi_linear_0",
|
|||
|
|
"type": "ps7_qspi_linear",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_axi_interconnect_0": {"hier_name": "ps7_axi_interconnect_0",
|
|||
|
|
"type": "ps7_axi_interconnect",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "BUS",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_0": {"hier_name": "ps7_cortexa9_0",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"hier_name": "ps7_cortexa9_1",
|
|||
|
|
"type": "ps7_cortexa9",
|
|||
|
|
"version": "5.2",
|
|||
|
|
"ip_type": "PROCESSOR",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"hier_name": "ps7_ddr_0",
|
|||
|
|
"type": "ps7_ddr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"hier_name": "ps7_sd_0",
|
|||
|
|
"type": "ps7_sdio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"hier_name": "ps7_gpio_0",
|
|||
|
|
"type": "ps7_gpio",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"hier_name": "ps7_ddrc_0",
|
|||
|
|
"type": "ps7_ddrc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"hier_name": "ps7_dev_cfg_0",
|
|||
|
|
"type": "ps7_dev_cfg",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"hier_name": "ps7_xadc_0",
|
|||
|
|
"type": "ps7_xadc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"hier_name": "ps7_ocmc_0",
|
|||
|
|
"type": "ps7_ocmc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"hier_name": "ps7_coresight_comp_0",
|
|||
|
|
"type": "ps7_coresight_comp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"hier_name": "ps7_gpv_0",
|
|||
|
|
"type": "ps7_gpv",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"hier_name": "ps7_scuc_0",
|
|||
|
|
"type": "ps7_scuc",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"hier_name": "ps7_globaltimer_0",
|
|||
|
|
"type": "ps7_globaltimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"hier_name": "ps7_intc_dist_0",
|
|||
|
|
"type": "ps7_intc_dist",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"hier_name": "ps7_l2cachec_0",
|
|||
|
|
"type": "ps7_l2cachec",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"hier_name": "ps7_dma_s",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"hier_name": "ps7_iop_bus_config_0",
|
|||
|
|
"type": "ps7_iop_bus_config",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"hier_name": "ps7_ram_0",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"hier_name": "ps7_ram_1",
|
|||
|
|
"type": "ps7_ram",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "MEMORY_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"hier_name": "ps7_scugic_0",
|
|||
|
|
"type": "ps7_scugic",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "INTERRUPT_CNTLR",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"hier_name": "ps7_scutimer_0",
|
|||
|
|
"type": "ps7_scutimer",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"hier_name": "ps7_scuwdt_0",
|
|||
|
|
"type": "ps7_scuwdt",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"hier_name": "ps7_slcr_0",
|
|||
|
|
"type": "ps7_slcr",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"hier_name": "ps7_dma_ns",
|
|||
|
|
"type": "ps7_dma",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"hier_name": "ps7_afi_0",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"hier_name": "ps7_afi_1",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"hier_name": "ps7_afi_2",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"hier_name": "ps7_afi_3",
|
|||
|
|
"type": "ps7_afi",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"ps7_m_axi_gp0": {"hier_name": "ps7_m_axi_gp0",
|
|||
|
|
"type": "ps7_m_axi_gp",
|
|||
|
|
"version": "1.00.a",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_g_inst": {"hier_name": "system_ila_0/system_ila_0_g_inst",
|
|||
|
|
"type": "gigantic_mux",
|
|||
|
|
"version": "1.0",
|
|||
|
|
"ip_type": "MONITOR",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_ila_lib": {"hier_name": "system_ila_0/system_ila_0_ila_lib",
|
|||
|
|
"type": "ila",
|
|||
|
|
"version": "6.2",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_ar": {"hier_name": "system_ila_0/system_ila_0_slot_0_ar",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_aw": {"hier_name": "system_ila_0/system_ila_0_slot_0_aw",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_b": {"hier_name": "system_ila_0/system_ila_0_slot_0_b",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_r": {"hier_name": "system_ila_0/system_ila_0_slot_0_r",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
"system_ila_0_slot_0_w": {"hier_name": "system_ila_0/system_ila_0_slot_0_w",
|
|||
|
|
"type": "xlconcat",
|
|||
|
|
"version": "2.1",
|
|||
|
|
"ip_type": "PERIPHERAL",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.872
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.876
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_ps_config_params -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"PCW_APU_PERIPHERAL_FREQMHZ": "666.666666",
|
|||
|
|
"PCW_DDR_HPRLPR_QUEUE_PARTITION": "HPR(0)/LPR(32)",
|
|||
|
|
"PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": "15",
|
|||
|
|
"PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_DDR_PORT0_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT1_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT2_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_PORT3_HPR_ENABLE": "0",
|
|||
|
|
"PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": "2",
|
|||
|
|
"PCW_FPGA0_PERIPHERAL_FREQMHZ": "100",
|
|||
|
|
"PCW_UIPARAM_DDR_BUS_WIDTH": "32 Bit",
|
|||
|
|
"PCW_UIPARAM_DDR_FREQ_MHZ": "533.333333",
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.877
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.925
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.930
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.940
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_addr_ranges -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0], Result: [null, {"axi_dma_0_S_AXI_LITE": {"name": "axi_dma_0",
|
|||
|
|
"base": "0x40400000",
|
|||
|
|
"high": "0x4040FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_0_S_AXI": {"name": "axi_gpio_0",
|
|||
|
|
"base": "0x41200000",
|
|||
|
|
"high": "0x4120FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1_S_AXI": {"name": "axi_gpio_1",
|
|||
|
|
"base": "0x41210000",
|
|||
|
|
"high": "0x4121FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0_S_AXI_LITE": {"name": "axi_vdma_0",
|
|||
|
|
"base": "0x43000000",
|
|||
|
|
"high": "0x4300FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "S_AXI_LITE",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0_s00_axi": {"name": "axi_dynclk_0",
|
|||
|
|
"base": "0x43C00000",
|
|||
|
|
"high": "0x43C0FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "s00_axi",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"v_tc_0_ctrl": {"name": "v_tc_0",
|
|||
|
|
"base": "0x43C10000",
|
|||
|
|
"high": "0x43C1FFFF",
|
|||
|
|
"size": "65536",
|
|||
|
|
"slaveintf": "ctrl",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {"name": "ps7_afi_0",
|
|||
|
|
"base": "0xF8008000",
|
|||
|
|
"high": "0xF8008FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_1": {"name": "ps7_afi_1",
|
|||
|
|
"base": "0xF8009000",
|
|||
|
|
"high": "0xF8009FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_2": {"name": "ps7_afi_2",
|
|||
|
|
"base": "0xF800A000",
|
|||
|
|
"high": "0xF800AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_afi_3": {"name": "ps7_afi_3",
|
|||
|
|
"base": "0xF800B000",
|
|||
|
|
"high": "0xF800BFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_coresight_comp_0": {"name": "ps7_coresight_comp_0",
|
|||
|
|
"base": "0xF8800000",
|
|||
|
|
"high": "0xF88FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddrc_0": {"name": "ps7_ddrc_0",
|
|||
|
|
"base": "0xF8006000",
|
|||
|
|
"high": "0xF8006FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dev_cfg_0": {"name": "ps7_dev_cfg_0",
|
|||
|
|
"base": "0xF8007000",
|
|||
|
|
"high": "0xF80070FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_ns": {"name": "ps7_dma_ns",
|
|||
|
|
"base": "0xF8004000",
|
|||
|
|
"high": "0xF8004FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_dma_s": {"name": "ps7_dma_s",
|
|||
|
|
"base": "0xF8003000",
|
|||
|
|
"high": "0xF8003FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_globaltimer_0": {"name": "ps7_globaltimer_0",
|
|||
|
|
"base": "0xF8F00200",
|
|||
|
|
"high": "0xF8F002FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpio_0": {"name": "ps7_gpio_0",
|
|||
|
|
"base": "0xE000A000",
|
|||
|
|
"high": "0xE000AFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_gpv_0": {"name": "ps7_gpv_0",
|
|||
|
|
"base": "0xF8900000",
|
|||
|
|
"high": "0xF89FFFFF",
|
|||
|
|
"size": "1048576",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_intc_dist_0": {"name": "ps7_intc_dist_0",
|
|||
|
|
"base": "0xF8F01000",
|
|||
|
|
"high": "0xF8F01FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_iop_bus_config_0": {"name": "ps7_iop_bus_config_0",
|
|||
|
|
"base": "0xE0200000",
|
|||
|
|
"high": "0xE0200FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_l2cachec_0": {"name": "ps7_l2cachec_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ocmc_0": {"name": "ps7_ocmc_0",
|
|||
|
|
"base": "0xF800C000",
|
|||
|
|
"high": "0xF800CFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pl310_0": {"name": "ps7_pl310_0",
|
|||
|
|
"base": "0xF8F02000",
|
|||
|
|
"high": "0xF8F02FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_pmu_0": {"name": "ps7_pmu_0",
|
|||
|
|
"base": "0xF8893000",
|
|||
|
|
"high": "0xF8893FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_0": {"name": "ps7_qspi_0",
|
|||
|
|
"base": "0xE000D000",
|
|||
|
|
"high": "0xE000DFFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_qspi_linear_0": {"name": "ps7_qspi_linear_0",
|
|||
|
|
"base": "0xFC000000",
|
|||
|
|
"high": "0xFCFFFFFF",
|
|||
|
|
"size": "16777216",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "FLASH",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuc_0": {"name": "ps7_scuc_0",
|
|||
|
|
"base": "0xF8F00000",
|
|||
|
|
"high": "0xF8F000FC",
|
|||
|
|
"size": "253",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scugic_0": {"name": "ps7_scugic_0",
|
|||
|
|
"base": "0xF8F00100",
|
|||
|
|
"high": "0xF8F001FF",
|
|||
|
|
"size": "256",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scutimer_0": {"name": "ps7_scutimer_0",
|
|||
|
|
"base": "0xF8F00600",
|
|||
|
|
"high": "0xF8F0061F",
|
|||
|
|
"size": "32",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_scuwdt_0": {"name": "ps7_scuwdt_0",
|
|||
|
|
"base": "0xF8F00620",
|
|||
|
|
"high": "0xF8F006FF",
|
|||
|
|
"size": "224",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_sd_0": {"name": "ps7_sd_0",
|
|||
|
|
"base": "0xE0100000",
|
|||
|
|
"high": "0xE0100FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_slcr_0": {"name": "ps7_slcr_0",
|
|||
|
|
"base": "0xF8000000",
|
|||
|
|
"high": "0xF8000FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_uart_1": {"name": "ps7_uart_1",
|
|||
|
|
"base": "0xE0001000",
|
|||
|
|
"high": "0xE0001FFF",
|
|||
|
|
"size": "4096",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_xadc_0": {"name": "ps7_xadc_0",
|
|||
|
|
"base": "0xF8007100",
|
|||
|
|
"high": "0xF8007120",
|
|||
|
|
"size": "33",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "REGISTER",
|
|||
|
|
"flags": "3",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ddr_0": {"name": "ps7_ddr_0",
|
|||
|
|
"base": "0x00100000",
|
|||
|
|
"high": "0x3FFFFFFF",
|
|||
|
|
"size": "1072693248",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_0": {"name": "ps7_ram_0",
|
|||
|
|
"base": "0x00000000",
|
|||
|
|
"high": "0x0002FFFF",
|
|||
|
|
"size": "196608",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
"ps7_ram_1": {"name": "ps7_ram_1",
|
|||
|
|
"base": "0xFFFF0000",
|
|||
|
|
"high": "0xFFFFFDFF",
|
|||
|
|
"size": "65024",
|
|||
|
|
"slaveintf": "",
|
|||
|
|
"type": "MEMORY",
|
|||
|
|
"flags": "7",
|
|||
|
|
"segment": "",
|
|||
|
|
"acctype": "",
|
|||
|
|
"tz": "",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.942
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.944
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_ENABLED], Result: [null, ]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.945
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.946
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_EVENT_COUNTERS], Result: [null, ]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.946
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.947
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_LATENCY_COUNTERS], Result: [null, ]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.948
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.949
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_DEBUG_COUNTER_WIDTH], Result: [null, ]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.949
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.966
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_FREQ], Result: [null, ]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.967
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.968
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_hw_param_value L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_0 C_CPU_CLK_FREQ_HZ], Result: [null, 666666687]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.969
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.971
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_cpu_nr -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf], Result: [null, {"ps7_cortexa9_0": {"bscan": "",
|
|||
|
|
"index": "0",
|
|||
|
|
},
|
|||
|
|
"ps7_cortexa9_1": {"bscan": "",
|
|||
|
|
"index": "1",
|
|||
|
|
},
|
|||
|
|
}]. Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:29.971
|
|||
|
|
!MESSAGE XSCT Command: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Thread: Worker-2
|
|||
|
|
|
|||
|
|
!ENTRY com.xilinx.sdk.utils 0 0 2022-11-26 21:07:30.012
|
|||
|
|
!MESSAGE XSCT command with result: [::hsi::utils::get_all_register_data -json L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.sdk/design_1_wrapper_hw_platform_0/system.hdf ps7_cortexa9_1], Result: [null, {"axi_dma_0": {"MM2S_DMACR": {"description": "MM2S DMA Control Register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
|
|||
|
|
This bit is non functional when DMA operates in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable.
|
|||
|
|
0 - Error Interrupt disabled
|
|||
|
|
1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_DMASR": {"description": "MM2S DMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Scatter Gather Enabled
|
|||
|
|
0 - Scatter Gather not enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it.
|
|||
|
|
0 - No error Interrupt.
|
|||
|
|
1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x18",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA_MSB": {"description": "MM2S Source Address Register",
|
|||
|
|
"address_offset": "0x1C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Source_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_LENGTH": {"description": "MM2S DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMACR": {"description": "S2MM DMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop control for controlling running and stopping of the DMA channel.
|
|||
|
|
0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
|
|||
|
|
For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
|
|||
|
|
The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
|
|||
|
|
1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
|
|||
|
|
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Keyhole": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
|
|||
|
|
This bit is non functional when DMA is used in multichannel mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Cyclic_BD_Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
|
|||
|
|
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThreshold": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
|
|||
|
|
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
|
|||
|
|
Note: Setting this value to zero disables the delay timer interrupt.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DMASR": {"description": "S2MM DMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1
|
|||
|
|
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Idle": {"access": "read-only",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Channel Idle. Indicates the state of AXI DMA operations.
|
|||
|
|
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
|
|||
|
|
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIncld": {"access": "read-only",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMAIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
|
|||
|
|
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGIntErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGSlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "9",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SGDecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "10",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IOC_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Dly_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
|
|||
|
|
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQThresholdSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Threshold Status. Indicates current interrupt threshold value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelaySts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Time Status. Indicates current interrupt delay time value.
|
|||
|
|
Note: Applicable only when Scatter Gather is enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA": {"description": "S2MM DMA Destination Address Register",
|
|||
|
|
"address_offset": "0x48",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_DA_MSB": {"description": "S2MM Destination Address Register",
|
|||
|
|
"address_offset": "0x4C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Destination_Address": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
|
|||
|
|
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_LENGTH": {"description": "S2MM DMA Transfer Length Register",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Length": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "26",
|
|||
|
|
"desc": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
|
|||
|
|
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
|
|||
|
|
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_dynclk_0": {},
|
|||
|
|
"axi_gpio_0": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "1",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "4",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_gpio_1": {"GPIO_DATA": {"description": "Channel-1 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO_TRI": {"description": "Channel-1 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0x4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "2",
|
|||
|
|
"fields": {"Channel-1 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "2",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_DATA": {"description": "Channel-2 AXI GPIO Data register",
|
|||
|
|
"address_offset": "0x8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO DATA": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO Data Register.
|
|||
|
|
For each I/O bit programmed as input
|
|||
|
|
R - Reads value on the input pin.
|
|||
|
|
W - No effect.
|
|||
|
|
For each I/O bit programmed as output
|
|||
|
|
R - Reads value on GPIO_O pins
|
|||
|
|
W - Writes value to the corresponding AXI GPIO
|
|||
|
|
data register bit and output pin
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GPIO2_TRI": {"description": "Channel-2 AXI GPIO 3-State Control register",
|
|||
|
|
"address_offset": "0xC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-2 GPIO TRI": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "AXI GPIO 3-State Control Register
|
|||
|
|
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"GIER": {"description": "Global Interrupt Enable register",
|
|||
|
|
"address_offset": "0x11C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Global Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "31",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Master enable for the device interrupt output
|
|||
|
|
0 - Disabled
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_IER": {"description": "IP Interrupt Enable register",
|
|||
|
|
"address_offset": "0x128",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 1 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Enable": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enable Channel 2 Interrupt
|
|||
|
|
0 - Disabled (masked)
|
|||
|
|
1 - Enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"IP_ISR": {"description": "IP Interrupt Status register",
|
|||
|
|
"address_offset": "0x120",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Channel-1 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 1 Interrupt Status
|
|||
|
|
0 - No Channel 1 input interrupt
|
|||
|
|
1 - Channel 1 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Channel-2 Interrupt Status": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Channel 2 Interrupt Status
|
|||
|
|
0 - No Channel 2 input interrupt
|
|||
|
|
1 - Channel 2 input interrupt
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"axi_vdma_0": {"MM2S_VDMACR": {"description": "MM2S VDMA Control Register",
|
|||
|
|
"address_offset": "0x00",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA MM2S channel. Setting this bit to a 1 causes the AXI VDMA MM2S channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the MM2S channel. After completion of a soft reset all MM2S registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by MM2S. 1 - Genlock or Dynamic Genlock Synchronization enabled. MM2S synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the MM2S channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the MM2S channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when MM2S channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the MM2S channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the MM2S channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( m_axis_mm2s_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VDMASR": {"description": "MM2S VDMA Status Register",
|
|||
|
|
"address_offset": "0x04",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected This error occurs if mm2s_fsync is received before the completion of the frame on the streaming interface.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_REG_INDEX": {"description": "MM2S Register Index",
|
|||
|
|
"address_offset": "0x14",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"MM2S_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0x5C to 0x98 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0x5C to 0x98 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"PARK_PTR_REG": {"description": "Park Pointer Register",
|
|||
|
|
"address_offset": "0x28",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RdFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Pointer Reference. When Parked (MM2S_VDMACR.Circular_Park = 0) the MM2S channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmPtrRef": {"access": "read-only",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Pointer Reference. When Parked (S2MM_VDMACR.Circular_Park = 0) the S2MM channel parks on the buffer referenced by this frame number.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdFrmStore": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Read Frame Store number. Indicates the frame number being operated on by the MM2S channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"WrFrmStore": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Write Frame Store number. Indicates current frame number being operated on by the S2MM channel. During VDMA operations this value continually updates as each frame is processed. During error conditions, the value is updated with the frame number being operated on when the error occurred. It will again start tracking the current frame number when all errors are cleared.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"VDMA_VERSION": {"description": "AXI VDMA Version Register",
|
|||
|
|
"address_offset": "0x2C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Xilinx_Internal": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Reserved for Internal Use Only. Integer value from 0 to 9,999.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Minor_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "20",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Two separate 4-bit hexadecimal values. 00 = 00h, 01 = 01h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Major_Version": {"access": "read-only",
|
|||
|
|
"bit_offset": "28",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Single 4-bit hexadecimal value. v1 = 1h, v2=2h, v3=3h, and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMACR": {"description": "S2MM VDMA Control Register",
|
|||
|
|
"address_offset": "0x30",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"RS": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Run / Stop controls the running and stopping of the VDMA channel. For any VDMA operations to commence, the AXI VDMA engine must be running (VDMACR.RS=1). 0 - Stop. VDMA stops when current (if any) VDMA operations are complete. The halted bit in the VDMA Status Register asserts to 1 when the VDMA engine is halted. This bit gets cleared by the AXI VDMA hardware when an AXI4 Slave response error occurs. The CPU can also choose to clear this bit to stop VDMA operations. 1 - Run. Start VDMA operations. The halted bit in the VDMA Status Register deasserts to 0 when the VDMA engine begins operations. Note: On Run/Stop clear, in-progress stream transfers might terminate early.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Circular_Park": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Indicates frame buffer Circular mode or frame buffer Park mode.
|
|||
|
|
0 - Park Mode. Engine will park on frame buffer referenced by PARK_PTR_REG.RdFrmPntrRef.
|
|||
|
|
1 - Circular Mode. Engine continuously circles through frame buffers.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Reset": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Soft reset for AXI VDMA S2MM channel. Setting this bit to a 1 causes the AXI VDMA S2MM channel to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream reset output is asserted. Setting VDMACR.Reset = 1 only resets the S2MM channel. After completion of a soft reset all S2MM registers and bits are in the default state. This bit will be zero at the end of the reset cycle. 0 - Normal operation 1 - Reset in progress.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables Genlock or Dynamic Genlock Synchronization. 0 - Genlock or Dynamic Genlock Synchronization disabled. Genlock input is ignored by S2MM. 1 - Genlock or Dynamic Genlock Synchronization enabled. S2MM synchronized to Genlock frame input. Note: This value is valid only when the channel is configured as Genlock Slave or Dynamic Genlock Master or Dynamic Genlock Slave. If configured for Genlock Master mode, this bit is reserved and always reads as zero.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrameCntEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Configures the S2MM channel to allow only a IRQFrameCount number of transfers to occur. After IRQFrameCount frames have been transferred, the S2MM channel halts, DMACR.RS bit is cleared to 0, and DMASR.Halted asserts to 1 when the channel has completely halted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"GenlockSrc": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Selects internal or external genlock bus. This bit is set by default when both channels are enabled and are configured as a valid Genlock pair. 0 - External Genlock 1 - Internal Genlock
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"RdPntrNum": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "4",
|
|||
|
|
"desc": "Indicates the master in control when S2MM channel is configured for Genlock slave/Dynamic Genlock Master/Dynamic Genlock Slave or reserved otherwise. 0000b - Controlling entity is Entity 1 0001b - Controller entity is Entity 2 0010b - Controller entity is Entity 3 and so on.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Complete Interrupt Enable. When set to 1, allows DMASR.FrmCnt_Irq to generate an interrupt out when IRQFrameCount value reaches zero. 0 - Frame Count Interrupt disabled 1 - Frame Count Interrupt enabled
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay Count Interrupt Enable. When set to 1, allows DMASR.DlyCnt_Irq to generate an interrupt out. 0 - Delay Count Interrupt disabled 1 - Delay Count Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_IrqEn": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error Interrupt Enable. When set to 1, allows VDMASR.Err_Irq to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Repeat_En": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Enables repeat or advance frame when AXI VDMA encounters a frame error. This is applicable when AXI VDMA is configured in Genlock Master or Dynamic Genlock Master. 0 - Advance to next frame on frame errors 1 - Repeat previous frame on frame errors
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt threshold. When a frame transfer starts, an internal counter counts down from the Interrupt Frame Count setting.
|
|||
|
|
When the count reaches zero, an interrupt out is generated by the S2MM channel. When a value different than the current IRQFrameCount is written to this field, the internal frame counter is reset to the new value.
|
|||
|
|
The minimum setting for the count is 0x01. A write of 0x00 to this register sets the count to 0x01.
|
|||
|
|
When DMACR.FrameCntEn = 1, this value determines the number of frame buffers to process.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCount": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "This value is used for setting the interrupt delay count value. The delay count interrupt is a mechanism for causing the S2MM channel to generate an interrupt after the delay period has expired. The timer begins counting either upon receipt of frame sync (external fsync mode) or completion of vsize lines (free run mode). It resets with a subsequent start-of-packet ( s_axis_s2mm_tvalid ) assertion. When a value different than the current IRQDelayCount is written to this field, the internal delay counter is reset to the new value.
|
|||
|
|
Setting this value to zero disables the delay counter interrupt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMASR": {"description": "S2MM VDMA Status Register",
|
|||
|
|
"address_offset": "0x34",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Halted": {"access": "read-only",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Channel Halted.
|
|||
|
|
Indicates the run/stop state of the VDMA channel.
|
|||
|
|
0 - VDMA channel running
|
|||
|
|
1 - VDMA channel halted. This bit gets set when VDMACR.RS = 0. There can be a lag of time between when VDMACR.RS = 0 and when VDMASR.Halted = 1.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMAIntErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "4",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Internal Error. 0 - No VDMA Internal Errors. 1 - VDMA Internal Error detected. This error occurs during one of the following conditions. (a) HSIZE or VSIZE register were written zeros or (b) Internal error received from helper core axi_datamover or (c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr). In case (a) and/or (b) channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared).
|
|||
|
|
To restart the channel, soft or hard reset is required.
|
|||
|
|
In case (c), channel does not stop or halt.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMASlvErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "5",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Slave Error. 0 - No VDMA Slave Errors. 1 - VDMA Slave Error detected. VDMA Engine halts. This error occurs if the slave read from the Memory Map interface issues a Slave Error.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"VDMADecErr": {"access": "read-only",
|
|||
|
|
"bit_offset": "6",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "VDMA Decode Error. This error occurs if the address request is to an invalid address. 0 = No VDMA Decode Errors. 1 = VDMA Decode Error detected. VDMA channel halts.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "7",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Early Error 0 - No start-of-frame Error 1 - Start of Frame Early Error detected. VDMA does not halt. This error occurs if incoming frame size is lesser than programmed vsize value. Write 1 to Clear in flush on fsync mode and Read Only otherwise.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "8",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Early Error. 0 - No End of Line Early Error 1 - End of Line Early Error detected. VDMA does not halt. This error occurs if the incoming line size is lesser than the programmed hsize value. Write 1 to clear.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"SOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "11",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Start of Frame Late Error. 0 - No start-of-frame Late Error 1 - Start of Frame Late Error detected. VDMA does not halt. This error occurs if the incoming frame size is greater than the programmed vsize value. Write 1 to Clear in flush on fsync mode.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"FrmCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "12",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Frame Count Interrupt. 0 - No Frame Count Interrupt. 1 - Frame Count Interrupt detected. If enabled (DMACR.FrmCnt_IrqEn = 1) and if the interrupt threshold has been met, an interrupt out is generated.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"DlyCnt_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "13",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Delay. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. If enabled (DMACR.DlyCnt_IrqEn = 1), an interrupt out is generated when the delay count reaches its programmed value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Err_Irq": {"access": "read-write",
|
|||
|
|
"bit_offset": "14",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "Interrupt on Error. 0 - No error Interrupt. 1 - Error interrupt detected. If enabled (VDMACR.Err_IrqEn = 1), an interrupt out is generated when an error is detected.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"EOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "15",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "End of Line Late Error. 0 - No End of Line Late Error 1 - End of Line Late Error detected. VDMA does not halt. This error occurs if the incoming line size is greater than the programmed hsize value. Write 1 to clear
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQFrameCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "16",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Frame Count Status. Indicates current interrupt frame count value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQDelayCntSts": {"access": "read-only",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "8",
|
|||
|
|
"desc": "Interrupt Delay Count Status. Indicates current interrupt delay time value.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VDMA_IRQ_MASK": {"description": "S2MM Error Interrupt Mask Register",
|
|||
|
|
"address_offset": "0x3C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"IRQMaskSOFEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLEarlyErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "1",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to EOLEarlyErr.
|
|||
|
|
0 - Does not mask interrupt due to EOLEarlyErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskSOFLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "2",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 - Masks interrupt due to SOFLateErr.
|
|||
|
|
0 - Does not mask interrupt due to SOFLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"IRQMaskEOLLateErr": {"access": "read-write",
|
|||
|
|
"bit_offset": "3",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "1 = Masks interrupt due to EOLLateErr.
|
|||
|
|
0 = Does not mask interrupt due to EOLLateErr.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_REG_INDEX": {"description": "S2MM Register Index",
|
|||
|
|
"address_offset": "0x44",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"S2MM_Reg_Index": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "1",
|
|||
|
|
"desc": "When Frame Buffers is greater than 16
|
|||
|
|
0 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 1 to 16.
|
|||
|
|
1 - Any write or read access between 0xAC to 0xE8 accesses the Start Address 17 to 32.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_VSIZE": {"description": "MM2S Vertical Size",
|
|||
|
|
"address_offset": "0x50",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_HSIZE": {"description": "MM2S Horizontal Size",
|
|||
|
|
"address_offset": "0x54",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when MM2S_VSIZE is written causes a VDMAIntErr to be flagged in the MM2S_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_FRMDLY_STRIDE": {"description": "MM2S Frame Delay and Stride",
|
|||
|
|
"address_offset": "0x58",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than MM2S_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA1": {"description": "MM2S Start Address Register 1",
|
|||
|
|
"address_offset": "0x5C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA2": {"description": "MM2S Start Address Register 2",
|
|||
|
|
"address_offset": "0x60",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA3": {"description": "MM2S Start Address Register 3",
|
|||
|
|
"address_offset": "0x64",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA4": {"description": "MM2S Start Address Register 4",
|
|||
|
|
"address_offset": "0x68",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA5": {"description": "MM2S Start Address Register 5",
|
|||
|
|
"address_offset": "0x6C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA6": {"description": "MM2S Start Address Register 6",
|
|||
|
|
"address_offset": "0x70",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA7": {"description": "MM2S Start Address Register 7",
|
|||
|
|
"address_offset": "0x74",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA8": {"description": "MM2S Start Address Register 8",
|
|||
|
|
"address_offset": "0x78",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA9": {"description": "MM2S Start Address Register 9",
|
|||
|
|
"address_offset": "0x7C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA10": {"description": "MM2S Start Address Register 10",
|
|||
|
|
"address_offset": "0x80",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA11": {"description": "MM2S Start Address Register 11",
|
|||
|
|
"address_offset": "0x84",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA12": {"description": "MM2S Start Address Register 12",
|
|||
|
|
"address_offset": "0x88",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA13": {"description": "MM2S Start Address Register 13",
|
|||
|
|
"address_offset": "0x8C",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA14": {"description": "MM2S Start Address Register 14",
|
|||
|
|
"address_offset": "0x90",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA15": {"description": "MM2S Start Address Register 15",
|
|||
|
|
"address_offset": "0x94",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"MM2S_SA16": {"description": "MM2S Start Address Register 16",
|
|||
|
|
"address_offset": "0x98",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_VSIZE": {"description": "S2MM Vertical Size",
|
|||
|
|
"address_offset": "0xA0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Vertical_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "13",
|
|||
|
|
"desc": "Indicates the vertical size in lines of the video data to transfer.
|
|||
|
|
Note: Writing a value of zero in this field causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_HSIZE": {"description": "S2MM Horizontal Size",
|
|||
|
|
"address_offset": "0xA4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Horizontal_Size": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the horizontal size in bytes of the video data to transfer.
|
|||
|
|
Note: A value of zero in this field when S2MM_VSIZE is written causes a VDMAIntErr to be flagged in the S2MM_VDMASR register on the next frame boundary.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_FRMDLY_STRIDE": {"description": "S2MM Frame Delay and Stride",
|
|||
|
|
"address_offset": "0xA8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Stride": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "16",
|
|||
|
|
"desc": "Indicates the number of address bytes between the first pixels of each video line.
|
|||
|
|
Note: A stride value less than S2MM_HSIZE causes data to be corrupted.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
"Frame_Delay": {"access": "read-write",
|
|||
|
|
"bit_offset": "24",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "5",
|
|||
|
|
"desc": "Indicates the minimum number of frame buffers the Genlock slave is to be behind the locked master. This field is only used if the channel is enabled for Genlock Slave operations. This field has no meaning in other Genlock modes.
|
|||
|
|
Note: Frame Delay must be less than or equal to Frame Buffers or an undefined results occur.
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA1": {"description": "S2MM Start Address Register 1",
|
|||
|
|
"address_offset": "0xAC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address1": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 1
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA2": {"description": "S2MM Start Address Register 2",
|
|||
|
|
"address_offset": "0xB0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address2": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 2
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA3": {"description": "S2MM Start Address Register 3",
|
|||
|
|
"address_offset": "0xB4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address3": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 3
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA4": {"description": "S2MM Start Address Register 4",
|
|||
|
|
"address_offset": "0xB8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address4": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 4
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA5": {"description": "S2MM Start Address Register 5",
|
|||
|
|
"address_offset": "0xBC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address5": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 5
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA6": {"description": "S2MM Start Address Register 6",
|
|||
|
|
"address_offset": "0xC0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address6": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 6
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA7": {"description": "S2MM Start Address Register 7",
|
|||
|
|
"address_offset": "0xC4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address7": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 7
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA8": {"description": "S2MM Start Address Register 8",
|
|||
|
|
"address_offset": "0xC8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address8": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 8
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA9": {"description": "S2MM Start Address Register 9",
|
|||
|
|
"address_offset": "0xCC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address9": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 9
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA10": {"description": "S2MM Start Address Register 10",
|
|||
|
|
"address_offset": "0xD0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address10": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 10
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA11": {"description": "S2MM Start Address Register 11",
|
|||
|
|
"address_offset": "0xD4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address11": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 11
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA12": {"description": "S2MM Start Address Register 12",
|
|||
|
|
"address_offset": "0xD8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address12": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 12
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA13": {"description": "S2MM Start Address Register 13",
|
|||
|
|
"address_offset": "0xDC",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address13": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 13
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA14": {"description": "S2MM Start Address Register 14",
|
|||
|
|
"address_offset": "0xE0",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address14": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 14
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA15": {"description": "S2MM Start Address Register 15",
|
|||
|
|
"address_offset": "0xE4",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address15": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 15
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"S2MM_SA16": {"description": "S2MM Start Address Register 16",
|
|||
|
|
"address_offset": "0xE8",
|
|||
|
|
"access": "read-write",
|
|||
|
|
"size": "32",
|
|||
|
|
"fields": {"Start_Address16": {"access": "read-write",
|
|||
|
|
"bit_offset": "0",
|
|||
|
|
"bit_range": "",
|
|||
|
|
"bit_width": "32",
|
|||
|
|
"desc": "Indicates the Start Address for video buffer 16
|
|||
|
|
",
|
|||
|
|
"enum_values": "",
|
|||
|
|
"lsb": "",
|
|||
|
|
"mod_write_val": "",
|
|||
|
|
"msb": "",
|
|||
|
|
"read_action": "",
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
},
|
|||
|
|
"ps7_afi_0": {},
|
|||
|
|
"ps7_afi_1": {},
|
|||
|
|
"ps7_afi_2": {},
|
|||
|
|
"ps7_afi_3": {},
|
|||
|
|
"ps7_coresight_comp_0": {},
|
|||
|
|
"ps7_ddr_0": {},
|
|||
|
|
"ps7_ddrc_0": {},
|
|||
|
|
"ps7_dev_cfg_0": {},
|
|||
|
|
"ps7_dma_ns": {},
|
|||
|
|
"ps7_dma_s": {},
|
|||
|
|
"ps7_globaltimer_0": {},
|
|||
|
|
"ps7_gpio_0": {},
|
|||
|
|
"ps7_gpv_0": {},
|
|||
|
|
"ps7_intc_dist_0": {},
|
|||
|
|
"ps7_iop_bus_config_0": {},
|
|||
|
|
"ps7_l2cachec_0": {},
|
|||
|
|
"ps7_ocmc_0": {},
|
|||
|
|
"ps7_pl310_0": {},
|
|||
|
|
"ps7_pmu_0": {},
|
|||
|
|
"ps7_qspi_0": {},
|
|||
|
|
"ps7_qspi_linear_0": {},
|
|||
|
|
"ps7_ram_0": {},
|
|||
|
|
"ps7_ram_1": {},
|
|||
|
|
"ps7_scuc_0": {},
|
|||
|
|
"ps7_scugic_0": {},
|
|||
|
|
"ps7_scutimer_0": {},
|
|||
|
|
"ps7_scuwdt_0": {},
|
|||
|
|
"ps7_sd_0": {},
|
|||
|
|
"ps7_slcr_0": {},
|
|||
|
|
"ps7_uart_1": {},
|
|||
|
|
"ps7_xadc_0": {},
|
|||
|
|
"v_tc_0": {},
|
|||
|
|
}]. Thread: Worker-2
|