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ebaz4205_adc_test/vivado.log

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first init
2023-01-06 07:40:09 +00:00
#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Fri Jan 6 15:38:00 2023
# Process ID: 22772
# Current directory: D:/project/hdl/ebaz4205_adc_test.git
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11156 D:\project\hdl\ebaz4205_adc_test.git\axi_dma.xpr
# Log file: D:/project/hdl/ebaz4205_adc_test.git/vivado.log
# Journal file: D:/project/hdl/ebaz4205_adc_test.git\vivado.jou
# Running On: home-pc, OS: Windows, CPU Frequency: 3593 MHz, CPU Physical cores: 12, Host memory: 17088 MB
#-----------------------------------------------------------
start_gui
open_project D:/project/hdl/ebaz4205_adc_test.git/axi_dma.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:ac701:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/ac701/1.4/board.xml as part xc7a200tfbg676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.2/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.3/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26c/1.4/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.2/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.3/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/k26i/1.4/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kr260_som:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kr260_som/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kr260_som:part0:1.1 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kr260_som/1.1/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.2/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.3/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260_som:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kv260_som/1.4/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:sp701:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/sp701/1.0/board.xml as part xc7s100fgga676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:sp701:part0:1.1 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/sp701/1.1/board.xml as part xc7s100fgga676-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at H:/vitis/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [Project 1-313] Project file moved from 'D:/project/hdl/axi_dma' since last save.
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'D:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1'.
WARNING: [Project 1-312] File not found as 'D:/project/hdl/ebaz4205_adc_test.git/simu_behav.wcfg'; using path 'D:/project/hdl/axi_dma/simu_behav.wcfg' instead.
Scanning sources...
Finished scanning sources
WARNING: [Project 1-509] GeneratedRun file for 'synth_1' not found
WARNING: [Project 1-509] GeneratedRun file for 'design_1_processing_system7_0_0_synth_1' not found
WARNING: [Project 1-509] GeneratedRun file for 'design_1_clk_wiz_0_0_synth_1' not found
WARNING: [Project 1-509] GeneratedRun file for 'design_1_ila_3_0_synth_1' not found
WARNING: [Project 1-509] GeneratedRun file for 'design_1_adc_capture_module_0_0_synth_1' not found
WARNING: [Project 1-509] GeneratedRun file for 'impl_1' not found
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/vitis/Vivado/2022.2/data/ip'.
open_project: Time (s): cpu = 00:01:09 ; elapsed = 00:01:15 . Memory (MB): peak = 1455.031 ; gain = 632.727
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset_n' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXIS'.
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'M_AXIS_ARESETN'.
WARNING: [IP_Flow 19-5661] Bus Interface 'adc_clk' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'.
update_compile_order -fileset sources_1
open_bd_design {D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd}
Reading block design file <D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd>...
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
WARNING: [BD 41-1282] Ignoring parameter HAS_BURST
WARNING: [BD 41-1281] Parameter HAS_BURST is not defined on /axi_dma_0/M_AXIS_MM2S. Setting parameter on /axi_dma_0/M_AXIS_MM2S failed
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_1
INFO: [xilinx.com:ip:ila:6.2-6] /ila_1: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_2
INFO: [xilinx.com:ip:ila:6.2-6] /ila_2: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps7_0_axi_periph
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_1
Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_3
INFO: [xilinx.com:ip:ila:6.2-6] /ila_3: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:module_ref:adc_capture_module:1.0 - adc_capture_module_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset_n' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXIS_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXIS'.
INFO: [IP_Flow 19-4728] Bus Interface 'M_AXIS_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'M_AXIS_ARESETN'.
WARNING: [IP_Flow 19-5661] Bus Interface 'adc_clk' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'.
INFO: [IP_Flow 19-3420] Updated design_1_adc_capture_module_0_0 to use current project options
Successfully read diagram <design_1> from block design file <D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1494.906 ; gain = 30.781
no message
2023-01-06 07:50:06 +00:00
make_wrapper -files [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -top
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter In0_width(4) on '/xlconcat_0' with propagated value(8). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_axi_smc_1: SmartConnect design_1_axi_smc_1 is in High-performance Mode.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
Wrote : <D:\project\hdl\ebaz4205_adc_test.git\axi_dma.srcs\sources_1\bd\design_1\design_1.bd>
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/sim/design_1.v
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:23 . Memory (MB): peak = 1964.883 ; gain = 291.582
update_compile_order -fileset sources_1
generate_target all [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.v
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/sim/design_1.v
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_dma_0 .
Exporting to file d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_axi_smc_1/bd_0/hw_handoff/design_1_axi_smc_1.hwh
Generated Hardware Definition File d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_axi_smc_1/bd_0/synth/design_1_axi_smc_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_1 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_2_0/design_1_ila_2_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_3_0/design_1_ila_3_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block adc_capture_module_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Hardware Definition File d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.hwdef
generate_target: Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 2063.836 ; gain = 64.484
catch { config_ip_cache -export [get_ips -all design_1_rst_ps7_0_100M_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_rst_ps7_0_100M_0
catch { config_ip_cache -export [get_ips -all design_1_axi_dma_0_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_dma_0_0
catch { config_ip_cache -export [get_ips -all design_1_axi_smc_1] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_smc_1
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
catch { config_ip_cache -export [get_ips -all design_1_ila_2_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_2_0
catch { config_ip_cache -export [get_ips -all design_1_ila_3_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_3_0
catch { config_ip_cache -export [get_ips -all design_1_adc_capture_module_0_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_adc_capture_module_0_0
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_auto_pc_0
export_ip_user_files -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
launch_runs design_1_processing_system7_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ila_3_0_synth_1 design_1_adc_capture_module_0_0_synth_1 design_1_rst_ps7_0_100M_0_synth_1 design_1_axi_dma_0_0_synth_1 design_1_axi_smc_1_synth_1 design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_ila_2_0_synth_1 design_1_auto_pc_0_synth_1 -jobs 6
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_3_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_adc_capture_module_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_rst_ps7_0_100M_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_dma_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_smc_1
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_2_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_auto_pc_0
[Fri Jan 6 15:43:54 2023] Launched design_1_processing_system7_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_ila_3_0_synth_1, design_1_adc_capture_module_0_0_synth_1, design_1_rst_ps7_0_100M_0_synth_1, design_1_axi_dma_0_0_synth_1, design_1_axi_smc_1_synth_1, design_1_ila_0_0_synth_1, design_1_ila_1_0_synth_1, design_1_ila_2_0_synth_1, design_1_auto_pc_0_synth_1...
Run output will be captured here:
design_1_processing_system7_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_processing_system7_0_0_synth_1/runme.log
design_1_clk_wiz_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_clk_wiz_0_0_synth_1/runme.log
design_1_ila_3_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_3_0_synth_1/runme.log
design_1_adc_capture_module_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_adc_capture_module_0_0_synth_1/runme.log
design_1_rst_ps7_0_100M_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_rst_ps7_0_100M_0_synth_1/runme.log
design_1_axi_dma_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_axi_dma_0_0_synth_1/runme.log
design_1_axi_smc_1_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_axi_smc_1_synth_1/runme.log
design_1_ila_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_0_0_synth_1/runme.log
design_1_ila_1_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_1_0_synth_1/runme.log
design_1_ila_2_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_2_0_synth_1/runme.log
design_1_auto_pc_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_auto_pc_0_synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 2064.238 ; gain = 0.402
export_simulation -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/sim_scripts -ip_user_files_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files -ipstatic_source_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/modelsim} {questa=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/questa} {riviera=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/riviera} {activehdl=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
exit
INFO: [Common 17-206] Exiting Vivado at Fri Jan 6 15:45:05 2023...