no message
zcy
parent
5dff7668f2
commit
2bbdc1cafc
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@ -0,0 +1,3 @@
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|||
axi_dma.gen/
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||||
axi_dma.runs/
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||||
axi_dma.cache/
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||||
|
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@ -136,7 +136,7 @@
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|||
</spirit:parameter>
|
||||
<spirit:parameter>
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||||
<spirit:name>PHASE</spirit:name>
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||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -145,7 +145,7 @@
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|||
</spirit:parameter>
|
||||
<spirit:parameter>
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||||
<spirit:name>CLK_DOMAIN</spirit:name>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">design_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -283,7 +283,7 @@
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|||
</spirit:parameter>
|
||||
<spirit:parameter>
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||||
<spirit:name>PHASE</spirit:name>
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||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.PHASE">0.0</spirit:value>
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||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -292,7 +292,7 @@
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|||
</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.CLK_DOMAIN"/>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.CLK_DOMAIN">design_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
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||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -337,7 +337,7 @@
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|||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>FREQ_HZ</spirit:name>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.FREQ_HZ">100000000</spirit:value>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.FREQ_HZ">5000000</spirit:value>
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -364,7 +364,7 @@
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</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.CLK_DOMAIN"/>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
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||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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@ -411,6 +411,97 @@
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</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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||||
<spirit:modelName>adc_capture_module</spirit:modelName>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:85514200</spirit:value>
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||||
</spirit:parameter>
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</spirit:parameters>
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||||
</spirit:view>
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||||
<spirit:view>
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<spirit:name>xilinx_synthesisconstraints</spirit:name>
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<spirit:displayName>Synthesis Constraints</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:85514200</spirit:value>
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</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
<spirit:view>
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<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
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<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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||||
<spirit:modelName>design_1_adc_capture_module_0_0</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Fri Jan 06 07:43:45 UTC 2023</spirit:value>
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</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:85514200</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:modelName>adc_capture_module</spirit:modelName>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:627a8bb7</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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||||
<spirit:language>verilog</spirit:language>
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||||
<spirit:modelName>design_1_adc_capture_module_0_0</spirit:modelName>
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<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Fri Jan 06 07:43:45 UTC 2023</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:627a8bb7</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_externalfiles</spirit:name>
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<spirit:displayName>External Files</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:85514200</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>adc_input</spirit:name>
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@ -423,7 +514,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -435,7 +527,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -447,7 +540,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -459,7 +553,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -475,7 +570,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -491,7 +587,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -507,7 +604,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@ -519,7 +617,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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@ -531,7 +630,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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</spirit:wire>
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@ -543,7 +643,8 @@
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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@ -559,7 +660,8 @@
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<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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</spirit:wire>
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@ -575,7 +677,8 @@
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<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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@ -587,7 +690,8 @@
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<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
|
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
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@ -599,7 +703,8 @@
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|||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
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||||
<spirit:driver>
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||||
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@ -683,6 +788,60 @@
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<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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||||
</spirit:choice>
|
||||
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|
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<spirit:fileSets>
|
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<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
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<spirit:name>synth/design_1_adc_capture_module_0_0.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
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</spirit:fileSet>
|
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
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<spirit:file>
|
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<spirit:name>sim/design_1_adc_capture_module_0_0.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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|
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<spirit:fileSet>
|
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<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
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<spirit:file>
|
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<spirit:name>design_1_adc_capture_module_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
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<spirit:file>
|
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<spirit:name>design_1_adc_capture_module_0_0_stub.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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|
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<spirit:file>
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<spirit:name>design_1_adc_capture_module_0_0_stub.vhdl</spirit:name>
|
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<spirit:fileType>vhdlSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
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<spirit:file>
|
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<spirit:name>design_1_adc_capture_module_0_0_sim_netlist.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
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<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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|
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<spirit:file>
|
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<spirit:name>design_1_adc_capture_module_0_0_sim_netlist.vhdl</spirit:name>
|
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<spirit:fileType>vhdlSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
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<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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|
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|
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</spirit:fileSets>
|
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<spirit:description>xilinx.com:module_ref:adc_capture_module:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
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|
@ -760,6 +919,36 @@
|
|||
<xilinx:displayName>adc_capture_module_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.CLK_DOMAIN" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.FREQ_HZ" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ADC_CLK.PHASE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ACLK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESET_N.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_6f02,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_6f02,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=46,numReposBlks=36,numNonXlnxBlks=0,numHierBlks=10,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_axi_smc_1.hwdef" *)
|
||||
(* CORE_GENERATION_INFO = "bd_6f02,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_6f02,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=46,numReposBlks=36,numNonXlnxBlks=0,numHierBlks=10,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1_axi_smc_1.hwdef" *)
|
||||
module bd_6f02
|
||||
(M00_AXI_araddr,
|
||||
M00_AXI_arburst,
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
|
|||
|
|
@ -1,258 +0,0 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Wed Dec 7 19:49:18 2022
|
||||
// Host : home-pc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// d:/project/hdl/axi_dma/axi_dma.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.v
|
||||
// Design : design_1_clk_wiz_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_clk_wiz_0_0
|
||||
(clk_out1,
|
||||
resetn,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input resetn;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire resetn;
|
||||
|
||||
design_1_clk_wiz_0_0_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.resetn(resetn));
|
||||
endmodule
|
||||
|
||||
module design_1_clk_wiz_0_0_clk_wiz
|
||||
(clk_out1,
|
||||
resetn,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input resetn;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_design_1_clk_wiz_0_0;
|
||||
wire clk_out1;
|
||||
wire clk_out1_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_buf_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_design_1_clk_wiz_0_0;
|
||||
wire reset_high;
|
||||
wire resetn;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_design_1_clk_wiz_0_0),
|
||||
.O(clkfbout_buf_design_1_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.CCIO_EN("TRUE"),
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_design_1_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_design_1_clk_wiz_0_0),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(32.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(10.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(128.000000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(5),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.CLKFBOUT(clkfbout_design_1_clk_wiz_0_0),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_design_1_clk_wiz_0_0),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_design_1_clk_wiz_0_0),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset_high));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
mmcm_adv_inst_i_1
|
||||
(.I0(resetn),
|
||||
.O(reset_high));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Wed Dec 7 19:49:18 2022
|
||||
-- Host : home-pc running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- d:/project/hdl/axi_dma/axi_dma.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_clk_wiz_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_clk_wiz_0_0_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
end design_1_clk_wiz_0_0_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of design_1_clk_wiz_0_0_clk_wiz is
|
||||
signal clk_in1_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clk_out1_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_buf_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal reset_high : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_design_1_clk_wiz_0_0,
|
||||
O => clkfbout_buf_design_1_clk_wiz_0_0
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
CCIO_EN => "TRUE",
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_design_1_clk_wiz_0_0
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_design_1_clk_wiz_0_0,
|
||||
O => clk_out1
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 32.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 10.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 128.000000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 1,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 1,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 5,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_0,
|
||||
CLKFBOUT => clkfbout_design_1_clk_wiz_0_0,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_design_1_clk_wiz_0_0,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_design_1_clk_wiz_0_0,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => reset_high
|
||||
);
|
||||
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => resetn,
|
||||
O => reset_high
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_clk_wiz_0_0 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_clk_wiz_0_0 : entity is true;
|
||||
end design_1_clk_wiz_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_clk_wiz_0_0 is
|
||||
begin
|
||||
inst: entity work.design_1_clk_wiz_0_0_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
resetn => resetn
|
||||
);
|
||||
end STRUCTURE;
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,979 +0,0 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun Nov 27 11:14:50 2022
|
||||
// Host : home-pc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top design_1_rst_ps7_0_100M_0 -prefix
|
||||
// design_1_rst_ps7_0_100M_0_ design_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2022.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
design_1_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
module design_1_rst_ps7_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
@ -117,7 +117,7 @@ ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
|
|||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
//Date : Thu Jan 5 17:19:48 2023
|
||||
//Date : Fri Jan 6 15:43:11 2023
|
||||
//Host : home-pc running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1.bd
|
||||
//Design : design_1
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ vlib activehdl/axi_dma_v7_1_28
|
|||
vlib activehdl/xlconstant_v1_1_7
|
||||
vlib activehdl/smartconnect_v1_0
|
||||
vlib activehdl/axi_register_slice_v2_1_27
|
||||
vlib activehdl/xlconcat_v2_1_4
|
||||
vlib activehdl/generic_baseblocks_v2_1_0
|
||||
vlib activehdl/axi_data_fifo_v2_1_26
|
||||
vlib activehdl/axi_protocol_converter_v2_1_27
|
||||
vlib activehdl/xlconcat_v2_1_4
|
||||
|
||||
vmap xilinx_vip activehdl/xilinx_vip
|
||||
vmap xpm activehdl/xpm
|
||||
|
|
@ -42,10 +42,10 @@ vmap axi_dma_v7_1_28 activehdl/axi_dma_v7_1_28
|
|||
vmap xlconstant_v1_1_7 activehdl/xlconstant_v1_1_7
|
||||
vmap smartconnect_v1_0 activehdl/smartconnect_v1_0
|
||||
vmap axi_register_slice_v2_1_27 activehdl/axi_register_slice_v2_1_27
|
||||
vmap xlconcat_v2_1_4 activehdl/xlconcat_v2_1_4
|
||||
vmap generic_baseblocks_v2_1_0 activehdl/generic_baseblocks_v2_1_0
|
||||
vmap axi_data_fifo_v2_1_26 activehdl/axi_data_fifo_v2_1_26
|
||||
vmap axi_protocol_converter_v2_1_27 activehdl/axi_protocol_converter_v2_1_27
|
||||
vmap xlconcat_v2_1_4 activehdl/xlconcat_v2_1_4
|
||||
|
||||
vlog -work xilinx_vip -sv2k12 "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
|
||||
|
|
@ -59,9 +59,9 @@ vlog -work xilinx_vip -sv2k12 "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/i
|
|||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
|
||||
vlog -work xpm -sv2k12 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
|
@ -215,6 +215,16 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/d
|
|||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
|
||||
vlog -work generic_baseblocks_v2_1_0 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
|
||||
|
|
@ -226,16 +236,6 @@ vlog -work axi_protocol_converter_v2_1_27 -v2k5 "+incdir+../../../../axi_dma.ge
|
|||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -93,7 +93,7 @@ map_setup_file()
|
|||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="D:/project/hdl/axi_dma/axi_dma.cache/compile_simlib/activehdl"
|
||||
lib_map_path="D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/activehdl"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
|
|
@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
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|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim +access +r +m+design_1 -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
asim +access +r +m+design_1 -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ vlib modelsim_lib/msim/axi_dma_v7_1_28
|
|||
vlib modelsim_lib/msim/xlconstant_v1_1_7
|
||||
vlib modelsim_lib/msim/smartconnect_v1_0
|
||||
vlib modelsim_lib/msim/axi_register_slice_v2_1_27
|
||||
vlib modelsim_lib/msim/xlconcat_v2_1_4
|
||||
vlib modelsim_lib/msim/generic_baseblocks_v2_1_0
|
||||
vlib modelsim_lib/msim/axi_data_fifo_v2_1_26
|
||||
vlib modelsim_lib/msim/axi_protocol_converter_v2_1_27
|
||||
vlib modelsim_lib/msim/xlconcat_v2_1_4
|
||||
|
||||
vmap xilinx_vip modelsim_lib/msim/xilinx_vip
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
|
@ -42,10 +42,10 @@ vmap axi_dma_v7_1_28 modelsim_lib/msim/axi_dma_v7_1_28
|
|||
vmap xlconstant_v1_1_7 modelsim_lib/msim/xlconstant_v1_1_7
|
||||
vmap smartconnect_v1_0 modelsim_lib/msim/smartconnect_v1_0
|
||||
vmap axi_register_slice_v2_1_27 modelsim_lib/msim/axi_register_slice_v2_1_27
|
||||
vmap xlconcat_v2_1_4 modelsim_lib/msim/xlconcat_v2_1_4
|
||||
vmap generic_baseblocks_v2_1_0 modelsim_lib/msim/generic_baseblocks_v2_1_0
|
||||
vmap axi_data_fifo_v2_1_26 modelsim_lib/msim/axi_data_fifo_v2_1_26
|
||||
vmap axi_protocol_converter_v2_1_27 modelsim_lib/msim/axi_protocol_converter_v2_1_27
|
||||
vmap xlconcat_v2_1_4 modelsim_lib/msim/xlconcat_v2_1_4
|
||||
|
||||
vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
|
||||
|
|
@ -59,9 +59,9 @@ vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0
|
|||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
|
||||
vlog -work xpm -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
|
@ -215,6 +215,16 @@ vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources
|
|||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
|
||||
vlog -work generic_baseblocks_v2_1_0 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
|
||||
|
|
@ -226,16 +236,6 @@ vlog -work axi_protocol_converter_v2_1_27 -incr -mfcu "+incdir+../../../../axi
|
|||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -95,7 +95,7 @@ copy_setup_file()
|
|||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="D:/project/hdl/axi_dma/axi_dma.cache/compile_simlib/modelsim"
|
||||
lib_map_path="D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/modelsim"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
|
|
@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_2_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc " -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
vsim -voptargs="+acc " -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ vlib questa_lib/msim/axi_dma_v7_1_28
|
|||
vlib questa_lib/msim/xlconstant_v1_1_7
|
||||
vlib questa_lib/msim/smartconnect_v1_0
|
||||
vlib questa_lib/msim/axi_register_slice_v2_1_27
|
||||
vlib questa_lib/msim/xlconcat_v2_1_4
|
||||
vlib questa_lib/msim/generic_baseblocks_v2_1_0
|
||||
vlib questa_lib/msim/axi_data_fifo_v2_1_26
|
||||
vlib questa_lib/msim/axi_protocol_converter_v2_1_27
|
||||
vlib questa_lib/msim/xlconcat_v2_1_4
|
||||
|
||||
vmap xilinx_vip questa_lib/msim/xilinx_vip
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
|
@ -42,10 +42,10 @@ vmap axi_dma_v7_1_28 questa_lib/msim/axi_dma_v7_1_28
|
|||
vmap xlconstant_v1_1_7 questa_lib/msim/xlconstant_v1_1_7
|
||||
vmap smartconnect_v1_0 questa_lib/msim/smartconnect_v1_0
|
||||
vmap axi_register_slice_v2_1_27 questa_lib/msim/axi_register_slice_v2_1_27
|
||||
vmap xlconcat_v2_1_4 questa_lib/msim/xlconcat_v2_1_4
|
||||
vmap generic_baseblocks_v2_1_0 questa_lib/msim/generic_baseblocks_v2_1_0
|
||||
vmap axi_data_fifo_v2_1_26 questa_lib/msim/axi_data_fifo_v2_1_26
|
||||
vmap axi_protocol_converter_v2_1_27 questa_lib/msim/axi_protocol_converter_v2_1_27
|
||||
vmap xlconcat_v2_1_4 questa_lib/msim/xlconcat_v2_1_4
|
||||
|
||||
vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
|
||||
|
|
@ -59,9 +59,9 @@ vlog -work xilinx_vip -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0
|
|||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
|
||||
vlog -work xpm -incr -mfcu -sv -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_15 -L xilinx_vip "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
|
@ -215,6 +215,16 @@ vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources
|
|||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
|
||||
vlog -work generic_baseblocks_v2_1_0 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
|
||||
|
|
@ -226,16 +236,6 @@ vlog -work axi_protocol_converter_v2_1_27 -incr -mfcu "+incdir+../../../../axi
|
|||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -incr -mfcu "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -102,7 +102,7 @@ copy_setup_file()
|
|||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="D:/project/hdl/axi_dma/axi_dma.cache/compile_simlib/questa"
|
||||
lib_map_path="D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/questa"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
vopt +acc=npr -l elaborate.log -L xil_defaultlib -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_opt
|
||||
vopt +acc=npr -l elaborate.log -L xil_defaultlib -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_opt
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
|
|
@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_2_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ vlib riviera/axi_dma_v7_1_28
|
|||
vlib riviera/xlconstant_v1_1_7
|
||||
vlib riviera/smartconnect_v1_0
|
||||
vlib riviera/axi_register_slice_v2_1_27
|
||||
vlib riviera/xlconcat_v2_1_4
|
||||
vlib riviera/generic_baseblocks_v2_1_0
|
||||
vlib riviera/axi_data_fifo_v2_1_26
|
||||
vlib riviera/axi_protocol_converter_v2_1_27
|
||||
vlib riviera/xlconcat_v2_1_4
|
||||
|
||||
vmap xilinx_vip riviera/xilinx_vip
|
||||
vmap xpm riviera/xpm
|
||||
|
|
@ -42,10 +42,10 @@ vmap axi_dma_v7_1_28 riviera/axi_dma_v7_1_28
|
|||
vmap xlconstant_v1_1_7 riviera/xlconstant_v1_1_7
|
||||
vmap smartconnect_v1_0 riviera/smartconnect_v1_0
|
||||
vmap axi_register_slice_v2_1_27 riviera/axi_register_slice_v2_1_27
|
||||
vmap xlconcat_v2_1_4 riviera/xlconcat_v2_1_4
|
||||
vmap generic_baseblocks_v2_1_0 riviera/generic_baseblocks_v2_1_0
|
||||
vmap axi_data_fifo_v2_1_26 riviera/axi_data_fifo_v2_1_26
|
||||
vmap axi_protocol_converter_v2_1_27 riviera/axi_protocol_converter_v2_1_27
|
||||
vmap xlconcat_v2_1_4 riviera/xlconcat_v2_1_4
|
||||
|
||||
vlog -work xilinx_vip -sv2k12 "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
|
||||
|
|
@ -59,9 +59,9 @@ vlog -work xilinx_vip -sv2k12 "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/i
|
|||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
|
||||
vlog -work xpm -sv2k12 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
|
@ -215,6 +215,16 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/d
|
|||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
|
||||
vlog -work generic_baseblocks_v2_1_0 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
|
||||
|
|
@ -226,16 +236,6 @@ vlog -work axi_protocol_converter_v2_1_27 -v2k5 "+incdir+../../../../axi_dma.ge
|
|||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
|
||||
vlog -work xlconcat_v2_1_4 -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" "+incdir+../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" "+incdir+H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -93,7 +93,7 @@ map_setup_file()
|
|||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="D:/project/hdl/axi_dma/axi_dma.cache/compile_simlib/riviera"
|
||||
lib_map_path="D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/riviera"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
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||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
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||||
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||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
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||||
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||||
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@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
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|||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim +access +r +m+design_1 -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
asim +access +r +m+design_1 -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl
|
||||
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -54,7 +54,7 @@ vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log "
|
|||
vcs_sim_opts="-ucli -licqueue -l simulate.log "
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_13 processing_system7_vip_v1_0_15 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lib_pkg_v1_0_2 fifo_generator_v13_2_7 lib_fifo_v1_0_16 lib_srl_fifo_v1_0_2 axi_datamover_v5_1_29 axi_sg_v4_1_15 axi_dma_v7_1_28 xlconstant_v1_1_7 smartconnect_v1_0 axi_register_slice_v2_1_27 generic_baseblocks_v2_1_0 axi_data_fifo_v2_1_26 axi_protocol_converter_v2_1_27 xlconcat_v2_1_4)
|
||||
design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_13 processing_system7_vip_v1_0_15 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lib_pkg_v1_0_2 fifo_generator_v13_2_7 lib_fifo_v1_0_16 lib_srl_fifo_v1_0_2 axi_datamover_v5_1_29 axi_sg_v4_1_15 axi_dma_v7_1_28 xlconstant_v1_1_7 smartconnect_v1_0 axi_register_slice_v2_1_27 xlconcat_v2_1_4 generic_baseblocks_v2_1_0 axi_data_fifo_v2_1_26 axi_protocol_converter_v2_1_27)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
|
|
@ -88,9 +88,9 @@ compile()
|
|||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
|
|
@ -285,6 +285,18 @@ compile()
|
|||
"$ref_dir/../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xlconcat_v2_1_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work generic_baseblocks_v2_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
|
@ -299,18 +311,6 @@ compile()
|
|||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xlconcat_v2_1_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"H:/vitis/Vivado/2022.2/data/xilinx_vip/include" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"$ref_dir/../../../bd/design_1/sim/design_1.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
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|
@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_2_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -48,7 +48,7 @@ ref_lib_dir="."
|
|||
xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen "
|
||||
|
||||
# Design libraries
|
||||
design_libs=(simprims_ver xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_13 processing_system7_vip_v1_0_15 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lib_pkg_v1_0_2 fifo_generator_v13_2_7 lib_fifo_v1_0_16 lib_srl_fifo_v1_0_2 axi_datamover_v5_1_29 axi_sg_v4_1_15 axi_dma_v7_1_28 xlconstant_v1_1_7 smartconnect_v1_0 axi_register_slice_v2_1_27 generic_baseblocks_v2_1_0 axi_data_fifo_v2_1_26 axi_protocol_converter_v2_1_27 xlconcat_v2_1_4)
|
||||
design_libs=(simprims_ver xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_13 processing_system7_vip_v1_0_15 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 lib_pkg_v1_0_2 fifo_generator_v13_2_7 lib_fifo_v1_0_16 lib_srl_fifo_v1_0_2 axi_datamover_v5_1_29 axi_sg_v4_1_15 axi_dma_v7_1_28 xlconstant_v1_1_7 smartconnect_v1_0 axi_register_slice_v2_1_27 xlconcat_v2_1_4 generic_baseblocks_v2_1_0 axi_data_fifo_v2_1_26 axi_protocol_converter_v2_1_27)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="xcelium_lib"
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ axi4stream_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx
|
|||
axi_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_fifo.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_cdc.sv,systemverilog,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_13,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
|
|
@ -82,15 +82,15 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_2_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
xlconcat_v2_1_vl_rfs.v,verilog,xlconcat_v2_1_4,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_0,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_26,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_27,../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@
|
|||
"H:/vitis/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm -sv \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"H:/vitis/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
|
@ -166,6 +166,16 @@
|
|||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xlconcat_v2_1_4 \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/generic_baseblocks_v2_1_0 \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
|
||||
-endlib
|
||||
|
|
@ -177,16 +187,6 @@
|
|||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xlconcat_v2_1_4 \
|
||||
"../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by export_simulation on Fri Jan 06 15:43:55 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
|
|
|||
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri Jan 06 15:23:05 +0800 2023
|
||||
# Generated by Vivado on Fri Jan 06 15:43:55 +0800 2023
|
||||
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.10
|
||||
|
|
@ -50,7 +50,7 @@ compile()
|
|||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
xelab --incr --debug typical --relax --mt auto -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log
|
||||
xelab --incr --debug typical --relax --mt auto -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
--incr --debug typical --relax --mt auto -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log
|
||||
--incr --debug typical --relax --mt auto -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_7 -L lib_fifo_v1_0_16 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_29 -L axi_sg_v4_1_15 -L axi_dma_v7_1_28 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L xlconcat_v2_1_4 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_26 -L axi_protocol_converter_v2_1_27 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log
|
||||
|
|
|
|||
|
|
@ -44,11 +44,11 @@ design_1_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_c
|
|||
design_1_ila_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_2_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconcat_1_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_xlconstant_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_ila_3_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_adc_capture_module_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v,incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="$ref_dir/../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/ee60/hdl"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/66be/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/7698"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog"incdir="../../../../axi_dma.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
|
|
|||
|
|
@ -46,12 +46,12 @@ verilog xil_defaultlib --include "H:/vitis/Vivado/2022.2/data/xilinx_vip/include
|
|||
"../../../bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_2_0/sim/design_1_ila_2_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_0_0/sim/design_1_xlconcat_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconcat_1_0/sim/design_1_xlconcat_1_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_adc_capture_module_0_0/sim/design_1_adc_capture_module_0_0.v" \
|
||||
"../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
|
||||
"../../../bd/design_1/sim/design_1.v" \
|
||||
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -23,22 +23,13 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -49,6 +40,16 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
|
|
@ -68,6 +69,10 @@
|
|||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="BA">0x40400000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4040FFFF</data>
|
||||
|
|
@ -85,19 +90,14 @@
|
|||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n5">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">design_1</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n6">
|
||||
<data key="BA">0x00000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x1FFFFFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">Data_MM2S</data>
|
||||
<data key="MA">Data_S2MM</data>
|
||||
<data key="MX">/axi_dma_0</data>
|
||||
<data key="MI">M_AXI_MM2S</data>
|
||||
<data key="MI">M_AXI_S2MM</data>
|
||||
<data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data>
|
||||
<data key="MV">xilinx.com:ip:axi_dma:7.1</data>
|
||||
<data key="TM">both</data>
|
||||
|
|
@ -108,18 +108,18 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n5"/>
|
||||
<edge id="e1" source="n5" target="n0"/>
|
||||
<edge id="e2" source="n4" target="n0">
|
||||
<edge id="e0" source="n4" target="n1"/>
|
||||
<edge id="e1" source="n1" target="n2"/>
|
||||
<edge id="e2" source="n5" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n3" target="n0">
|
||||
<edge id="e3" source="n3" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n6" target="n0">
|
||||
<edge id="e4" source="n0" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e5" source="n2" target="n0">
|
||||
<edge id="e5" source="n6" target="n2">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_adc_capture_module_0_0",
|
||||
"cell_name": "adc_capture_module_0",
|
||||
"component_reference": "xilinx.com:module_ref:adc_capture_module:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../axi_dma.gen/sources_1/bd/design_1/ip/design_1_adc_capture_module_0_0",
|
||||
|
|
@ -86,18 +87,18 @@
|
|||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
@ -113,7 +114,7 @@
|
|||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
@ -125,7 +126,7 @@
|
|||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
@ -137,13 +138,13 @@
|
|||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIS_ARESETN", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
@ -155,13 +156,13 @@
|
|||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "5000000", "value_src": "ip_propagated", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_src": "ip_propagated", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
|
|||
|
|
@ -636,8 +636,8 @@
|
|||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
|
|
|||
|
|
@ -2062,8 +2062,8 @@
|
|||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRIGOUT_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
|
|
@ -6240,7 +6240,7 @@
|
|||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT0_DIVIDE_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
|
|
|
|||
|
|
@ -2062,8 +2062,8 @@
|
|||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRIGOUT_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
|
|
@ -3102,7 +3102,7 @@
|
|||
"EN_BRAM_DRC": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ALL_PROBE_SAME_MU": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ALL_PROBE_SAME_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
|
|
@ -6240,7 +6240,7 @@
|
|||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT0_DIVIDE_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
|
|
|
|||
|
|
@ -2062,8 +2062,8 @@
|
|||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRIGOUT_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
|
|
@ -3102,7 +3102,7 @@
|
|||
"EN_BRAM_DRC": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ALL_PROBE_SAME_MU": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ALL_PROBE_SAME_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_SLOT_0_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
|
|
@ -6240,7 +6240,7 @@
|
|||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT0_DIVIDE_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
|
|
|
|||
|
|
@ -2062,8 +2062,8 @@
|
|||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TRIGOUT_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
|
|
@ -6240,7 +6240,7 @@
|
|||
"C_INPUT_PIPE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_STRG_QUAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_TIME_TAG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TIME_TAG_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT0_DIVIDE_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -78,9 +78,11 @@
|
|||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
|
|
|
|||
354
axi_dma.xpr
354
axi_dma.xpr
|
|
@ -65,13 +65,13 @@
|
|||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="97"/>
|
||||
<Option Name="WTModelSimExportSim" Val="97"/>
|
||||
<Option Name="WTQuestaExportSim" Val="97"/>
|
||||
<Option Name="WTXSimExportSim" Val="98"/>
|
||||
<Option Name="WTModelSimExportSim" Val="98"/>
|
||||
<Option Name="WTQuestaExportSim" Val="98"/>
|
||||
<Option Name="WTIesExportSim" Val="85"/>
|
||||
<Option Name="WTVcsExportSim" Val="97"/>
|
||||
<Option Name="WTRivieraExportSim" Val="97"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="97"/>
|
||||
<Option Name="WTVcsExportSim" Val="98"/>
|
||||
<Option Name="WTRivieraExportSim" Val="98"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="98"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
|
|
@ -89,32 +89,13 @@
|
|||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/adc_capture_module.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/test_axis.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_adc_capture_module_0_0/design_1_adc_capture_module_0_0.xci">
|
||||
<Proxy FileSetName="design_1_adc_capture_module_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ila_3_0/design_1_ila_3_0.xci">
|
||||
<Proxy FileSetName="design_1_ila_3_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/simu.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
|
|
@ -122,13 +103,55 @@
|
|||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/test_axis.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/adc_capture_module.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ila_0_0/design_1_ila_0_0.xci">
|
||||
<Proxy FileSetName="design_1_ila_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ila_1_0/design_1_ila_1_0.xci">
|
||||
<Proxy FileSetName="design_1_ila_1_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ila_2_0/design_1_ila_2_0.xci">
|
||||
<Proxy FileSetName="design_1_ila_2_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0.xci">
|
||||
<Proxy FileSetName="design_1_rst_ps7_0_100M_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axi_dma_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_smc_1/design_1_axi_smc_1.xci">
|
||||
<Proxy FileSetName="design_1_axi_smc_1"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_adc_capture_module_0_0/design_1_adc_capture_module_0_0.xci">
|
||||
<Proxy FileSetName="design_1_adc_capture_module_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ila_3_0/design_1_ila_3_0.xci">
|
||||
<Proxy FileSetName="design_1_ila_3_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_auto_pc_0/design_1_auto_pc_0.xci">
|
||||
<Proxy FileSetName="design_1_auto_pc_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
|
|
@ -139,7 +162,8 @@
|
|||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopModule" Val="simu"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
|
|
@ -163,8 +187,9 @@
|
|||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopModule" Val="simu"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
|
|
@ -209,6 +234,48 @@
|
|||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rst_ps7_0_100M_0" RelGenDir="$PGENDIR/design_1_rst_ps7_0_100M_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_rst_ps7_0_100M_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axi_dma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_dma_0_0" RelGenDir="$PGENDIR/design_1_axi_dma_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axi_dma_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axi_smc_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_smc_1" RelGenDir="$PGENDIR/design_1_axi_smc_1">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axi_smc_1"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_ila_0_0" RelGenDir="$PGENDIR/design_1_ila_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_ila_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_ila_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_ila_1_0" RelGenDir="$PGENDIR/design_1_ila_1_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_ila_1_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_ila_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_ila_2_0" RelGenDir="$PGENDIR/design_1_ila_2_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_ila_2_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_auto_pc_0" RelGenDir="$PGENDIR/design_1_auto_pc_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_auto_pc_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
|
|
@ -238,38 +305,126 @@
|
|||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1">
|
||||
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1">
|
||||
<Run Id="design_1_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_3_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_ila_3_0" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_3_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_3_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_3_0_synth_1">
|
||||
<Run Id="design_1_ila_3_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_ila_3_0" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_3_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_ila_3_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_3_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_3_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_adc_capture_module_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_adc_capture_module_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_adc_capture_module_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_adc_capture_module_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_adc_capture_module_0_0_synth_1">
|
||||
<Run Id="design_1_adc_capture_module_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_adc_capture_module_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_adc_capture_module_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_adc_capture_module_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_adc_capture_module_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_adc_capture_module_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_rst_ps7_0_100M_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_rst_ps7_0_100M_0" Part="xc7z010clg400-1" ConstrsSet="design_1_rst_ps7_0_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rst_ps7_0_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axi_dma_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_dma_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_axi_dma_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_dma_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_dma_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_dma_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axi_smc_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_smc_1" Part="xc7z010clg400-1" ConstrsSet="design_1_axi_smc_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_smc_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_smc_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_smc_1_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_ila_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_1_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_ila_1_0" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_ila_1_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_1_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_1_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_2_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_ila_2_0" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_2_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_ila_2_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_2_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_2_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_auto_pc_0" Part="xc7z010clg400-1" ConstrsSet="design_1_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
|
|
@ -359,6 +514,139 @@
|
|||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_rst_ps7_0_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_rst_ps7_0_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rst_ps7_0_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_100M_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axi_dma_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_axi_dma_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_dma_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_dma_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_dma_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axi_smc_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_axi_smc_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_smc_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_smc_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_smc_1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_ila_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_1_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_ila_2_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_ila_2_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_ila_2_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_ila_2_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_ila_2_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_auto_pc_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
|
|
|
|||
28
vivado.jou
28
vivado.jou
|
|
@ -14,3 +14,31 @@ start_gui
|
|||
open_project D:/project/hdl/ebaz4205_adc_test.git/axi_dma.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
open_bd_design {D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd}
|
||||
make_wrapper -files [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -top
|
||||
update_compile_order -fileset sources_1
|
||||
generate_target all [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
|
||||
catch { config_ip_cache -export [get_ips -all design_1_rst_ps7_0_100M_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_axi_dma_0_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_axi_smc_1] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_2_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_3_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_adc_capture_module_0_0] }
|
||||
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
|
||||
export_ip_user_files -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
|
||||
launch_runs design_1_processing_system7_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ila_3_0_synth_1 design_1_adc_capture_module_0_0_synth_1 design_1_rst_ps7_0_100M_0_synth_1 design_1_axi_dma_0_0_synth_1 design_1_axi_smc_1_synth_1 design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_ila_2_0_synth_1 design_1_auto_pc_0_synth_1 -jobs 6
|
||||
wait_on_run design_1_processing_system7_0_0_synth_1
|
||||
wait_on_run design_1_clk_wiz_0_0_synth_1
|
||||
wait_on_run design_1_ila_3_0_synth_1
|
||||
wait_on_run design_1_adc_capture_module_0_0_synth_1
|
||||
wait_on_run design_1_rst_ps7_0_100M_0_synth_1
|
||||
wait_on_run design_1_axi_dma_0_0_synth_1
|
||||
wait_on_run design_1_axi_smc_1_synth_1
|
||||
wait_on_run design_1_ila_0_0_synth_1
|
||||
wait_on_run design_1_ila_1_0_synth_1
|
||||
wait_on_run design_1_ila_2_0_synth_1
|
||||
wait_on_run design_1_auto_pc_0_synth_1
|
||||
export_simulation -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/sim_scripts -ip_user_files_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files -ipstatic_source_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/modelsim} {questa=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/questa} {riviera=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/riviera} {activehdl=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||||
|
|
|
|||
99
vivado.log
99
vivado.log
|
|
@ -140,3 +140,102 @@ INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'.
|
|||
INFO: [IP_Flow 19-3420] Updated design_1_adc_capture_module_0_0 to use current project options
|
||||
Successfully read diagram <design_1> from block design file <D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd>
|
||||
open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1494.906 ; gain = 30.781
|
||||
make_wrapper -files [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -top
|
||||
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
|
||||
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter In0_width(4) on '/xlconcat_0' with propagated value(8). Command ignored
|
||||
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
|
||||
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_PROBE0_WIDTH(2) on '/ila_2' with propagated value(1). Command ignored
|
||||
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_axi_smc_1: SmartConnect design_1_axi_smc_1 is in High-performance Mode.
|
||||
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
||||
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
||||
Wrote : <D:\project\hdl\ebaz4205_adc_test.git\axi_dma.srcs\sources_1\bd\design_1\design_1.bd>
|
||||
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.v
|
||||
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/sim/design_1.v
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||||
make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:23 . Memory (MB): peak = 1964.883 ; gain = 291.582
|
||||
update_compile_order -fileset sources_1
|
||||
generate_target all [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
|
||||
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||||
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.v
|
||||
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/xlconcat_0/In0'(4) to pin '/processing_system7_0/ENET0_GMII_TXD'(8) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/sim/design_1.v
|
||||
Verilog Output written to : d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||||
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
|
||||
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0'. A default connection has been created.
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_100M .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_dma_0 .
|
||||
Exporting to file d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_axi_smc_1/bd_0/hw_handoff/design_1_axi_smc_1.hwh
|
||||
Generated Hardware Definition File d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_axi_smc_1/bd_0/synth/design_1_axi_smc_1.hwdef
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
|
||||
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc'
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_0 .
|
||||
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0_ooc.xdc'
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_1 .
|
||||
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_2_0/design_1_ila_2_0_ooc.xdc'
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_2 .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_1 .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_0 .
|
||||
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_ila_3_0/design_1_ila_3_0_ooc.xdc'
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_3 .
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block adc_capture_module_0 .
|
||||
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'd:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
|
||||
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
|
||||
Exporting to file d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||||
Generated Hardware Definition File d:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||||
generate_target: Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 2063.836 ; gain = 64.484
|
||||
catch { config_ip_cache -export [get_ips -all design_1_rst_ps7_0_100M_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_rst_ps7_0_100M_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_axi_dma_0_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_dma_0_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_axi_smc_1] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_smc_1
|
||||
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_2_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_2_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_ila_3_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_3_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_adc_capture_module_0_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_adc_capture_module_0_0
|
||||
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_auto_pc_0
|
||||
export_ip_user_files -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd]
|
||||
launch_runs design_1_processing_system7_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ila_3_0_synth_1 design_1_adc_capture_module_0_0_synth_1 design_1_rst_ps7_0_100M_0_synth_1 design_1_axi_dma_0_0_synth_1 design_1_axi_smc_1_synth_1 design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_ila_2_0_synth_1 design_1_auto_pc_0_synth_1 -jobs 6
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_3_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_adc_capture_module_0_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_rst_ps7_0_100M_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_dma_0_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_smc_1
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_2_0
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_auto_pc_0
|
||||
[Fri Jan 6 15:43:54 2023] Launched design_1_processing_system7_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_ila_3_0_synth_1, design_1_adc_capture_module_0_0_synth_1, design_1_rst_ps7_0_100M_0_synth_1, design_1_axi_dma_0_0_synth_1, design_1_axi_smc_1_synth_1, design_1_ila_0_0_synth_1, design_1_ila_1_0_synth_1, design_1_ila_2_0_synth_1, design_1_auto_pc_0_synth_1...
|
||||
Run output will be captured here:
|
||||
design_1_processing_system7_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_processing_system7_0_0_synth_1/runme.log
|
||||
design_1_clk_wiz_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_clk_wiz_0_0_synth_1/runme.log
|
||||
design_1_ila_3_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_3_0_synth_1/runme.log
|
||||
design_1_adc_capture_module_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_adc_capture_module_0_0_synth_1/runme.log
|
||||
design_1_rst_ps7_0_100M_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_rst_ps7_0_100M_0_synth_1/runme.log
|
||||
design_1_axi_dma_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_axi_dma_0_0_synth_1/runme.log
|
||||
design_1_axi_smc_1_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_axi_smc_1_synth_1/runme.log
|
||||
design_1_ila_0_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_0_0_synth_1/runme.log
|
||||
design_1_ila_1_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_1_0_synth_1/runme.log
|
||||
design_1_ila_2_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_ila_2_0_synth_1/runme.log
|
||||
design_1_auto_pc_0_synth_1: D:/project/hdl/ebaz4205_adc_test.git/axi_dma.runs/design_1_auto_pc_0_synth_1/runme.log
|
||||
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 2064.238 ; gain = 0.402
|
||||
export_simulation -of_objects [get_files D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/sim_scripts -ip_user_files_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files -ipstatic_source_dir D:/project/hdl/ebaz4205_adc_test.git/axi_dma.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/modelsim} {questa=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/questa} {riviera=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/riviera} {activehdl=D:/project/hdl/ebaz4205_adc_test.git/axi_dma.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Jan 6 15:45:05 2023...
|
||||
|
|
|
|||
|
|
@ -1,265 +0,0 @@
|
|||
/*
|
||||
|
||||
Xilinx Vivado v2022.2 (64-bit) [Major: 2022, Minor: 2]
|
||||
SW Build: 3671981 on Fri Oct 14 05:00:03 MDT 2022
|
||||
IP Build: 3669848 on Fri Oct 14 08:30:02 MDT 2022
|
||||
|
||||
Process ID (PID): 22772
|
||||
License: Customer
|
||||
Mode: GUI Mode
|
||||
|
||||
Current time: Fri Jan 06 15:38:13 CST 2023
|
||||
Time zone: China Standard Time (Asia/Shanghai)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 2560x1440
|
||||
Screen resolution (DPI): 125
|
||||
Available screens: 1
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=15
|
||||
Scale size: 19
|
||||
|
||||
Java version: 11.0.11 64-bit
|
||||
Java home: H:/vitis/Vivado/2022.2/tps/win64/jre11.0.11_9
|
||||
Java executable: H:/vitis/Vivado/2022.2/tps/win64/jre11.0.11_9/bin/java.exe
|
||||
Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]
|
||||
Java initial memory (-Xms): 256 MB
|
||||
Java maximum memory (-Xmx): 3 GB
|
||||
|
||||
|
||||
User name: 29019
|
||||
User home directory: C:/Users/29019
|
||||
User working directory: D:/project/hdl/ebaz4205_adc_test.git
|
||||
User country: CN
|
||||
User language: zh
|
||||
User locale: zh_CN
|
||||
|
||||
RDI_BASEROOT: H:/vitis/Vivado
|
||||
HDI_APPROOT: H:/vitis/Vivado/2022.2
|
||||
RDI_DATADIR: H:/vitis/Vivado/2022.2/data
|
||||
RDI_BINDIR: H:/vitis/Vivado/2022.2/bin
|
||||
|
||||
Vivado preferences file: C:/Users/29019/AppData/Roaming/Xilinx/Vivado/2022.2/vivado.xml
|
||||
Vivado preferences directory: C:/Users/29019/AppData/Roaming/Xilinx/Vivado/2022.2/
|
||||
Vivado layouts directory: C:/Users/29019/AppData/Roaming/Xilinx/Vivado/2022.2/data/layouts
|
||||
PlanAhead jar file: H:/vitis/Vivado/2022.2/lib/classes/planAhead.jar
|
||||
Vivado log file: D:/project/hdl/ebaz4205_adc_test.git/vivado.log
|
||||
Vivado journal file: D:/project/hdl/ebaz4205_adc_test.git/vivado.jou
|
||||
Engine tmp dir: D:/project/hdl/ebaz4205_adc_test.git/.Xil/Vivado-22772-home-pc
|
||||
|
||||
Xilinx Environment Variables
|
||||
----------------------------
|
||||
ANDROID_SDK_HOME: C:\Users\29019\AppData\Local\Android\Sdk
|
||||
RDI_APPROOT: H:/vitis/Vivado/2022.2
|
||||
RDI_ARGS: -gui_launcher_event rodinguilauncherevent11156 "D:\project\hdl\ebaz4205_adc_test.git\axi_dma.xpr"
|
||||
RDI_ARGS_FUNCTION: RDI_EXEC_DEFAULT
|
||||
RDI_BASEROOT: H:/vitis/Vivado
|
||||
RDI_BINDIR: H:/vitis/Vivado/2022.2/bin
|
||||
RDI_BINROOT: H:/vitis/Vivado/2022.2/bin
|
||||
RDI_BUILD: yes
|
||||
RDI_CHECK_PROG: True
|
||||
RDI_DATADIR: H:/vitis/Vivado/2022.2/data
|
||||
RDI_INSTALLROOT: H:/vitis
|
||||
RDI_INSTALLVER: 2022.2
|
||||
RDI_INSTALLVERSION: 2022.2
|
||||
RDI_ISE_PLATFORM: nt64
|
||||
RDI_JAVACEFROOT: H:/vitis/Vivado/2022.2/tps/win64/java-cef-95.0.4638.69
|
||||
RDI_JAVAFXROOT: H:/vitis/Vivado/2022.2/tps/win64/javafx-sdk-11.0.2
|
||||
RDI_JAVAROOT: H:/vitis/Vivado/2022.2/tps/win64/jre11.0.11_9
|
||||
RDI_JAVA_VERSION: 11.0.11_9
|
||||
RDI_LIBDIR: H:/vitis/Vivado/2022.2/lib/win64.o
|
||||
RDI_MINGW_LIB: H:/vitis/Vivado/2022.2\tps\mingw\6.2.0\win64.o\nt\bin;H:/vitis/Vivado/2022.2\tps\mingw\6.2.0\win64.o\nt\libexec\gcc\x86_64-w64-mingw32\6.2.0
|
||||
RDI_OPT_EXT: .o
|
||||
RDI_PLATFORM: win64
|
||||
RDI_PREPEND_PATH: H:/vitis/Vitis/2022.2/bin;H:/vitis/Vivado/2022.2/ids_lite/ISE/bin/nt64;H:/vitis/Vivado/2022.2/ids_lite/ISE/lib/nt64
|
||||
RDI_PROG: H:/vitis/Vivado/2022.2/bin/unwrapped/win64.o/vivado.exe
|
||||
RDI_PROGNAME: vivado.exe
|
||||
RDI_PYTHON3: H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3
|
||||
RDI_PYTHON3_VERSION: 3.8.3
|
||||
RDI_PYTHONHOME: H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3
|
||||
RDI_PYTHONPATH: H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3;H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3\bin;H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3\lib;H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3\lib\site-packages
|
||||
RDI_PYTHON_LD_LIBPATH: H:/vitis/Vivado/2022.2\tps\win64\python-3.8.3\lib
|
||||
RDI_TPS_ROOT: H:/vitis/Vivado/2022.2/tps/win64
|
||||
RDI_USE_JDK11: True
|
||||
RDI_VERBOSE: False
|
||||
XILINX: H:/vitis/Vivado/2022.2/ids_lite/ISE
|
||||
XILINX_DSP: H:/vitis/Vivado/2022.2/ids_lite/ISE
|
||||
XILINX_HLS: H:/vitis/Vitis_HLS/2022.2
|
||||
XILINX_PLANAHEAD: H:/vitis/Vivado/2022.2
|
||||
XILINX_SDK: H:/vitis/Vitis/2022.2
|
||||
XILINX_VITIS: H:/vitis/Vitis/2022.2
|
||||
XILINX_VIVADO: H:/vitis/Vivado/2022.2
|
||||
XILINX_VIVADO_HLS: H:/vitis/Vivado/2022.2
|
||||
_RDI_BINROOT: H:\vitis\Vivado\2022.2\bin
|
||||
_RDI_CWD: D:\project\hdl\ebaz4205_adc_test.git
|
||||
|
||||
|
||||
GUI allocated memory: 256 MB
|
||||
GUI max memory: 3,072 MB
|
||||
Engine allocated memory: 830 MB
|
||||
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Opening Vivado Project: D:\project\hdl\ebaz4205_adc_test.git\axi_dma.xpr. Version: Vivado v2022.2
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// TclEventType: FLOW_ADDED
|
||||
// Tcl Message: open_project D:/project/hdl/ebaz4205_adc_test.git/axi_dma.xpr
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 865 MB. GUI used memory: 67 MB. Current time: 1/6/23, 3:38:15 PM CST
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_DASHBOARD_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
|
||||
// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: IP_LOCK_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: LOAD_FEATURE
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,060 MB. GUI used memory: 64 MB. Current time: 1/6/23, 3:38:40 PM CST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,088 MB. GUI used memory: 64 MB. Current time: 1/6/23, 3:39:10 PM CST
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 83 MB (+84852kb) [00:01:19]
|
||||
// [Engine Memory]: 1,270 MB (+1179867kb) [00:01:19]
|
||||
// [GUI Memory]: 112 MB (+25489kb) [00:01:20]
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 2128 ms.
|
||||
// Tcl Message: open_project D:/project/hdl/ebaz4205_adc_test.git/axi_dma.xpr
|
||||
// Tcl Message: INFO: [Project 1-313] Project file moved from 'D:/project/hdl/axi_dma' since last save. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'D:/project/hdl/ebaz4205_adc_test.git/axi_dma.gen/sources_1'.
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/vitis/Vivado/2022.2/data/ip'.
|
||||
// Project name: axi_dma; location: D:/project/hdl/ebaz4205_adc_test.git; part: xc7z010clg400-1
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:01:09 ; elapsed = 00:01:15 . Memory (MB): peak = 1455.031 ; gain = 632.727
|
||||
dismissDialog("Open Project"); // bq
|
||||
// [Engine Memory]: 1,335 MB (+1850kb) [00:01:23]
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: PACKAGER_OBJECT_ADD
|
||||
// TclEventType: PACKAGER_MESSAGE_RESET
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: PACKAGER_MESSAGE_RESET
|
||||
// TclEventType: PACKAGER_MESSAGE_UPDATE
|
||||
// TclEventType: IP_LOCK_CHANGE
|
||||
// TclEventType: BDCELL_LOCK_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// [GUI Memory]: 130 MB (+13531kb) [00:01:28]
|
||||
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, IP Integrator, Open Block Design]", 7, false); // f
|
||||
// Run Command: PAResourceCommand.PACommandNames_OPEN_BLOCK_DESIGN
|
||||
// TclEventType: RSB_SCRIPT_TASK
|
||||
// Tcl Message: open_bd_design {D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd}
|
||||
// Tcl Message: Reading block design file <D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd>...
|
||||
// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
|
||||
selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
|
||||
// TclEventType: RSB_LOCK_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_100M Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,355 MB. GUI used memory: 71 MB. Current time: 1/6/23, 3:39:40 PM CST
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: PACKAGER_OBJECT_ADD
|
||||
// TclEventType: PACKAGER_OBJECT_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_PROPERTY_CHANGE
|
||||
// TclEventType: PACKAGER_OBJECT_ADD
|
||||
// TclEventType: PACKAGER_MESSAGE_RESET
|
||||
// TclEventType: PACKAGER_MESSAGE_UPDATE
|
||||
// TclEventType: BDCELL_LOCK_CHANGE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: RSB_LOCK_CHANGE
|
||||
// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
|
||||
// TclEventType: RSB_SCRIPT_TASK
|
||||
// TclEventType: RSB_OPEN_DIAGRAM
|
||||
// WARNING: HEventQueue.dispatchEvent() is taking 1148 ms.
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0 Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
|
||||
// Tcl Message: INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_1
|
||||
// Tcl Message: INFO: [xilinx.com:ip:ila:6.2-6] /ila_1: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_2
|
||||
// Tcl Message: INFO: [xilinx.com:ip:ila:6.2-6] /ila_2: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps7_0_axi_periph Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_1 Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0 Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_3
|
||||
// Tcl Message: INFO: [xilinx.com:ip:ila:6.2-6] /ila_3: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
|
||||
// Tcl Message: Adding component instance block -- xilinx.com:module_ref:adc_capture_module:1.0 - adc_capture_module_0
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/project/hdl/ip'. INFO: [IP_Flow 19-3420] Updated design_1_adc_capture_module_0_0 to use current project options
|
||||
// Tcl Message: Successfully read diagram <design_1> from block design file <D:/project/hdl/ebaz4205_adc_test.git/axi_dma.srcs/sources_1/bd/design_1/design_1.bd>
|
||||
closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // t
|
||||
// Tcl Message: open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1494.906 ; gain = 30.781
|
||||
// JavaFX intialization before: 1672990783267
|
||||
dismissDialog("Open Block Design"); // bq
|
||||
// JavaFX initialization after: 1672990783550
|
||||
// WARNING: HTimer (Open addressing views timer) is taking 339ms to process. Increasing delay to 1300 ms.
|
||||
// [Engine Memory]: 1,409 MB (+8041kb) [00:01:40]
|
||||
// [Engine Memory]: 1,486 MB (+6600kb) [00:01:40]
|
||||
// [GUI Memory]: 145 MB (+8463kb) [00:01:48]
|
||||
Loading…
Reference in New Issue