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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:name>M_AXIS_TDATA</spirit:name>
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<spirit:name>M_AXIS_TLAST</spirit:name>
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<spirit:name>TREADY</spirit:name>
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<spirit:name>M_AXIS_TREADY</spirit:name>
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<spirit:name>HAS_TSTRB</spirit:name>
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<spirit:parameter>
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<spirit:name>HAS_TKEEP</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
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<spirit:name>HAS_TLAST</spirit:name>
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<spirit:vendorExtensions>
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<spirit:vendorExtensions>
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<spirit:name>PHASE</spirit:name>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
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<spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:name>LAYERED_METADATA</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
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<spirit:vendorExtensions>
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<spirit:parameter>
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||||
<spirit:name>INSERT_VIP</spirit:name>
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||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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</spirit:busInterface>
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<spirit:busInterface>
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||||
<spirit:name>M_AXIS_ARESETN</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>RST</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>M_AXIS_ARESETN</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>POLARITY</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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||||
</spirit:parameter>
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<spirit:parameter>
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||||
<spirit:name>INSERT_VIP</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ARESETN.INSERT_VIP">0</spirit:value>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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<spirit:busInterface>
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<spirit:name>reset_n</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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<spirit:physicalPort>
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<spirit:name>reset_n</spirit:name>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RESET_N.POLARITY">ACTIVE_LOW</spirit:value>
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<spirit:name>INSERT_VIP</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET_N.INSERT_VIP">0</spirit:value>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>M_AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>M_AXIS_ACLK</spirit:name>
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||||
</spirit:physicalPort>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
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||||
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<spirit:parameter>
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||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_RESET">M_AXIS_ARESETN</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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<spirit:parameter>
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<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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<spirit:name>PHASE</spirit:name>
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||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.PHASE">0.0</spirit:value>
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<spirit:name>CLK_DOMAIN</spirit:name>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.CLK_DOMAIN"/>
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<spirit:name>ASSOCIATED_PORT</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.ASSOCIATED_PORT"/>
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<spirit:parameter>
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||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_ACLK.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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||||
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||||
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|
||||
<spirit:busInterface>
|
||||
<spirit:name>adc_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>adc_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.FREQ_HZ">100000000</spirit:value>
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
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||||
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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||||
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|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.CLK_DOMAIN"/>
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
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||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ADC_CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>adc_input</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>adc_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>reset_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>test_out</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>debug_status</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>debug_status2</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>debug_status3</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TSTRB</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>C_M_AXIS_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M Axis Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_M_START_COUNT</spirit:name>
|
||||
<spirit:displayName>C M Start Count</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_START_COUNT">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Capture Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Capture Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_CAPTURING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Capture Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Send Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Send Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_SENDING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Send Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_IDLE</spirit:name>
|
||||
<spirit:displayName>Send Status Idle</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_IDLE" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_FULL</spirit:name>
|
||||
<spirit:displayName>Buffer Status Full</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_FULL" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_SENDING" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_CAPTURING" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_EMPTY</spirit:name>
|
||||
<spirit:displayName>Buffer Status Empty</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_EMPTY" spirit:bitStringLength="8">"00000100"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:description>xilinx.com:module_ref:adc_capture_module:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M_AXIS_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M Axis Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXIS_TDATA_WIDTH">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M_START_COUNT</spirit:name>
|
||||
<spirit:displayName>C M Start Count</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_START_COUNT">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Capture Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Capture Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_CAPTURING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Capture Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Send Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Send Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_SENDING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Send Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_IDLE</spirit:name>
|
||||
<spirit:displayName>Send Status Idle</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_IDLE" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_FULL</spirit:name>
|
||||
<spirit:displayName>Buffer Status Full</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_FULL" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_SENDING" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_CAPTURING" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_EMPTY</spirit:name>
|
||||
<spirit:displayName>Buffer Status Empty</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_EMPTY" spirit:bitStringLength="8">"00000100"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
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|
|
@ -0,0 +1,16 @@
|
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
| Date : Fri Jan 6 15:39:41 2023
|
||||
| Host : home-pc running 64-bit major release (build 9200)
|
||||
| Command : upgrade_ip
|
||||
| Device : xc7z010clg400-1
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Upgrade Log for IP 'design_1_adc_capture_module_0_0'
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
SUCCESS in the conversion of design_1_adc_capture_module_0_0 (xilinx.com:module_ref:adc_capture_module:1.0 (Rev. 1)) to Vivado generation flows.
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
{
|
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"design": {
|
||||
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|
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"boundary_crc": "0x0",
|
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TSTRB</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>C_M_AXIS_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M Axis Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_M_START_COUNT</spirit:name>
|
||||
<spirit:displayName>C M Start Count</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_START_COUNT">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Capture Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Capture Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_CAPTURING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CAPTURE_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Capture Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CAPTURE_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Send Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Send Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_SENDING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Send Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEND_STATUS_IDLE</spirit:name>
|
||||
<spirit:displayName>Send Status Idle</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEND_STATUS_IDLE" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_FULL</spirit:name>
|
||||
<spirit:displayName>Buffer Status Full</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_FULL" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_SENDING" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_CAPTURING" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_STATUS_EMPTY</spirit:name>
|
||||
<spirit:displayName>Buffer Status Empty</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_STATUS_EMPTY" spirit:bitStringLength="8">"00000100"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/adc_capture_module_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_7df2a4a6</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:adc_capture_module:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M_AXIS_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M Axis Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXIS_TDATA_WIDTH">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M_START_COUNT</spirit:name>
|
||||
<spirit:displayName>C M Start Count</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_START_COUNT">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Capture Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Capture Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_CAPTURING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAPTURE_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Capture Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.CAPTURE_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_STOP</spirit:name>
|
||||
<spirit:displayName>Send Status Stop</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_STOP" spirit:bitStringLength="8">"00000001"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Send Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_SENDING" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_SEND_START</spirit:name>
|
||||
<spirit:displayName>Send Status Send Start</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_SEND_START" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEND_STATUS_IDLE</spirit:name>
|
||||
<spirit:displayName>Send Status Idle</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SEND_STATUS_IDLE" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_FULL</spirit:name>
|
||||
<spirit:displayName>Buffer Status Full</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_FULL" spirit:bitStringLength="8">"00000000"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_SENDING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Sending</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_SENDING" spirit:bitStringLength="8">"00000010"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_CAPTURING</spirit:name>
|
||||
<spirit:displayName>Buffer Status Capturing</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_CAPTURING" spirit:bitStringLength="8">"00000011"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUFFER_STATUS_EMPTY</spirit:name>
|
||||
<spirit:displayName>Buffer Status Empty</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_STATUS_EMPTY" spirit:bitStringLength="8">"00000100"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">adc_capture_module_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>adc_capture_module_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2023-01-06T07:39:41Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "BUFFER_STATUS_CAPTURING" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "BUFFER_STATUS_EMPTY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "BUFFER_STATUS_FULL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "BUFFER_STATUS_SENDING" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CAPTURE_STATUS_CAPTURING" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CAPTURE_STATUS_SEND_START" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CAPTURE_STATUS_STOP" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_M_AXIS_TDATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_M_START_COUNT" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SEND_STATUS_IDLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SEND_STATUS_SENDING" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SEND_STATUS_SEND_START" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SEND_STATUS_STOP" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUFFER_STATUS_CAPTURING { PARAM_VALUE.BUFFER_STATUS_CAPTURING } {
|
||||
# Procedure called to update BUFFER_STATUS_CAPTURING when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUFFER_STATUS_CAPTURING { PARAM_VALUE.BUFFER_STATUS_CAPTURING } {
|
||||
# Procedure called to validate BUFFER_STATUS_CAPTURING
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUFFER_STATUS_EMPTY { PARAM_VALUE.BUFFER_STATUS_EMPTY } {
|
||||
# Procedure called to update BUFFER_STATUS_EMPTY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUFFER_STATUS_EMPTY { PARAM_VALUE.BUFFER_STATUS_EMPTY } {
|
||||
# Procedure called to validate BUFFER_STATUS_EMPTY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUFFER_STATUS_FULL { PARAM_VALUE.BUFFER_STATUS_FULL } {
|
||||
# Procedure called to update BUFFER_STATUS_FULL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUFFER_STATUS_FULL { PARAM_VALUE.BUFFER_STATUS_FULL } {
|
||||
# Procedure called to validate BUFFER_STATUS_FULL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUFFER_STATUS_SENDING { PARAM_VALUE.BUFFER_STATUS_SENDING } {
|
||||
# Procedure called to update BUFFER_STATUS_SENDING when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUFFER_STATUS_SENDING { PARAM_VALUE.BUFFER_STATUS_SENDING } {
|
||||
# Procedure called to validate BUFFER_STATUS_SENDING
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CAPTURE_STATUS_CAPTURING { PARAM_VALUE.CAPTURE_STATUS_CAPTURING } {
|
||||
# Procedure called to update CAPTURE_STATUS_CAPTURING when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CAPTURE_STATUS_CAPTURING { PARAM_VALUE.CAPTURE_STATUS_CAPTURING } {
|
||||
# Procedure called to validate CAPTURE_STATUS_CAPTURING
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CAPTURE_STATUS_SEND_START { PARAM_VALUE.CAPTURE_STATUS_SEND_START } {
|
||||
# Procedure called to update CAPTURE_STATUS_SEND_START when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CAPTURE_STATUS_SEND_START { PARAM_VALUE.CAPTURE_STATUS_SEND_START } {
|
||||
# Procedure called to validate CAPTURE_STATUS_SEND_START
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CAPTURE_STATUS_STOP { PARAM_VALUE.CAPTURE_STATUS_STOP } {
|
||||
# Procedure called to update CAPTURE_STATUS_STOP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CAPTURE_STATUS_STOP { PARAM_VALUE.CAPTURE_STATUS_STOP } {
|
||||
# Procedure called to validate CAPTURE_STATUS_STOP
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } {
|
||||
# Procedure called to update C_M_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } {
|
||||
# Procedure called to validate C_M_AXIS_TDATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_M_START_COUNT { PARAM_VALUE.C_M_START_COUNT } {
|
||||
# Procedure called to update C_M_START_COUNT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_M_START_COUNT { PARAM_VALUE.C_M_START_COUNT } {
|
||||
# Procedure called to validate C_M_START_COUNT
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SEND_STATUS_IDLE { PARAM_VALUE.SEND_STATUS_IDLE } {
|
||||
# Procedure called to update SEND_STATUS_IDLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SEND_STATUS_IDLE { PARAM_VALUE.SEND_STATUS_IDLE } {
|
||||
# Procedure called to validate SEND_STATUS_IDLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SEND_STATUS_SENDING { PARAM_VALUE.SEND_STATUS_SENDING } {
|
||||
# Procedure called to update SEND_STATUS_SENDING when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SEND_STATUS_SENDING { PARAM_VALUE.SEND_STATUS_SENDING } {
|
||||
# Procedure called to validate SEND_STATUS_SENDING
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SEND_STATUS_SEND_START { PARAM_VALUE.SEND_STATUS_SEND_START } {
|
||||
# Procedure called to update SEND_STATUS_SEND_START when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SEND_STATUS_SEND_START { PARAM_VALUE.SEND_STATUS_SEND_START } {
|
||||
# Procedure called to validate SEND_STATUS_SEND_START
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SEND_STATUS_STOP { PARAM_VALUE.SEND_STATUS_STOP } {
|
||||
# Procedure called to update SEND_STATUS_STOP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SEND_STATUS_STOP { PARAM_VALUE.SEND_STATUS_STOP } {
|
||||
# Procedure called to validate SEND_STATUS_STOP
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_M_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_M_START_COUNT { MODELPARAM_VALUE.C_M_START_COUNT PARAM_VALUE.C_M_START_COUNT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_M_START_COUNT}] ${MODELPARAM_VALUE.C_M_START_COUNT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CAPTURE_STATUS_STOP { MODELPARAM_VALUE.CAPTURE_STATUS_STOP PARAM_VALUE.CAPTURE_STATUS_STOP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CAPTURE_STATUS_STOP}] ${MODELPARAM_VALUE.CAPTURE_STATUS_STOP}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CAPTURE_STATUS_CAPTURING { MODELPARAM_VALUE.CAPTURE_STATUS_CAPTURING PARAM_VALUE.CAPTURE_STATUS_CAPTURING } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CAPTURE_STATUS_CAPTURING}] ${MODELPARAM_VALUE.CAPTURE_STATUS_CAPTURING}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CAPTURE_STATUS_SEND_START { MODELPARAM_VALUE.CAPTURE_STATUS_SEND_START PARAM_VALUE.CAPTURE_STATUS_SEND_START } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CAPTURE_STATUS_SEND_START}] ${MODELPARAM_VALUE.CAPTURE_STATUS_SEND_START}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SEND_STATUS_STOP { MODELPARAM_VALUE.SEND_STATUS_STOP PARAM_VALUE.SEND_STATUS_STOP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SEND_STATUS_STOP}] ${MODELPARAM_VALUE.SEND_STATUS_STOP}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SEND_STATUS_SENDING { MODELPARAM_VALUE.SEND_STATUS_SENDING PARAM_VALUE.SEND_STATUS_SENDING } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SEND_STATUS_SENDING}] ${MODELPARAM_VALUE.SEND_STATUS_SENDING}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SEND_STATUS_SEND_START { MODELPARAM_VALUE.SEND_STATUS_SEND_START PARAM_VALUE.SEND_STATUS_SEND_START } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SEND_STATUS_SEND_START}] ${MODELPARAM_VALUE.SEND_STATUS_SEND_START}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SEND_STATUS_IDLE { MODELPARAM_VALUE.SEND_STATUS_IDLE PARAM_VALUE.SEND_STATUS_IDLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SEND_STATUS_IDLE}] ${MODELPARAM_VALUE.SEND_STATUS_IDLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUFFER_STATUS_FULL { MODELPARAM_VALUE.BUFFER_STATUS_FULL PARAM_VALUE.BUFFER_STATUS_FULL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUFFER_STATUS_FULL}] ${MODELPARAM_VALUE.BUFFER_STATUS_FULL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUFFER_STATUS_SENDING { MODELPARAM_VALUE.BUFFER_STATUS_SENDING PARAM_VALUE.BUFFER_STATUS_SENDING } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUFFER_STATUS_SENDING}] ${MODELPARAM_VALUE.BUFFER_STATUS_SENDING}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUFFER_STATUS_CAPTURING { MODELPARAM_VALUE.BUFFER_STATUS_CAPTURING PARAM_VALUE.BUFFER_STATUS_CAPTURING } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUFFER_STATUS_CAPTURING}] ${MODELPARAM_VALUE.BUFFER_STATUS_CAPTURING}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUFFER_STATUS_EMPTY { MODELPARAM_VALUE.BUFFER_STATUS_EMPTY PARAM_VALUE.BUFFER_STATUS_EMPTY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUFFER_STATUS_EMPTY}] ${MODELPARAM_VALUE.BUFFER_STATUS_EMPTY}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0">
|
||||
<HWSession Dir="hw_1" File="hw.xml"/>
|
||||
</labtools>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,59 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="D:/project/hdl/axi_dma/axi_dma.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
|
||||
<top_modules>
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0"></ZoomStartTime>
|
||||
<ZoomEndTime time="2,005"></ZoomEndTime>
|
||||
<Cursor1Time time="762"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="478"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="188"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="4" />
|
||||
<wave_markers>
|
||||
</wave_markers>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_M_AXIS_TDATA" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_M_AXIS_TDATA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_M_AXIS_TDATA[31:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
<obj_property name="AnalogYRangeType">ANALOG_YRANGETYPE_AUTO</obj_property>
|
||||
<obj_property name="AnalogYRangeMin">0.000000</obj_property>
|
||||
<obj_property name="AnalogYRRangeMax">0.000000</obj_property>
|
||||
<obj_property name="AnalogInterpolation">ANALOG_INTERPOLATION_HOLD</obj_property>
|
||||
<obj_property name="AnalogOffscale">ANALOG_OFFSCALE_HIDE</obj_property>
|
||||
<obj_property name="AnalogHorizLine">0.000000</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_M_AXIS_TSTRB" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_M_AXIS_TSTRB[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_M_AXIS_TSTRB[3:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_M_AXIS_TREADY" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_M_AXIS_TREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_M_AXIS_TREADY</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_M_AXIS_TVALID" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_M_AXIS_TVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_M_AXIS_TVALID</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,49 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="D:/project/hdl/axi_dma/axi_dma.hw/hw_1/wave/hw_ila_data_2/hw_ila_data_2.wdb" id="1">
|
||||
<top_modules>
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0"></ZoomStartTime>
|
||||
<ZoomEndTime time="16"></ZoomEndTime>
|
||||
<Cursor1Time time="0"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="76"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="72"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="4" />
|
||||
<wvobject fp_name="design_1_i/axi_dma_0_s2mm_prmry_reset_out_n" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/axi_dma_0_s2mm_prmry_reset_out_n</obj_property>
|
||||
<obj_property name="ObjectShortName">axi_dma_0_s2mm_prmry_reset_out_n</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/xlconcat_0_dout" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/xlconcat_0_dout</obj_property>
|
||||
<obj_property name="ObjectShortName">xlconcat_0_dout</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/processing_system7_0_FCLK_RESET0_N_1" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/processing_system7_0_FCLK_RESET0_N_1</obj_property>
|
||||
<obj_property name="ObjectShortName">processing_system7_0_FCLK_RESET0_N_1</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/processing_system7_0_FCLK_RESET1_N" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/processing_system7_0_FCLK_RESET1_N</obj_property>
|
||||
<obj_property name="ObjectShortName">processing_system7_0_FCLK_RESET1_N</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,75 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="D:/project/hdl/axi_dma/axi_dma.hw/hw_1/wave/hw_ila_data_3/hw_ila_data_3.wdb" id="1">
|
||||
<top_modules>
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0"></ZoomStartTime>
|
||||
<ZoomEndTime time="12"></ZoomEndTime>
|
||||
<Cursor1Time time="0"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="409"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="72"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="7" />
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_debug_status" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_debug_status[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_debug_status[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_test_out" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_test_out</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_test_out</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_test_out_1" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_test_out_1</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_test_out_1</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_input_0_1" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_input_0_1[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_input_0_1[7:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ANALOG</obj_property>
|
||||
<obj_property name="CellHeight">100</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/clk_wiz_0_clk_out1" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/clk_wiz_0_clk_out1</obj_property>
|
||||
<obj_property name="ObjectShortName">clk_wiz_0_clk_out1</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_debug_status2" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_debug_status2[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_debug_status2[7:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="design_1_i/adc_capture_module_0_debug_status3" type="array">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">design_1_i/adc_capture_module_0_debug_status3[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_capture_module_0_debug_status3[1:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,133 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:adc_capture_module:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_adc_capture_module_0_0 (
|
||||
adc_input,
|
||||
adc_clk,
|
||||
reset_n,
|
||||
test_out,
|
||||
debug_status,
|
||||
debug_status2,
|
||||
debug_status3,
|
||||
M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TSTRB,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY
|
||||
);
|
||||
|
||||
input wire [7 : 0] adc_input;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME adc_clk, FREQ_HZ 5000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 adc_clk CLK" *)
|
||||
input wire adc_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME reset_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_n RST" *)
|
||||
input wire reset_n;
|
||||
output wire test_out;
|
||||
output wire [7 : 0] debug_status;
|
||||
output wire [7 : 0] debug_status2;
|
||||
output wire [1 : 0] debug_status3;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_ACLK CLK" *)
|
||||
input wire M_AXIS_ACLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_ARESETN RST" *)
|
||||
input wire M_AXIS_ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [31 : 0] M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
|
||||
output wire [3 : 0] M_AXIS_TSTRB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
|
||||
output wire M_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 1, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire M_AXIS_TREADY;
|
||||
|
||||
adc_capture_module #(
|
||||
.C_M_AXIS_TDATA_WIDTH(32),
|
||||
.C_M_START_COUNT(32),
|
||||
.CAPTURE_STATUS_STOP(8'B00000001),
|
||||
.CAPTURE_STATUS_CAPTURING(8'B00000000),
|
||||
.CAPTURE_STATUS_SEND_START(8'B00000010),
|
||||
.SEND_STATUS_STOP(8'B00000001),
|
||||
.SEND_STATUS_SENDING(8'B00000000),
|
||||
.SEND_STATUS_SEND_START(8'B00000010),
|
||||
.SEND_STATUS_IDLE(8'B00000011),
|
||||
.BUFFER_STATUS_FULL(8'B00000000),
|
||||
.BUFFER_STATUS_SENDING(8'B00000010),
|
||||
.BUFFER_STATUS_CAPTURING(8'B00000011),
|
||||
.BUFFER_STATUS_EMPTY(8'B00000100)
|
||||
) inst (
|
||||
.adc_input(adc_input),
|
||||
.adc_clk(adc_clk),
|
||||
.reset_n(reset_n),
|
||||
.test_out(test_out),
|
||||
.debug_status(debug_status),
|
||||
.debug_status2(debug_status2),
|
||||
.debug_status3(debug_status3),
|
||||
.M_AXIS_ACLK(M_AXIS_ACLK),
|
||||
.M_AXIS_ARESETN(M_AXIS_ARESETN),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TSTRB(M_AXIS_TSTRB),
|
||||
.M_AXIS_TLAST(M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,354 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 27
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_27_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,569 @@
|
|||
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 28
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_28;
|
||||
USE axi_dma_v7_1_28.axi_dma;
|
||||
|
||||
ENTITY design_1_axi_dma_0_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_dma_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE" &
|
||||
"ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR" &
|
||||
"EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_sg_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_SG_CLK, ASSOCIATED_BUSIF M_AXI_SG, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_sg_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_SG, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_mm2s_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0, HAS_BURST 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_introut: SIGNAL IS "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 2";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T" &
|
||||
"HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 0,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 1,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 14,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 32,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 1,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 64,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 0,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 64,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_S2MM_DRE => 0,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => m_axi_sg_aclk,
|
||||
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awaddr => m_axi_sg_awaddr,
|
||||
m_axi_sg_awlen => m_axi_sg_awlen,
|
||||
m_axi_sg_awsize => m_axi_sg_awsize,
|
||||
m_axi_sg_awburst => m_axi_sg_awburst,
|
||||
m_axi_sg_awprot => m_axi_sg_awprot,
|
||||
m_axi_sg_awcache => m_axi_sg_awcache,
|
||||
m_axi_sg_awvalid => m_axi_sg_awvalid,
|
||||
m_axi_sg_awready => m_axi_sg_awready,
|
||||
m_axi_sg_wdata => m_axi_sg_wdata,
|
||||
m_axi_sg_wstrb => m_axi_sg_wstrb,
|
||||
m_axi_sg_wlast => m_axi_sg_wlast,
|
||||
m_axi_sg_wvalid => m_axi_sg_wvalid,
|
||||
m_axi_sg_wready => m_axi_sg_wready,
|
||||
m_axi_sg_bresp => m_axi_sg_bresp,
|
||||
m_axi_sg_bvalid => m_axi_sg_bvalid,
|
||||
m_axi_sg_bready => m_axi_sg_bready,
|
||||
m_axi_sg_araddr => m_axi_sg_araddr,
|
||||
m_axi_sg_arlen => m_axi_sg_arlen,
|
||||
m_axi_sg_arsize => m_axi_sg_arsize,
|
||||
m_axi_sg_arburst => m_axi_sg_arburst,
|
||||
m_axi_sg_arprot => m_axi_sg_arprot,
|
||||
m_axi_sg_arcache => m_axi_sg_arcache,
|
||||
m_axi_sg_arvalid => m_axi_sg_arvalid,
|
||||
m_axi_sg_arready => m_axi_sg_arready,
|
||||
m_axi_sg_rdata => m_axi_sg_rdata,
|
||||
m_axi_sg_rresp => m_axi_sg_rresp,
|
||||
m_axi_sg_rlast => m_axi_sg_rlast,
|
||||
m_axi_sg_rvalid => m_axi_sg_rvalid,
|
||||
m_axi_sg_rready => m_axi_sg_rready,
|
||||
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
|
||||
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
|
||||
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
|
||||
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
|
||||
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready => m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
|
||||
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
|
||||
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready => m_axi_mm2s_rready,
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
|
||||
m_axis_mm2s_tready => m_axis_mm2s_tready,
|
||||
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
mm2s_introut => mm2s_introut,
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END design_1_axi_dma_0_0_arch;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,68 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY bd_6f02_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_6f02_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_6f02_psr_aclk_0_arch OF bd_6f02_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_6f02_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_6f02_psr_aclk_0_arch;
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s00a2s_0 (
|
||||
aclk,
|
||||
s_sc_r_req,
|
||||
s_sc_r_info,
|
||||
s_sc_r_send,
|
||||
s_sc_r_recv,
|
||||
s_sc_r_payld,
|
||||
m_sc_ar_req,
|
||||
m_sc_ar_info,
|
||||
m_sc_ar_send,
|
||||
m_sc_ar_recv,
|
||||
m_sc_ar_payld,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
input wire s_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R INFO" *)
|
||||
input wire [0 : 0] s_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R SEND" *)
|
||||
input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [53 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
output wire [0 : 0] m_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR SEND" *)
|
||||
output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [139 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
|
||||
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(3),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(54),
|
||||
.C_BPAYLD_WIDTH(8)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
.s_sc_r_info(s_sc_r_info),
|
||||
.s_sc_r_send(s_sc_r_send),
|
||||
.s_sc_r_recv(s_sc_r_recv),
|
||||
.s_sc_r_payld(s_sc_r_payld),
|
||||
.s_sc_b_req(1'D0),
|
||||
.s_sc_b_info(1'D0),
|
||||
.s_sc_b_send(1'D0),
|
||||
.s_sc_b_recv(),
|
||||
.s_sc_b_payld(8'D0),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
.m_sc_ar_recv(m_sc_ar_recv),
|
||||
.m_sc_ar_payld(m_sc_ar_payld),
|
||||
.m_sc_aw_req(),
|
||||
.m_sc_aw_info(),
|
||||
.m_sc_aw_send(),
|
||||
.m_sc_aw_recv(1'D0),
|
||||
.m_sc_aw_payld(),
|
||||
.m_sc_w_req(),
|
||||
.m_sc_w_info(),
|
||||
.m_sc_w_send(),
|
||||
.m_sc_w_recv(1'D0),
|
||||
.m_sc_w_payld(),
|
||||
.s_axi_awid(2'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1024'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1024'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sarn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_srn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [53 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [53 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(54),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,313 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s01mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_mmu_v1_0_11_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'H1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'H1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s01tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK\
|
||||
_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_transaction_regulator_v1_0_9_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER(3),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(2'H3),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_si_converter:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s01sic_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK\
|
||||
_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_si_converter_v1_0_11_top #(
|
||||
.C_AXILITE_CONV(0),
|
||||
.C_LIMIT_WRITE_LENGTH(0),
|
||||
.C_LIMIT_READ_LENGTH(0),
|
||||
.C_WRITE_WATERMARK(0),
|
||||
.C_READ_WATERMARK(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEP_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_PROTOCOL_ARRAY(32'H00000001),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
.C_S_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(2'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s01a2s_0 (
|
||||
aclk,
|
||||
s_sc_b_req,
|
||||
s_sc_b_info,
|
||||
s_sc_b_send,
|
||||
s_sc_b_recv,
|
||||
s_sc_b_payld,
|
||||
m_sc_aw_req,
|
||||
m_sc_aw_info,
|
||||
m_sc_aw_send,
|
||||
m_sc_aw_recv,
|
||||
m_sc_aw_payld,
|
||||
m_sc_w_req,
|
||||
m_sc_w_info,
|
||||
m_sc_w_send,
|
||||
m_sc_w_recv,
|
||||
m_sc_w_payld,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B REQ" *)
|
||||
input wire s_sc_b_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B INFO" *)
|
||||
input wire [0 : 0] s_sc_b_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B SEND" *)
|
||||
input wire s_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B RECV" *)
|
||||
output wire s_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B PAYLD" *)
|
||||
input wire [7 : 0] s_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW REQ" *)
|
||||
output wire m_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW INFO" *)
|
||||
output wire [0 : 0] m_sc_aw_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW SEND" *)
|
||||
output wire m_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW RECV" *)
|
||||
input wire m_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW PAYLD" *)
|
||||
output wire [139 : 0] m_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W REQ" *)
|
||||
output wire m_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W INFO" *)
|
||||
output wire [0 : 0] m_sc_w_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W SEND" *)
|
||||
output wire m_sc_w_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W RECV" *)
|
||||
input wire m_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W PAYLD" *)
|
||||
output wire [51 : 0] m_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(3),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(54),
|
||||
.C_BPAYLD_WIDTH(8)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(1'D0),
|
||||
.s_sc_r_info(1'D0),
|
||||
.s_sc_r_send(1'D0),
|
||||
.s_sc_r_recv(),
|
||||
.s_sc_r_payld(54'D0),
|
||||
.s_sc_b_req(s_sc_b_req),
|
||||
.s_sc_b_info(s_sc_b_info),
|
||||
.s_sc_b_send(s_sc_b_send),
|
||||
.s_sc_b_recv(s_sc_b_recv),
|
||||
.s_sc_b_payld(s_sc_b_payld),
|
||||
.m_sc_ar_req(),
|
||||
.m_sc_ar_info(),
|
||||
.m_sc_ar_send(),
|
||||
.m_sc_ar_recv(1'D0),
|
||||
.m_sc_ar_payld(),
|
||||
.m_sc_aw_req(m_sc_aw_req),
|
||||
.m_sc_aw_info(m_sc_aw_info),
|
||||
.m_sc_aw_send(m_sc_aw_send),
|
||||
.m_sc_aw_recv(m_sc_aw_recv),
|
||||
.m_sc_aw_payld(m_sc_aw_payld),
|
||||
.m_sc_w_req(m_sc_w_req),
|
||||
.m_sc_w_info(m_sc_w_info),
|
||||
.m_sc_w_send(m_sc_w_send),
|
||||
.m_sc_w_recv(m_sc_w_recv),
|
||||
.m_sc_w_payld(m_sc_w_payld),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(2'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sawn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(3),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_swn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [51 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [51 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(1),
|
||||
.C_PAYLD_WIDTH(52),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sbn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [7 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [7 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(8),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_switchboard:1.0
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_arsw_0 (
|
||||
aclk,
|
||||
aclken,
|
||||
s_sc_send,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_payld,
|
||||
s_sc_recv,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC SEND [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC REQ [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC INFO [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [139:0] [139:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [139:0] [279:140], xilinx.com:interface:sc:1.0 S02_SC PAYLD [139:0] [419:280]" *)
|
||||
input wire [419 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S02_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC RECV [0:0] [2:2]" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(3'B111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(3'B111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s02mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1\
|
||||
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_mmu_v1_0_11_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'H1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'H1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,423 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s02tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_\
|
||||
0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [1 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [1 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_transaction_regulator_v1_0_9_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER(1),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(2'H1),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,424 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_si_converter:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s02sic_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_\
|
||||
0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [1 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [1 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_si_converter_v1_0_11_top #(
|
||||
.C_AXILITE_CONV(0),
|
||||
.C_LIMIT_WRITE_LENGTH(0),
|
||||
.C_LIMIT_READ_LENGTH(0),
|
||||
.C_WRITE_WATERMARK(0),
|
||||
.C_READ_WATERMARK(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEP_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_PROTOCOL_ARRAY(32'H00000001),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
.C_S_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s02a2s_0 (
|
||||
aclk,
|
||||
s_sc_r_req,
|
||||
s_sc_r_info,
|
||||
s_sc_r_send,
|
||||
s_sc_r_recv,
|
||||
s_sc_r_payld,
|
||||
s_sc_b_req,
|
||||
s_sc_b_info,
|
||||
s_sc_b_send,
|
||||
s_sc_b_recv,
|
||||
s_sc_b_payld,
|
||||
m_sc_ar_req,
|
||||
m_sc_ar_info,
|
||||
m_sc_ar_send,
|
||||
m_sc_ar_recv,
|
||||
m_sc_ar_payld,
|
||||
m_sc_aw_req,
|
||||
m_sc_aw_info,
|
||||
m_sc_aw_send,
|
||||
m_sc_aw_recv,
|
||||
m_sc_aw_payld,
|
||||
m_sc_w_req,
|
||||
m_sc_w_info,
|
||||
m_sc_w_send,
|
||||
m_sc_w_recv,
|
||||
m_sc_w_payld,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
input wire s_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R INFO" *)
|
||||
input wire [0 : 0] s_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R SEND" *)
|
||||
input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [53 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B REQ" *)
|
||||
input wire s_sc_b_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B INFO" *)
|
||||
input wire [0 : 0] s_sc_b_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B SEND" *)
|
||||
input wire s_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B RECV" *)
|
||||
output wire s_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_B PAYLD" *)
|
||||
input wire [7 : 0] s_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
output wire [0 : 0] m_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR SEND" *)
|
||||
output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [139 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW REQ" *)
|
||||
output wire m_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW INFO" *)
|
||||
output wire [0 : 0] m_sc_aw_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW SEND" *)
|
||||
output wire m_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW RECV" *)
|
||||
input wire m_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AW PAYLD" *)
|
||||
output wire [139 : 0] m_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W REQ" *)
|
||||
output wire m_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W INFO" *)
|
||||
output wire [0 : 0] m_sc_w_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W SEND" *)
|
||||
output wire m_sc_w_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W RECV" *)
|
||||
input wire m_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_W PAYLD" *)
|
||||
output wire [51 : 0] m_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(3),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(54),
|
||||
.C_BPAYLD_WIDTH(8)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
.s_sc_r_info(s_sc_r_info),
|
||||
.s_sc_r_send(s_sc_r_send),
|
||||
.s_sc_r_recv(s_sc_r_recv),
|
||||
.s_sc_r_payld(s_sc_r_payld),
|
||||
.s_sc_b_req(s_sc_b_req),
|
||||
.s_sc_b_info(s_sc_b_info),
|
||||
.s_sc_b_send(s_sc_b_send),
|
||||
.s_sc_b_recv(s_sc_b_recv),
|
||||
.s_sc_b_payld(s_sc_b_payld),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
.m_sc_ar_recv(m_sc_ar_recv),
|
||||
.m_sc_ar_payld(m_sc_ar_payld),
|
||||
.m_sc_aw_req(m_sc_aw_req),
|
||||
.m_sc_aw_info(m_sc_aw_info),
|
||||
.m_sc_aw_send(m_sc_aw_send),
|
||||
.m_sc_aw_recv(m_sc_aw_recv),
|
||||
.m_sc_aw_payld(m_sc_aw_payld),
|
||||
.m_sc_w_req(m_sc_w_req),
|
||||
.m_sc_w_info(m_sc_w_info),
|
||||
.m_sc_w_send(m_sc_w_send),
|
||||
.m_sc_w_recv(m_sc_w_recv),
|
||||
.m_sc_w_payld(m_sc_w_payld),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sarn_1 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(2),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_srn_1 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [53 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [53 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(54),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(2),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sawn_1 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(3),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(2),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_swn_1 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [51 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [51 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(1),
|
||||
.C_PAYLD_WIDTH(52),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(2),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_sbn_1 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [7 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [7 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(8),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(2),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_sc2axi:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00s2a_0 (
|
||||
aclk,
|
||||
m_sc_r_req,
|
||||
m_sc_r_info,
|
||||
m_sc_r_send,
|
||||
m_sc_r_recv,
|
||||
m_sc_r_payld,
|
||||
m_sc_b_req,
|
||||
m_sc_b_info,
|
||||
m_sc_b_send,
|
||||
m_sc_b_recv,
|
||||
m_sc_b_payld,
|
||||
s_sc_ar_req,
|
||||
s_sc_ar_info,
|
||||
s_sc_ar_send,
|
||||
s_sc_ar_recv,
|
||||
s_sc_ar_payld,
|
||||
s_sc_aw_req,
|
||||
s_sc_aw_info,
|
||||
s_sc_aw_send,
|
||||
s_sc_aw_recv,
|
||||
s_sc_aw_payld,
|
||||
s_sc_w_req,
|
||||
s_sc_w_info,
|
||||
s_sc_w_send,
|
||||
s_sc_w_recv,
|
||||
s_sc_w_payld,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF M_AXI:S_AW_SC:S_AR_SC:S_W_SC:M_R_SC:M_W_SC, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R REQ" *)
|
||||
output wire m_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R INFO" *)
|
||||
output wire [0 : 0] m_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R SEND" *)
|
||||
output wire m_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R RECV" *)
|
||||
input wire m_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R PAYLD" *)
|
||||
output wire [53 : 0] m_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B REQ" *)
|
||||
output wire m_sc_b_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B INFO" *)
|
||||
output wire [0 : 0] m_sc_b_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B SEND" *)
|
||||
output wire m_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B RECV" *)
|
||||
input wire m_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B PAYLD" *)
|
||||
output wire [7 : 0] m_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR REQ" *)
|
||||
input wire s_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR INFO" *)
|
||||
input wire [0 : 0] s_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR SEND" *)
|
||||
input wire s_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR RECV" *)
|
||||
output wire s_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR PAYLD" *)
|
||||
input wire [139 : 0] s_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW REQ" *)
|
||||
input wire s_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW INFO" *)
|
||||
input wire [0 : 0] s_sc_aw_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW SEND" *)
|
||||
input wire s_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW RECV" *)
|
||||
output wire s_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW PAYLD" *)
|
||||
input wire [139 : 0] s_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W REQ" *)
|
||||
input wire s_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W INFO" *)
|
||||
input wire [0 : 0] s_sc_w_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W SEND" *)
|
||||
input wire s_sc_w_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W RECV" *)
|
||||
output wire s_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W PAYLD" *)
|
||||
input wire [51 : 0] s_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [1 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [1 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [1 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [1 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_sc2axi_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(2),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(2),
|
||||
.C_SC_RDATA_WIDTH(32),
|
||||
.C_SC_WDATA_WIDTH(32),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(3),
|
||||
.C_AWPAYLD_WIDTH(140),
|
||||
.C_ARPAYLD_WIDTH(140),
|
||||
.C_WPAYLD_WIDTH(52),
|
||||
.C_RPAYLD_WIDTH(54),
|
||||
.C_BPAYLD_WIDTH(8)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.m_sc_r_req(m_sc_r_req),
|
||||
.m_sc_r_info(m_sc_r_info),
|
||||
.m_sc_r_send(m_sc_r_send),
|
||||
.m_sc_r_recv(m_sc_r_recv),
|
||||
.m_sc_r_payld(m_sc_r_payld),
|
||||
.m_sc_b_req(m_sc_b_req),
|
||||
.m_sc_b_info(m_sc_b_info),
|
||||
.m_sc_b_send(m_sc_b_send),
|
||||
.m_sc_b_recv(m_sc_b_recv),
|
||||
.m_sc_b_payld(m_sc_b_payld),
|
||||
.s_sc_ar_req(s_sc_ar_req),
|
||||
.s_sc_ar_info(s_sc_ar_info),
|
||||
.s_sc_ar_send(s_sc_ar_send),
|
||||
.s_sc_ar_recv(s_sc_ar_recv),
|
||||
.s_sc_ar_payld(s_sc_ar_payld),
|
||||
.s_sc_aw_req(s_sc_aw_req),
|
||||
.s_sc_aw_info(s_sc_aw_info),
|
||||
.s_sc_aw_send(s_sc_aw_send),
|
||||
.s_sc_aw_recv(s_sc_aw_recv),
|
||||
.s_sc_aw_payld(s_sc_aw_payld),
|
||||
.s_sc_w_req(s_sc_w_req),
|
||||
.s_sc_w_info(s_sc_w_info),
|
||||
.s_sc_w_send(s_sc_w_send),
|
||||
.s_sc_w_recv(s_sc_w_recv),
|
||||
.s_sc_w_payld(s_sc_w_payld),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_switchboard:1.0
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_rsw_0 (
|
||||
aclk,
|
||||
aclken,
|
||||
s_sc_send,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_payld,
|
||||
s_sc_recv,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD" *)
|
||||
input wire [53 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC RECV [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC SEND [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC REQ [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC INFO [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD [53:0] [53:0], xilinx.com:interface:sc:1.0 M01_SC PAYLD [53:0] [107:54], xilinx.com:interface:sc:1.0 M02_SC PAYLD [53:0] [161:108]" *)
|
||||
output wire [161 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(54),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(3),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(3'B111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(3'B111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00arn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(96'H000000040000000400000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(3'B000),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00rn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [53 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [53 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(3),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(54),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(96'H000000040000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00awn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld,
|
||||
m_axis_arb_tvalid,
|
||||
m_axis_arb_tready,
|
||||
m_axis_arb_tdata
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [139 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_ARB TVALID" *)
|
||||
output wire m_axis_arb_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_ARB TREADY" *)
|
||||
input wire m_axis_arb_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_ARB, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_ARB TDATA" *)
|
||||
output wire [15 : 0] m_axis_arb_tdata;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(3),
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.C_S_NUM_BYTES_ARRAY(96'H000000040000000400000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(3'B000),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(m_axis_arb_tvalid),
|
||||
.m_axis_arb_tready(m_axis_arb_tready),
|
||||
.m_axis_arb_tdata(m_axis_arb_tdata),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00wn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld,
|
||||
s_axis_arb_tvalid,
|
||||
s_axis_arb_tready,
|
||||
s_axis_arb_tdata
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [51 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [51 : 0] m_sc_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_ARB TVALID" *)
|
||||
input wire s_axis_arb_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_ARB TREADY" *)
|
||||
output wire s_axis_arb_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_ARB, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_ARB TDATA" *)
|
||||
input wire [15 : 0] s_axis_arb_tdata;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(1),
|
||||
.C_PAYLD_WIDTH(52),
|
||||
.C_S_NUM_BYTES_ARRAY(96'H000000040000000400000004),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(3'B000),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(s_axis_arb_tvalid),
|
||||
.s_axis_arb_tready(s_axis_arb_tready),
|
||||
.s_axis_arb_tdata(s_axis_arb_tdata)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00bn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [7 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [7 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(3),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(8),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(96'H000000040000000400000004),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(3),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(4),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_exit:1.0
|
||||
// IP Revision: 13
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_m00e_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [1 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [1 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NU\
|
||||
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [3 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [1 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [3 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [1 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_exit_v1_0_13_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_SSC_ROUTE_WIDTH(3),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_SSC_ROUTE_ARRAY(12'B010001100000),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_M_RUSER_BITS_PER_BYTE(0),
|
||||
.C_M_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_M_ARUSER_WIDTH(0),
|
||||
.C_M_AWUSER_WIDTH(0),
|
||||
.C_M_RUSER_WIDTH(0),
|
||||
.C_M_WUSER_WIDTH(0),
|
||||
.C_M_BUSER_WIDTH(0),
|
||||
.C_S_ID_WIDTH(2),
|
||||
.C_M_ID_WIDTH(0),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_M_PROTOCOL(1),
|
||||
.C_HAS_LOCK(0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_M_LIMIT_READ_LENGTH(16),
|
||||
.C_M_LIMIT_WRITE_LENGTH(16),
|
||||
.C_NUM_READ_OUTSTANDING(16),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'B1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_switchboard:1.0
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_awsw_0 (
|
||||
aclk,
|
||||
aclken,
|
||||
s_sc_send,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_payld,
|
||||
s_sc_recv,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC SEND [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC REQ [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC INFO [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [139:0] [139:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [139:0] [279:140], xilinx.com:interface:sc:1.0 S02_SC PAYLD [139:0] [419:280]" *)
|
||||
input wire [419 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S02_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC RECV [0:0] [2:2]" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD" *)
|
||||
output wire [139 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(140),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(3'B111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(3'B111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_switchboard:1.0
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_wsw_0 (
|
||||
aclk,
|
||||
aclken,
|
||||
s_sc_send,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_payld,
|
||||
s_sc_recv,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC SEND [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC REQ [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC INFO [0:0] [2:2]" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD [51:0] [51:0], xilinx.com:interface:sc:1.0 S01_SC PAYLD [51:0] [103:52], xilinx.com:interface:sc:1.0 S02_SC PAYLD [51:0] [155:104]" *)
|
||||
input wire [155 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S01_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC, XIL_INTERFACENAME S02_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 S01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 S02_SC RECV [0:0] [2:2]" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD" *)
|
||||
output wire [51 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(52),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(3),
|
||||
.C_NUM_MI(1),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(3'B111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(3'B111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_switchboard:1.0
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_bsw_0 (
|
||||
aclk,
|
||||
aclken,
|
||||
s_sc_send,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_payld,
|
||||
s_sc_recv,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC:S00_SC:S01_SC:S02_SC:S03_SC:S04_SC:S05_SC:S06_SC:S07_SC:S08_SC:S09_SC:S10_SC:S11_SC:S12_SC:S13_SC:S14_SC:S15_SC, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclken, POLARITY ACTIVE_LOW" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken CE" *)
|
||||
input wire aclken;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC SEND" *)
|
||||
input wire [2 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC REQ" *)
|
||||
input wire [2 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC INFO" *)
|
||||
input wire [2 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC PAYLD" *)
|
||||
input wire [7 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_SC, BRIDGES M00_SC:M01_SC:M02_SC:M03_SC:M04_SC:M05_SC:M06_SC:M07_SC:M08_SC:M09_SC:M10_SC:M11_SC:M12_SC:M13_SC:M14_SC:M15_SC" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S00_SC RECV" *)
|
||||
output wire [2 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC RECV [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC RECV [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC RECV [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC SEND [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC SEND [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC SEND [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC REQ [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC REQ [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC REQ [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC INFO [0:0] [0:0], xilinx.com:interface:sc:1.0 M01_SC INFO [0:0] [1:1], xilinx.com:interface:sc:1.0 M02_SC INFO [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M00_SC PAYLD [7:0] [7:0], xilinx.com:interface:sc:1.0 M01_SC PAYLD [7:0] [15:8], xilinx.com:interface:sc:1.0 M02_SC PAYLD [7:0] [23:16]" *)
|
||||
output wire [23 : 0] m_sc_payld;
|
||||
|
||||
sc_switchboard_v1_0_6_top #(
|
||||
.C_PAYLD_WIDTH(8),
|
||||
.K_MAX_INFO_WIDTH(1),
|
||||
.C_S_PIPELINES(0),
|
||||
.C_M_PIPELINES(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(3),
|
||||
.C_TESTING_MODE(0),
|
||||
.C_CONNECTIVITY(3'B111)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(aclken),
|
||||
.connectivity(3'B111),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s00mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1\
|
||||
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
|
||||
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_mmu_v1_0_11_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'H1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'H1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(16),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H00),
|
||||
.s_axi_awsize(3'H0),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'H0),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'H0),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(2'H0),
|
||||
.m_axi_buser(1024'H0),
|
||||
.m_axi_bvalid(1'H0),
|
||||
.m_axi_bready(),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s00tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK\
|
||||
0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [1 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [1 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
|
||||
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_transaction_regulator_v1_0_9_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_MEP_IDENTIFIER(2),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(2),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(16),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(2'H2),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awsize(3'H0),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1024'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1024'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'H0),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'H0),
|
||||
.m_axi_bid(2'H0),
|
||||
.m_axi_bresp(2'H0),
|
||||
.m_axi_buser(1024'H0),
|
||||
.m_axi_bvalid(1'H0),
|
||||
.m_axi_bready(),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_si_converter:1.0
|
||||
// IP Revision: 11
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_6f02_s00sic_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [1 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [1 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK\
|
||||
0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [1 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [1 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 2, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
|
||||
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_si_converter_v1_0_11_top #(
|
||||
.C_AXILITE_CONV(0),
|
||||
.C_LIMIT_WRITE_LENGTH(0),
|
||||
.C_LIMIT_READ_LENGTH(0),
|
||||
.C_WRITE_WATERMARK(0),
|
||||
.C_READ_WATERMARK(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(2),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_HAS_BURST(0),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEP_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_SEP_PROTOCOL_ARRAY(32'H00000001),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_WDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_MSC_RDATA_WIDTH_ARRAY(32'H00000020),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(2),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_S_WUSER_BITS_PER_BYTE(0),
|
||||
.C_S_RUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_WUSER_BITS_PER_BYTE(0),
|
||||
.C_MAX_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_NUM_READ_OUTSTANDING(16),
|
||||
.C_NUM_WRITE_OUTSTANDING(2),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(2'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awsize(3'H0),
|
||||
.s_axi_awburst(2'H1),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1024'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1024'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'H0),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'H0),
|
||||
.m_axi_bid(2'H0),
|
||||
.m_axi_bresp(2'H0),
|
||||
.m_axi_buser(1024'H0),
|
||||
.m_axi_bvalid(1'H0),
|
||||
.m_axi_bready(),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,165 @@
|
|||
NUM_SI 3
|
||||
NUM_MI 1
|
||||
NUM_CLKS 1
|
||||
S00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S00_AXI.CONFIG.NUM_READ_OUTSTANDING 16
|
||||
S00_AXI.CONFIG.DATA_WIDTH 32
|
||||
S00_AXI.CONFIG.DATAWIDTH 32
|
||||
S00_AXI.CONFIG.PROTOCOL AXI4
|
||||
S00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S00_AXI.CONFIG.ID_WIDTH 0
|
||||
S00_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S00_AXI.CONFIG.READ_WRITE_MODE READ_ONLY
|
||||
S00_AXI.CONFIG.HAS_BURST 0
|
||||
S00_AXI.CONFIG.HAS_LOCK 0
|
||||
S00_AXI.CONFIG.HAS_PROT 1
|
||||
S00_AXI.CONFIG.HAS_CACHE 1
|
||||
S00_AXI.CONFIG.HAS_QOS 0
|
||||
S00_AXI.CONFIG.HAS_REGION 0
|
||||
S00_AXI.CONFIG.HAS_WSTRB 0
|
||||
S00_AXI.CONFIG.HAS_BRESP 0
|
||||
S00_AXI.CONFIG.HAS_RRESP 1
|
||||
S00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 2
|
||||
S00_AXI.CONFIG.MAX_BURST_LENGTH 64
|
||||
S00_AXI.CONFIG.PHASE 0.000
|
||||
S00_AXI.CONFIG.CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0
|
||||
S00_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S00_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S00_AXI.CONFIG.INSERT_VIP 0
|
||||
S01_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S01_AXI.CONFIG.NUM_WRITE_OUTSTANDING 16
|
||||
S01_AXI.CONFIG.DATA_WIDTH 32
|
||||
S01_AXI.CONFIG.DATAWIDTH 32
|
||||
S01_AXI.CONFIG.PROTOCOL AXI4
|
||||
S01_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S01_AXI.CONFIG.ID_WIDTH 0
|
||||
S01_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S01_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S01_AXI.CONFIG.READ_WRITE_MODE WRITE_ONLY
|
||||
S01_AXI.CONFIG.HAS_BURST 0
|
||||
S01_AXI.CONFIG.HAS_LOCK 0
|
||||
S01_AXI.CONFIG.HAS_PROT 1
|
||||
S01_AXI.CONFIG.HAS_CACHE 1
|
||||
S01_AXI.CONFIG.HAS_QOS 0
|
||||
S01_AXI.CONFIG.HAS_REGION 0
|
||||
S01_AXI.CONFIG.HAS_WSTRB 1
|
||||
S01_AXI.CONFIG.HAS_BRESP 1
|
||||
S01_AXI.CONFIG.HAS_RRESP 0
|
||||
S01_AXI.CONFIG.NUM_READ_OUTSTANDING 2
|
||||
S01_AXI.CONFIG.MAX_BURST_LENGTH 64
|
||||
S01_AXI.CONFIG.PHASE 0.000
|
||||
S01_AXI.CONFIG.CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0
|
||||
S01_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S01_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S01_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S01_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S01_AXI.CONFIG.INSERT_VIP 0
|
||||
S02_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
S02_AXI.CONFIG.NUM_READ_OUTSTANDING 2
|
||||
S02_AXI.CONFIG.NUM_WRITE_OUTSTANDING 2
|
||||
S02_AXI.CONFIG.MAX_BURST_LENGTH 16
|
||||
S02_AXI.CONFIG.DATA_WIDTH 32
|
||||
S02_AXI.CONFIG.DATAWIDTH 32
|
||||
S02_AXI.CONFIG.PROTOCOL AXI4
|
||||
S02_AXI.CONFIG.FREQ_HZ 100000000
|
||||
S02_AXI.CONFIG.ID_WIDTH 0
|
||||
S02_AXI.CONFIG.ADDR_WIDTH 32
|
||||
S02_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.WUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.RUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.BUSER_WIDTH 0
|
||||
S02_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
S02_AXI.CONFIG.HAS_BURST 0
|
||||
S02_AXI.CONFIG.HAS_LOCK 0
|
||||
S02_AXI.CONFIG.HAS_PROT 1
|
||||
S02_AXI.CONFIG.HAS_CACHE 1
|
||||
S02_AXI.CONFIG.HAS_QOS 0
|
||||
S02_AXI.CONFIG.HAS_REGION 0
|
||||
S02_AXI.CONFIG.HAS_WSTRB 1
|
||||
S02_AXI.CONFIG.HAS_BRESP 1
|
||||
S02_AXI.CONFIG.HAS_RRESP 1
|
||||
S02_AXI.CONFIG.PHASE 0.000
|
||||
S02_AXI.CONFIG.CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0
|
||||
S02_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
S02_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
S02_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
S02_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
S02_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.CONFIG.NUM_WRITE_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.NUM_READ_OUTSTANDING 8
|
||||
M00_AXI.CONFIG.DATA_WIDTH 32
|
||||
M00_AXI.CONFIG.DATAWIDTH 32
|
||||
M00_AXI.CONFIG.PROTOCOL AXI3
|
||||
M00_AXI.CONFIG.FREQ_HZ 100000000
|
||||
M00_AXI.CONFIG.ID_WIDTH 6
|
||||
M00_AXI.CONFIG.ADDR_WIDTH 32
|
||||
M00_AXI.CONFIG.AWUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.ARUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.WUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.RUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.BUSER_WIDTH 0
|
||||
M00_AXI.CONFIG.READ_WRITE_MODE READ_WRITE
|
||||
M00_AXI.CONFIG.HAS_BURST 1
|
||||
M00_AXI.CONFIG.HAS_LOCK 1
|
||||
M00_AXI.CONFIG.HAS_PROT 1
|
||||
M00_AXI.CONFIG.HAS_CACHE 1
|
||||
M00_AXI.CONFIG.HAS_QOS 1
|
||||
M00_AXI.CONFIG.HAS_REGION 0
|
||||
M00_AXI.CONFIG.HAS_WSTRB 1
|
||||
M00_AXI.CONFIG.HAS_BRESP 1
|
||||
M00_AXI.CONFIG.HAS_RRESP 1
|
||||
M00_AXI.CONFIG.SUPPORTS_NARROW_BURST 0
|
||||
M00_AXI.CONFIG.MAX_BURST_LENGTH 16
|
||||
M00_AXI.CONFIG.PHASE 0.000
|
||||
M00_AXI.CONFIG.CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0
|
||||
M00_AXI.CONFIG.NUM_READ_THREADS 1
|
||||
M00_AXI.CONFIG.NUM_WRITE_THREADS 1
|
||||
M00_AXI.CONFIG.RUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.WUSER_BITS_PER_BYTE 0
|
||||
M00_AXI.CONFIG.INSERT_VIP 0
|
||||
M00_AXI.IS_CASCADED 0
|
||||
S00_AXI.IS_CASCADED 0
|
||||
S01_AXI.IS_CASCADED 0
|
||||
S02_AXI.IS_CASCADED 0
|
||||
S00_AXI.NUM_SEG 1
|
||||
S00_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S00_AXI.SEG000.SIZE 29
|
||||
S00_AXI.SEG000.SUPPORTS_READ 1
|
||||
S00_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S00_AXI.SEG000.SECURE_READ 0
|
||||
S00_AXI.SEG000.SECURE_WRITE 0
|
||||
S00_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S00_AXI.SEG000.PROTOCOL AXI3
|
||||
S00_AXI.SEG000.DATA_WIDTH 32
|
||||
S01_AXI.NUM_SEG 1
|
||||
S01_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S01_AXI.SEG000.SIZE 29
|
||||
S01_AXI.SEG000.SUPPORTS_READ 1
|
||||
S01_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S01_AXI.SEG000.SECURE_READ 0
|
||||
S01_AXI.SEG000.SECURE_WRITE 0
|
||||
S01_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S01_AXI.SEG000.PROTOCOL AXI3
|
||||
S01_AXI.SEG000.DATA_WIDTH 32
|
||||
S02_AXI.NUM_SEG 1
|
||||
S02_AXI.SEG000.BASE_ADDR 0x0000000000000000
|
||||
S02_AXI.SEG000.SIZE 29
|
||||
S02_AXI.SEG000.SUPPORTS_READ 1
|
||||
S02_AXI.SEG000.SUPPORTS_WRITE 1
|
||||
S02_AXI.SEG000.SECURE_READ 0
|
||||
S02_AXI.SEG000.SECURE_WRITE 0
|
||||
S02_AXI.SEG000.SEP_ROUTE 0b0000000000000000000000000000000000000000000000000000000000000000
|
||||
S02_AXI.SEG000.PROTOCOL AXI3
|
||||
S02_AXI.SEG000.DATA_WIDTH 32
|
||||
|
|
@ -0,0 +1,476 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:smartconnect:1.0
|
||||
// IP Revision: 19
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_axi_smc_1 (
|
||||
aclk,
|
||||
aresetn,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_rready,
|
||||
S01_AXI_awaddr,
|
||||
S01_AXI_awlen,
|
||||
S01_AXI_awsize,
|
||||
S01_AXI_awburst,
|
||||
S01_AXI_awlock,
|
||||
S01_AXI_awcache,
|
||||
S01_AXI_awprot,
|
||||
S01_AXI_awqos,
|
||||
S01_AXI_awvalid,
|
||||
S01_AXI_awready,
|
||||
S01_AXI_wdata,
|
||||
S01_AXI_wstrb,
|
||||
S01_AXI_wlast,
|
||||
S01_AXI_wvalid,
|
||||
S01_AXI_wready,
|
||||
S01_AXI_bresp,
|
||||
S01_AXI_bvalid,
|
||||
S01_AXI_bready,
|
||||
S02_AXI_awaddr,
|
||||
S02_AXI_awlen,
|
||||
S02_AXI_awsize,
|
||||
S02_AXI_awburst,
|
||||
S02_AXI_awlock,
|
||||
S02_AXI_awcache,
|
||||
S02_AXI_awprot,
|
||||
S02_AXI_awqos,
|
||||
S02_AXI_awvalid,
|
||||
S02_AXI_awready,
|
||||
S02_AXI_wdata,
|
||||
S02_AXI_wstrb,
|
||||
S02_AXI_wlast,
|
||||
S02_AXI_wvalid,
|
||||
S02_AXI_wready,
|
||||
S02_AXI_bresp,
|
||||
S02_AXI_bvalid,
|
||||
S02_AXI_bready,
|
||||
S02_AXI_araddr,
|
||||
S02_AXI_arlen,
|
||||
S02_AXI_arsize,
|
||||
S02_AXI_arburst,
|
||||
S02_AXI_arlock,
|
||||
S02_AXI_arcache,
|
||||
S02_AXI_arprot,
|
||||
S02_AXI_arqos,
|
||||
S02_AXI_arvalid,
|
||||
S02_AXI_arready,
|
||||
S02_AXI_rdata,
|
||||
S02_AXI_rresp,
|
||||
S02_AXI_rlast,
|
||||
S02_AXI_rvalid,
|
||||
S02_AXI_rready,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awlen,
|
||||
M00_AXI_awsize,
|
||||
M00_AXI_awburst,
|
||||
M00_AXI_awlock,
|
||||
M00_AXI_awcache,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awqos,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wlast,
|
||||
M00_AXI_wvalid,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_araddr,
|
||||
M00_AXI_arlen,
|
||||
M00_AXI_arsize,
|
||||
M00_AXI_arburst,
|
||||
M00_AXI_arlock,
|
||||
M00_AXI_arcache,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arqos,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rlast,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:S00_AXI:S01_AXI:S02_AXI, INSERT_VIP 0, ASSOCIATED_CLKEN m_sc_aclken" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [31 : 0] S00_AXI_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
|
||||
input wire [7 : 0] S00_AXI_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
|
||||
input wire [2 : 0] S00_AXI_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
|
||||
input wire [1 : 0] S00_AXI_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
|
||||
input wire [0 : 0] S00_AXI_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
|
||||
input wire [3 : 0] S00_AXI_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] S00_AXI_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
|
||||
input wire [3 : 0] S00_AXI_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire S00_AXI_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire S00_AXI_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] S00_AXI_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] S00_AXI_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
|
||||
output wire S00_AXI_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire S00_AXI_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire S00_AXI_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR" *)
|
||||
input wire [31 : 0] S01_AXI_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN" *)
|
||||
input wire [7 : 0] S01_AXI_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE" *)
|
||||
input wire [2 : 0] S01_AXI_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST" *)
|
||||
input wire [1 : 0] S01_AXI_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK" *)
|
||||
input wire [0 : 0] S01_AXI_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE" *)
|
||||
input wire [3 : 0] S01_AXI_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT" *)
|
||||
input wire [2 : 0] S01_AXI_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS" *)
|
||||
input wire [3 : 0] S01_AXI_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID" *)
|
||||
input wire S01_AXI_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY" *)
|
||||
output wire S01_AXI_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI WDATA" *)
|
||||
input wire [31 : 0] S01_AXI_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB" *)
|
||||
input wire [3 : 0] S01_AXI_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI WLAST" *)
|
||||
input wire S01_AXI_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI WVALID" *)
|
||||
input wire S01_AXI_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI WREADY" *)
|
||||
output wire S01_AXI_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI BRESP" *)
|
||||
output wire [1 : 0] S01_AXI_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI BVALID" *)
|
||||
output wire S01_AXI_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S01_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S01_AXI BREADY" *)
|
||||
input wire S01_AXI_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWADDR" *)
|
||||
input wire [31 : 0] S02_AXI_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWLEN" *)
|
||||
input wire [7 : 0] S02_AXI_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWSIZE" *)
|
||||
input wire [2 : 0] S02_AXI_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWBURST" *)
|
||||
input wire [1 : 0] S02_AXI_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK" *)
|
||||
input wire [0 : 0] S02_AXI_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE" *)
|
||||
input wire [3 : 0] S02_AXI_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWPROT" *)
|
||||
input wire [2 : 0] S02_AXI_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWQOS" *)
|
||||
input wire [3 : 0] S02_AXI_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWVALID" *)
|
||||
input wire S02_AXI_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI AWREADY" *)
|
||||
output wire S02_AXI_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI WDATA" *)
|
||||
input wire [31 : 0] S02_AXI_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI WSTRB" *)
|
||||
input wire [3 : 0] S02_AXI_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI WLAST" *)
|
||||
input wire S02_AXI_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI WVALID" *)
|
||||
input wire S02_AXI_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI WREADY" *)
|
||||
output wire S02_AXI_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI BRESP" *)
|
||||
output wire [1 : 0] S02_AXI_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI BVALID" *)
|
||||
output wire S02_AXI_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI BREADY" *)
|
||||
input wire S02_AXI_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARADDR" *)
|
||||
input wire [31 : 0] S02_AXI_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARLEN" *)
|
||||
input wire [7 : 0] S02_AXI_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARSIZE" *)
|
||||
input wire [2 : 0] S02_AXI_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARBURST" *)
|
||||
input wire [1 : 0] S02_AXI_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK" *)
|
||||
input wire [0 : 0] S02_AXI_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE" *)
|
||||
input wire [3 : 0] S02_AXI_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARPROT" *)
|
||||
input wire [2 : 0] S02_AXI_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARQOS" *)
|
||||
input wire [3 : 0] S02_AXI_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARVALID" *)
|
||||
input wire S02_AXI_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI ARREADY" *)
|
||||
output wire S02_AXI_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI RDATA" *)
|
||||
output wire [31 : 0] S02_AXI_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI RRESP" *)
|
||||
output wire [1 : 0] S02_AXI_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI RLAST" *)
|
||||
output wire S02_AXI_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI RVALID" *)
|
||||
output wire S02_AXI_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S02_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S02_AXI RREADY" *)
|
||||
input wire S02_AXI_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
|
||||
output wire [31 : 0] M00_AXI_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
|
||||
output wire [3 : 0] M00_AXI_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
|
||||
output wire [2 : 0] M00_AXI_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
|
||||
output wire [1 : 0] M00_AXI_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
|
||||
output wire [1 : 0] M00_AXI_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
|
||||
output wire [3 : 0] M00_AXI_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
|
||||
output wire [2 : 0] M00_AXI_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
|
||||
output wire [3 : 0] M00_AXI_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
|
||||
output wire M00_AXI_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
|
||||
input wire M00_AXI_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
|
||||
output wire [31 : 0] M00_AXI_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
|
||||
output wire [3 : 0] M00_AXI_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
|
||||
output wire M00_AXI_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
|
||||
output wire M00_AXI_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
|
||||
input wire M00_AXI_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
|
||||
input wire [1 : 0] M00_AXI_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
|
||||
input wire M00_AXI_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
|
||||
output wire M00_AXI_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
|
||||
output wire [31 : 0] M00_AXI_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
|
||||
output wire [3 : 0] M00_AXI_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
|
||||
output wire [2 : 0] M00_AXI_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
|
||||
output wire [1 : 0] M00_AXI_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
|
||||
output wire [1 : 0] M00_AXI_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
|
||||
output wire [3 : 0] M00_AXI_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
|
||||
output wire [2 : 0] M00_AXI_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
|
||||
output wire [3 : 0] M00_AXI_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
|
||||
output wire M00_AXI_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
|
||||
input wire M00_AXI_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
|
||||
input wire [31 : 0] M00_AXI_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
|
||||
input wire [1 : 0] M00_AXI_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
|
||||
input wire M00_AXI_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
|
||||
input wire M00_AXI_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\
|
||||
DS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
|
||||
output wire M00_AXI_rready;
|
||||
|
||||
bd_6f02 inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.S00_AXI_araddr(S00_AXI_araddr),
|
||||
.S00_AXI_arlen(S00_AXI_arlen),
|
||||
.S00_AXI_arsize(S00_AXI_arsize),
|
||||
.S00_AXI_arburst(S00_AXI_arburst),
|
||||
.S00_AXI_arlock(S00_AXI_arlock),
|
||||
.S00_AXI_arcache(S00_AXI_arcache),
|
||||
.S00_AXI_arprot(S00_AXI_arprot),
|
||||
.S00_AXI_arqos(S00_AXI_arqos),
|
||||
.S00_AXI_arvalid(S00_AXI_arvalid),
|
||||
.S00_AXI_arready(S00_AXI_arready),
|
||||
.S00_AXI_rdata(S00_AXI_rdata),
|
||||
.S00_AXI_rresp(S00_AXI_rresp),
|
||||
.S00_AXI_rlast(S00_AXI_rlast),
|
||||
.S00_AXI_rvalid(S00_AXI_rvalid),
|
||||
.S00_AXI_rready(S00_AXI_rready),
|
||||
.S01_AXI_awaddr(S01_AXI_awaddr),
|
||||
.S01_AXI_awlen(S01_AXI_awlen),
|
||||
.S01_AXI_awsize(S01_AXI_awsize),
|
||||
.S01_AXI_awburst(S01_AXI_awburst),
|
||||
.S01_AXI_awlock(S01_AXI_awlock),
|
||||
.S01_AXI_awcache(S01_AXI_awcache),
|
||||
.S01_AXI_awprot(S01_AXI_awprot),
|
||||
.S01_AXI_awqos(S01_AXI_awqos),
|
||||
.S01_AXI_awvalid(S01_AXI_awvalid),
|
||||
.S01_AXI_awready(S01_AXI_awready),
|
||||
.S01_AXI_wdata(S01_AXI_wdata),
|
||||
.S01_AXI_wstrb(S01_AXI_wstrb),
|
||||
.S01_AXI_wlast(S01_AXI_wlast),
|
||||
.S01_AXI_wvalid(S01_AXI_wvalid),
|
||||
.S01_AXI_wready(S01_AXI_wready),
|
||||
.S01_AXI_bresp(S01_AXI_bresp),
|
||||
.S01_AXI_bvalid(S01_AXI_bvalid),
|
||||
.S01_AXI_bready(S01_AXI_bready),
|
||||
.S02_AXI_awaddr(S02_AXI_awaddr),
|
||||
.S02_AXI_awlen(S02_AXI_awlen),
|
||||
.S02_AXI_awsize(S02_AXI_awsize),
|
||||
.S02_AXI_awburst(S02_AXI_awburst),
|
||||
.S02_AXI_awlock(S02_AXI_awlock),
|
||||
.S02_AXI_awcache(S02_AXI_awcache),
|
||||
.S02_AXI_awprot(S02_AXI_awprot),
|
||||
.S02_AXI_awqos(S02_AXI_awqos),
|
||||
.S02_AXI_awvalid(S02_AXI_awvalid),
|
||||
.S02_AXI_awready(S02_AXI_awready),
|
||||
.S02_AXI_wdata(S02_AXI_wdata),
|
||||
.S02_AXI_wstrb(S02_AXI_wstrb),
|
||||
.S02_AXI_wlast(S02_AXI_wlast),
|
||||
.S02_AXI_wvalid(S02_AXI_wvalid),
|
||||
.S02_AXI_wready(S02_AXI_wready),
|
||||
.S02_AXI_bresp(S02_AXI_bresp),
|
||||
.S02_AXI_bvalid(S02_AXI_bvalid),
|
||||
.S02_AXI_bready(S02_AXI_bready),
|
||||
.S02_AXI_araddr(S02_AXI_araddr),
|
||||
.S02_AXI_arlen(S02_AXI_arlen),
|
||||
.S02_AXI_arsize(S02_AXI_arsize),
|
||||
.S02_AXI_arburst(S02_AXI_arburst),
|
||||
.S02_AXI_arlock(S02_AXI_arlock),
|
||||
.S02_AXI_arcache(S02_AXI_arcache),
|
||||
.S02_AXI_arprot(S02_AXI_arprot),
|
||||
.S02_AXI_arqos(S02_AXI_arqos),
|
||||
.S02_AXI_arvalid(S02_AXI_arvalid),
|
||||
.S02_AXI_arready(S02_AXI_arready),
|
||||
.S02_AXI_rdata(S02_AXI_rdata),
|
||||
.S02_AXI_rresp(S02_AXI_rresp),
|
||||
.S02_AXI_rlast(S02_AXI_rlast),
|
||||
.S02_AXI_rvalid(S02_AXI_rvalid),
|
||||
.S02_AXI_rready(S02_AXI_rready),
|
||||
.M00_AXI_awaddr(M00_AXI_awaddr),
|
||||
.M00_AXI_awlen(M00_AXI_awlen),
|
||||
.M00_AXI_awsize(M00_AXI_awsize),
|
||||
.M00_AXI_awburst(M00_AXI_awburst),
|
||||
.M00_AXI_awlock(M00_AXI_awlock),
|
||||
.M00_AXI_awcache(M00_AXI_awcache),
|
||||
.M00_AXI_awprot(M00_AXI_awprot),
|
||||
.M00_AXI_awqos(M00_AXI_awqos),
|
||||
.M00_AXI_awvalid(M00_AXI_awvalid),
|
||||
.M00_AXI_awready(M00_AXI_awready),
|
||||
.M00_AXI_wdata(M00_AXI_wdata),
|
||||
.M00_AXI_wstrb(M00_AXI_wstrb),
|
||||
.M00_AXI_wlast(M00_AXI_wlast),
|
||||
.M00_AXI_wvalid(M00_AXI_wvalid),
|
||||
.M00_AXI_wready(M00_AXI_wready),
|
||||
.M00_AXI_bresp(M00_AXI_bresp),
|
||||
.M00_AXI_bvalid(M00_AXI_bvalid),
|
||||
.M00_AXI_bready(M00_AXI_bready),
|
||||
.M00_AXI_araddr(M00_AXI_araddr),
|
||||
.M00_AXI_arlen(M00_AXI_arlen),
|
||||
.M00_AXI_arsize(M00_AXI_arsize),
|
||||
.M00_AXI_arburst(M00_AXI_arburst),
|
||||
.M00_AXI_arlock(M00_AXI_arlock),
|
||||
.M00_AXI_arcache(M00_AXI_arcache),
|
||||
.M00_AXI_arprot(M00_AXI_arprot),
|
||||
.M00_AXI_arqos(M00_AXI_arqos),
|
||||
.M00_AXI_arvalid(M00_AXI_arvalid),
|
||||
.M00_AXI_arready(M00_AXI_arready),
|
||||
.M00_AXI_rdata(M00_AXI_rdata),
|
||||
.M00_AXI_rresp(M00_AXI_rresp),
|
||||
.M00_AXI_rlast(M00_AXI_rlast),
|
||||
.M00_AXI_rvalid(M00_AXI_rvalid),
|
||||
.M00_AXI_rready(M00_AXI_rready)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
|
||||
// file: design_1_clk_wiz_0_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1___5.00000______0.000______50.0______631.442____346.848
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v6_0_11_0_0,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module design_1_clk_wiz_0_0
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input resetn,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
design_1_clk_wiz_0_0_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.resetn(resetn),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
|
||||
// file: design_1_clk_wiz_0_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1___5.00000______0.000______50.0______631.442____346.848
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module design_1_clk_wiz_0_0_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input resetn,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_design_1_clk_wiz_0_0;
|
||||
wire clk_in2_design_1_clk_wiz_0_0;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_design_1_clk_wiz_0_0),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_design_1_clk_wiz_0_0;
|
||||
wire clk_out2_design_1_clk_wiz_0_0;
|
||||
wire clk_out3_design_1_clk_wiz_0_0;
|
||||
wire clk_out4_design_1_clk_wiz_0_0;
|
||||
wire clk_out5_design_1_clk_wiz_0_0;
|
||||
wire clk_out6_design_1_clk_wiz_0_0;
|
||||
wire clk_out7_design_1_clk_wiz_0_0;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_buf_design_1_clk_wiz_0_0;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
wire reset_high;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT_F (32.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (128.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (reset_high));
|
||||
assign reset_high = ~resetn;
|
||||
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.I (clkfbout_design_1_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_design_1_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Wed Dec 7 19:49:18 2022
|
||||
// Host : home-pc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// d:/project/hdl/axi_dma/axi_dma.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.v
|
||||
// Design : design_1_clk_wiz_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_clk_wiz_0_0
|
||||
(clk_out1,
|
||||
resetn,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input resetn;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire resetn;
|
||||
|
||||
design_1_clk_wiz_0_0_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.resetn(resetn));
|
||||
endmodule
|
||||
|
||||
module design_1_clk_wiz_0_0_clk_wiz
|
||||
(clk_out1,
|
||||
resetn,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input resetn;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_design_1_clk_wiz_0_0;
|
||||
wire clk_out1;
|
||||
wire clk_out1_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_buf_design_1_clk_wiz_0_0;
|
||||
wire clkfbout_design_1_clk_wiz_0_0;
|
||||
wire reset_high;
|
||||
wire resetn;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_design_1_clk_wiz_0_0),
|
||||
.O(clkfbout_buf_design_1_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.CCIO_EN("TRUE"),
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_design_1_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_design_1_clk_wiz_0_0),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(32.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(10.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(128.000000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(5),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_0),
|
||||
.CLKFBOUT(clkfbout_design_1_clk_wiz_0_0),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_design_1_clk_wiz_0_0),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_design_1_clk_wiz_0_0),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset_high));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
mmcm_adv_inst_i_1
|
||||
(.I0(resetn),
|
||||
.O(reset_high));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Wed Dec 7 19:49:18 2022
|
||||
-- Host : home-pc running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- d:/project/hdl/axi_dma/axi_dma.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_clk_wiz_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_clk_wiz_0_0_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
end design_1_clk_wiz_0_0_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of design_1_clk_wiz_0_0_clk_wiz is
|
||||
signal clk_in1_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clk_out1_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_buf_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_design_1_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal reset_high : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_design_1_clk_wiz_0_0,
|
||||
O => clkfbout_buf_design_1_clk_wiz_0_0
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
CCIO_EN => "TRUE",
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_design_1_clk_wiz_0_0
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_design_1_clk_wiz_0_0,
|
||||
O => clk_out1
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 32.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 10.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 128.000000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 1,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 1,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 5,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_0,
|
||||
CLKFBOUT => clkfbout_design_1_clk_wiz_0_0,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_design_1_clk_wiz_0_0,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_design_1_clk_wiz_0_0,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => reset_high
|
||||
);
|
||||
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => resetn,
|
||||
O => reset_high
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_clk_wiz_0_0 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_clk_wiz_0_0 : entity is true;
|
||||
end design_1_clk_wiz_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_clk_wiz_0_0 is
|
||||
begin
|
||||
inst: entity work.design_1_clk_wiz_0_0_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
resetn => resetn
|
||||
);
|
||||
end STRUCTURE;
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,78 @@
|
|||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module design_1_ila_0_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [31 : 0] probe1;
|
||||
input [3 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [3 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
input [0 : 0] probe8;
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,68 @@
|
|||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module design_1_ila_1_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,74 @@
|
|||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module design_1_ila_2_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [1 : 0] probe0;
|
||||
input [7 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [7 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [7 : 0] probe5;
|
||||
input [1 : 0] probe6;
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,62 @@
|
|||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module design_1_ila_3_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [7 : 0] probe0;
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,704 @@
|
|||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module design_1_processing_system7_0_0 (
|
||||
ENET0_GMII_TX_EN,
|
||||
ENET0_GMII_TX_ER,
|
||||
ENET0_MDIO_MDC,
|
||||
ENET0_MDIO_O,
|
||||
ENET0_MDIO_T,
|
||||
ENET0_GMII_TXD,
|
||||
ENET0_GMII_COL,
|
||||
ENET0_GMII_CRS,
|
||||
ENET0_GMII_RX_CLK,
|
||||
ENET0_GMII_RX_DV,
|
||||
ENET0_GMII_RX_ER,
|
||||
ENET0_GMII_TX_CLK,
|
||||
ENET0_MDIO_I,
|
||||
ENET0_EXT_INTIN,
|
||||
ENET0_GMII_RXD,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
S_AXI_HP0_ARREADY,
|
||||
S_AXI_HP0_AWREADY,
|
||||
S_AXI_HP0_BVALID,
|
||||
S_AXI_HP0_RLAST,
|
||||
S_AXI_HP0_RVALID,
|
||||
S_AXI_HP0_WREADY,
|
||||
S_AXI_HP0_BRESP,
|
||||
S_AXI_HP0_RRESP,
|
||||
S_AXI_HP0_BID,
|
||||
S_AXI_HP0_RID,
|
||||
S_AXI_HP0_RDATA,
|
||||
S_AXI_HP0_RCOUNT,
|
||||
S_AXI_HP0_WCOUNT,
|
||||
S_AXI_HP0_RACOUNT,
|
||||
S_AXI_HP0_WACOUNT,
|
||||
S_AXI_HP0_ACLK,
|
||||
S_AXI_HP0_ARVALID,
|
||||
S_AXI_HP0_AWVALID,
|
||||
S_AXI_HP0_BREADY,
|
||||
S_AXI_HP0_RDISSUECAP1_EN,
|
||||
S_AXI_HP0_RREADY,
|
||||
S_AXI_HP0_WLAST,
|
||||
S_AXI_HP0_WRISSUECAP1_EN,
|
||||
S_AXI_HP0_WVALID,
|
||||
S_AXI_HP0_ARBURST,
|
||||
S_AXI_HP0_ARLOCK,
|
||||
S_AXI_HP0_ARSIZE,
|
||||
S_AXI_HP0_AWBURST,
|
||||
S_AXI_HP0_AWLOCK,
|
||||
S_AXI_HP0_AWSIZE,
|
||||
S_AXI_HP0_ARPROT,
|
||||
S_AXI_HP0_AWPROT,
|
||||
S_AXI_HP0_ARADDR,
|
||||
S_AXI_HP0_AWADDR,
|
||||
S_AXI_HP0_ARCACHE,
|
||||
S_AXI_HP0_ARLEN,
|
||||
S_AXI_HP0_ARQOS,
|
||||
S_AXI_HP0_AWCACHE,
|
||||
S_AXI_HP0_AWLEN,
|
||||
S_AXI_HP0_AWQOS,
|
||||
S_AXI_HP0_ARID,
|
||||
S_AXI_HP0_AWID,
|
||||
S_AXI_HP0_WID,
|
||||
S_AXI_HP0_WDATA,
|
||||
S_AXI_HP0_WSTRB,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_RESET0_N,
|
||||
FCLK_RESET1_N,
|
||||
FCLK_RESET2_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
output [0 : 0] ENET0_GMII_TX_EN;
|
||||
output [0 : 0] ENET0_GMII_TX_ER;
|
||||
output ENET0_MDIO_MDC;
|
||||
output ENET0_MDIO_O;
|
||||
output ENET0_MDIO_T;
|
||||
output [7 : 0] ENET0_GMII_TXD;
|
||||
input ENET0_GMII_COL;
|
||||
input ENET0_GMII_CRS;
|
||||
input ENET0_GMII_RX_CLK;
|
||||
input ENET0_GMII_RX_DV;
|
||||
input ENET0_GMII_RX_ER;
|
||||
input ENET0_GMII_TX_CLK;
|
||||
input ENET0_MDIO_I;
|
||||
input ENET0_EXT_INTIN;
|
||||
input [7 : 0] ENET0_GMII_RXD;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output S_AXI_HP0_ARREADY;
|
||||
output S_AXI_HP0_AWREADY;
|
||||
output S_AXI_HP0_BVALID;
|
||||
output S_AXI_HP0_RLAST;
|
||||
output S_AXI_HP0_RVALID;
|
||||
output S_AXI_HP0_WREADY;
|
||||
output [1 : 0] S_AXI_HP0_BRESP;
|
||||
output [1 : 0] S_AXI_HP0_RRESP;
|
||||
output [5 : 0] S_AXI_HP0_BID;
|
||||
output [5 : 0] S_AXI_HP0_RID;
|
||||
output [31 : 0] S_AXI_HP0_RDATA;
|
||||
output [7 : 0] S_AXI_HP0_RCOUNT;
|
||||
output [7 : 0] S_AXI_HP0_WCOUNT;
|
||||
output [2 : 0] S_AXI_HP0_RACOUNT;
|
||||
output [5 : 0] S_AXI_HP0_WACOUNT;
|
||||
input S_AXI_HP0_ACLK;
|
||||
input S_AXI_HP0_ARVALID;
|
||||
input S_AXI_HP0_AWVALID;
|
||||
input S_AXI_HP0_BREADY;
|
||||
input S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input S_AXI_HP0_RREADY;
|
||||
input S_AXI_HP0_WLAST;
|
||||
input S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input S_AXI_HP0_WVALID;
|
||||
input [1 : 0] S_AXI_HP0_ARBURST;
|
||||
input [1 : 0] S_AXI_HP0_ARLOCK;
|
||||
input [2 : 0] S_AXI_HP0_ARSIZE;
|
||||
input [1 : 0] S_AXI_HP0_AWBURST;
|
||||
input [1 : 0] S_AXI_HP0_AWLOCK;
|
||||
input [2 : 0] S_AXI_HP0_AWSIZE;
|
||||
input [2 : 0] S_AXI_HP0_ARPROT;
|
||||
input [2 : 0] S_AXI_HP0_AWPROT;
|
||||
input [31 : 0] S_AXI_HP0_ARADDR;
|
||||
input [31 : 0] S_AXI_HP0_AWADDR;
|
||||
input [3 : 0] S_AXI_HP0_ARCACHE;
|
||||
input [3 : 0] S_AXI_HP0_ARLEN;
|
||||
input [3 : 0] S_AXI_HP0_ARQOS;
|
||||
input [3 : 0] S_AXI_HP0_AWCACHE;
|
||||
input [3 : 0] S_AXI_HP0_AWLEN;
|
||||
input [3 : 0] S_AXI_HP0_AWQOS;
|
||||
input [5 : 0] S_AXI_HP0_ARID;
|
||||
input [5 : 0] S_AXI_HP0_AWID;
|
||||
input [5 : 0] S_AXI_HP0_WID;
|
||||
input [31 : 0] S_AXI_HP0_WDATA;
|
||||
input [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input [1 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_RESET0_N;
|
||||
output FCLK_RESET1_N;
|
||||
output FCLK_RESET2_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_15 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(1),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(32),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(10.0),
|
||||
.C_FCLK_CLK2_FREQ(10.0),
|
||||
.C_FCLK_CLK3_FREQ(10.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
|
||||
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
|
||||
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
|
||||
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
|
||||
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
|
||||
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
|
||||
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
|
||||
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
|
||||
.S_AXI_HP0_BID(S_AXI_HP0_BID),
|
||||
.S_AXI_HP0_RID(S_AXI_HP0_RID),
|
||||
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
|
||||
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
|
||||
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
|
||||
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
|
||||
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
|
||||
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
|
||||
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
|
||||
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
|
||||
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
|
||||
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
|
||||
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
|
||||
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
|
||||
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
|
||||
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
|
||||
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
|
||||
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
|
||||
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
|
||||
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
|
||||
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
|
||||
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
|
||||
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
|
||||
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
|
||||
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
|
||||
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
|
||||
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
|
||||
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
|
||||
.S_AXI_HP0_WID(S_AXI_HP0_WID),
|
||||
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
|
||||
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(),
|
||||
|
||||
.FCLK_CLK2(),
|
||||
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(FCLK_RESET1_N),
|
||||
.FCLK_RESET2_N(FCLK_RESET2_N),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,979 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun Nov 27 11:14:50 2022
|
||||
// Host : home-pc running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top design_1_rst_ps7_0_100M_0 -prefix
|
||||
// design_1_rst_ps7_0_100M_0_ design_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2022.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
design_1_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
module design_1_rst_ps7_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
module design_1_rst_ps7_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,147 @@
|
|||
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY design_1_rst_ps7_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0;
|
||||
|
||||
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0_arch;
|
||||
|
|
@ -0,0 +1,326 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconcat_0_0 (
|
||||
In0,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [3 : 0] In0;
|
||||
output wire [3 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(4),
|
||||
.IN1_WIDTH(4),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(4),
|
||||
.NUM_PORTS(1)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(4'B0),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconcat_1_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [3 : 0] In0;
|
||||
input wire [3 : 0] In1;
|
||||
output wire [7 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(4),
|
||||
.IN1_WIDTH(4),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(8),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconstant_0_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [3 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(4),
|
||||
.CONST_VAL(4'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
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Reference in New Issue