66 lines
2.5 KiB
Coq
66 lines
2.5 KiB
Coq
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
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/* Module Version: 5.8 */
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/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n FIFo -lang verilog -synth lse -bb -arch xo3c00f -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 10 -pf 1000 */
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/* Thu Jan 16 00:09:17 2020 */
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`timescale 1 ns / 1 ps
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module FIFo (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q,
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Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
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input wire [7:0] Data;
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input wire WrClock;
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input wire RdClock;
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input wire WrEn;
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input wire RdEn;
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input wire Reset;
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input wire RPReset;
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output wire [7:0] Q;
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output wire Empty;
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output wire Full;
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output wire AlmostEmpty;
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output wire AlmostFull;
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wire scuba_vhi;
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wire Empty_int;
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wire Full_int;
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wire scuba_vlo;
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VHI scuba_vhi_inst (.Z(scuba_vhi));
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam FIFo_0_0.FULLPOINTER1 = "0b01111111111000" ;
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defparam FIFo_0_0.FULLPOINTER = "0b10000000000000" ;
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defparam FIFo_0_0.AFPOINTER1 = "0b01111100111000" ;
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defparam FIFo_0_0.AFPOINTER = "0b01111101000000" ;
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defparam FIFo_0_0.AEPOINTER1 = "0b00000001011000" ;
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defparam FIFo_0_0.AEPOINTER = "0b00000001010000" ;
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defparam FIFo_0_0.ASYNC_RESET_RELEASE = "SYNC" ;
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defparam FIFo_0_0.GSR = "DISABLED" ;
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defparam FIFo_0_0.RESETMODE = "ASYNC" ;
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defparam FIFo_0_0.REGMODE = "NOREG" ;
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defparam FIFo_0_0.CSDECODE_R = "0b11" ;
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defparam FIFo_0_0.CSDECODE_W = "0b11" ;
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defparam FIFo_0_0.DATA_WIDTH_R = 9 ;
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defparam FIFo_0_0.DATA_WIDTH_W = 9 ;
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FIFO8KB FIFo_0_0 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), .DI3(Data[3]),
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.DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), .DI7(Data[7]), .DI8(scuba_vlo),
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.DI9(scuba_vlo), .DI10(scuba_vlo), .DI11(scuba_vlo), .DI12(scuba_vlo),
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.DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), .DI16(scuba_vlo),
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.DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), .CSR0(scuba_vhi),
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.CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), .WE(WrEn),
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.RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), .RST(Reset),
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.RPRST(RPReset), .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]),
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.DO4(Q[4]), .DO5(Q[5]), .DO6(Q[6]), .DO7(Q[7]), .DO8(), .DO9(),
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.DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), .DO17(),
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.EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));
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assign Empty = Empty_int;
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assign Full = Full_int;
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// exemplar begin
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// exemplar end
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endmodule
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