241 lines
11 KiB
Coq
241 lines
11 KiB
Coq
|
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
|
||
|
|
/* Module Version: 2.8 */
|
||
|
|
/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n ROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -type rom -addr_width 10 -num_rows 768 -data_width 8 -outdata REGISTERED -memfile c:/users/gaurav/documents/fpga/lattice/counter/rom.mem -memformat orca */
|
||
|
|
/* Tue Jan 14 20:17:42 2020 */
|
||
|
|
|
||
|
|
|
||
|
|
`timescale 1 ns / 1 ps
|
||
|
|
module ROM (Address, OutClock, OutClockEn, Reset, Q)/* synthesis NGD_DRC_MASK=1 */;
|
||
|
|
input wire [9:0] Address;
|
||
|
|
input wire OutClock;
|
||
|
|
input wire OutClockEn;
|
||
|
|
input wire Reset;
|
||
|
|
output wire [7:0] Q;
|
||
|
|
|
||
|
|
wire qdataout7_ffin;
|
||
|
|
wire mdL0_0_2;
|
||
|
|
wire mdL0_0_1;
|
||
|
|
wire mdL0_0_0;
|
||
|
|
wire qdataout6_ffin;
|
||
|
|
wire mdL0_1_2;
|
||
|
|
wire mdL0_1_1;
|
||
|
|
wire mdL0_1_0;
|
||
|
|
wire qdataout5_ffin;
|
||
|
|
wire mdL0_2_2;
|
||
|
|
wire mdL0_2_1;
|
||
|
|
wire mdL0_2_0;
|
||
|
|
wire qdataout4_ffin;
|
||
|
|
wire mdL0_3_2;
|
||
|
|
wire mdL0_3_1;
|
||
|
|
wire mdL0_3_0;
|
||
|
|
wire qdataout3_ffin;
|
||
|
|
wire mdL0_4_2;
|
||
|
|
wire mdL0_4_1;
|
||
|
|
wire mdL0_4_0;
|
||
|
|
wire qdataout2_ffin;
|
||
|
|
wire mdL0_5_2;
|
||
|
|
wire mdL0_5_1;
|
||
|
|
wire mdL0_5_0;
|
||
|
|
wire qdataout1_ffin;
|
||
|
|
wire mdL0_6_2;
|
||
|
|
wire mdL0_6_1;
|
||
|
|
wire mdL0_6_0;
|
||
|
|
wire qdataout0_ffin;
|
||
|
|
wire scuba_vlo;
|
||
|
|
wire mdL0_7_2;
|
||
|
|
wire mdL0_7_1;
|
||
|
|
wire mdL0_7_0;
|
||
|
|
|
||
|
|
FD1P3DX FF_7 (.D(qdataout7_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[7]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_6 (.D(qdataout6_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[6]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_5 (.D(qdataout5_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[5]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_4 (.D(qdataout4_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[4]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_3 (.D(qdataout3_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[3]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_2 (.D(qdataout2_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[2]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_1 (.D(qdataout1_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[1]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
FD1P3DX FF_0 (.D(qdataout0_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
|
||
|
|
.Q(Q[0]))
|
||
|
|
/* synthesis GSR="ENABLED" */;
|
||
|
|
|
||
|
|
defparam mem_0_7.initval = 256'hFFFFFFF8A228E28E28840000000020080A82A0828000002A2402090080402000 ;
|
||
|
|
ROM256X1A mem_0_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_0_0));
|
||
|
|
|
||
|
|
defparam mem_0_6.initval = 256'hFFFFFFF88220E20E208000011000000008822080800000220010000400000000 ;
|
||
|
|
ROM256X1A mem_0_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_1_0));
|
||
|
|
|
||
|
|
defparam mem_0_5.initval = 256'hFFFFFFFCE338F38F38D400008AA0A0A84613A46A0000013A541A050281422000 ;
|
||
|
|
ROM256X1A mem_0_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_2_0));
|
||
|
|
|
||
|
|
defparam mem_0_4.initval = 256'hFFFFFFFC6018718618040001DCCC62084E9180C2800000181C3E170780C0E000 ;
|
||
|
|
ROM256X1A mem_0_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_3_0));
|
||
|
|
|
||
|
|
defparam mem_0_3.initval = 256'hFFFFFFFE61987987981400008A02A0284619844A20000198642A010285402000 ;
|
||
|
|
ROM256X1A mem_0_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_4_0));
|
||
|
|
|
||
|
|
defparam mem_0_2.initval = 256'hFFFFFFFC0300F00F00D8400154E642B0E0300E2C00000100987426150C864201 ;
|
||
|
|
ROM256X1A mem_0_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_5_0));
|
||
|
|
|
||
|
|
defparam mem_0_1.initval = 256'hFFFFFFFA0280E80E80800002A8820000B1280B0120000080D038140A04000000 ;
|
||
|
|
ROM256X1A mem_0_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_6_0));
|
||
|
|
|
||
|
|
defparam mem_0_0.initval = 256'hFFFFFFFBC4F16F16F1484001566EC2902C0F42E4000000F4087422150D86C201 ;
|
||
|
|
ROM256X1A mem_0_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_7_0));
|
||
|
|
|
||
|
|
defparam mem_1_7.initval = 256'hAAAB55555555555555555555552AAAAAAAAAAAAAAD5555555FFFFFFFFFFFFFFF ;
|
||
|
|
ROM256X1A mem_1_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_0_1));
|
||
|
|
|
||
|
|
defparam mem_1_6.initval = 256'hFFFF55555555555555555555552AAAAAABFFFFFFF8000000000000007FFFFFFF ;
|
||
|
|
ROM256X1A mem_1_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_1_1));
|
||
|
|
|
||
|
|
defparam mem_1_5.initval = 256'hFFFF55555557FFFFFFF55555552AAAAAAAAAAAAAA8000000155555552AAAAAAB ;
|
||
|
|
ROM256X1A mem_1_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_2_1));
|
||
|
|
|
||
|
|
defparam mem_1_4.initval = 256'h000155555555555555555555555555555555555552AAAAAABFFFFFFFFFFFFFFF ;
|
||
|
|
ROM256X1A mem_1_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_3_1));
|
||
|
|
|
||
|
|
defparam mem_1_3.initval = 256'h0001FFFFFFFD5555555555555555555555FFFFFFF8000000000000007FFFFFFF ;
|
||
|
|
ROM256X1A mem_1_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_4_1));
|
||
|
|
|
||
|
|
defparam mem_1_2.initval = 256'hFFFEAAAAAAA80000000000000000000000000000055555555FFFFFFFD5555555 ;
|
||
|
|
ROM256X1A mem_1_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_5_1));
|
||
|
|
|
||
|
|
defparam mem_1_1.initval = 256'hFFFE00000005555555400000002AAAAAABFFFFFFF80000000AAAAAAAFFFFFFFF ;
|
||
|
|
ROM256X1A mem_1_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_6_1));
|
||
|
|
|
||
|
|
defparam mem_1_0.initval = 256'h555400000005555555400000002AAAAAAAAAAAAAA8000000155555552AAAAAAB ;
|
||
|
|
ROM256X1A mem_1_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_7_1));
|
||
|
|
|
||
|
|
defparam mem_2_7.initval = 256'h0000000000000005555555400000000000000000000002AAAAAABFFFFFFFAAAA ;
|
||
|
|
ROM256X1A mem_2_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_0_2));
|
||
|
|
|
||
|
|
defparam mem_2_6.initval = 256'h0000000000000002AAAAAAA00000005555555400000007FFFFFFEAAAAAAAFFFF ;
|
||
|
|
ROM256X1A mem_2_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_1_2));
|
||
|
|
|
||
|
|
defparam mem_2_5.initval = 256'h00000000000000055555554AAAAAAAD555555400000007FFFFFFEAAAAAAAFFFF ;
|
||
|
|
ROM256X1A mem_2_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_2_2));
|
||
|
|
|
||
|
|
defparam mem_2_4.initval = 256'h0000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAA8000000155555550000 ;
|
||
|
|
ROM256X1A mem_2_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_3_2));
|
||
|
|
|
||
|
|
defparam mem_2_3.initval = 256'h00000000000000000000000AAAAAAAAAAAAAAAAAAAAAA8000000155555550000 ;
|
||
|
|
ROM256X1A mem_2_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_4_2));
|
||
|
|
|
||
|
|
defparam mem_2_2.initval = 256'h0000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAFFFFFFFFFFFFFFFFFFF ;
|
||
|
|
ROM256X1A mem_2_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_5_2));
|
||
|
|
|
||
|
|
defparam mem_2_1.initval = 256'h00000000000000055555555FFFFFFFAAAAAAAAAAAAAAAFFFFFFFFFFFFFFFFFFF ;
|
||
|
|
ROM256X1A mem_2_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_6_2));
|
||
|
|
|
||
|
|
defparam mem_2_0.initval = 256'h00000000000000000000001FFFFFFFAAAAAAAAAAAAAAAD555555555555555555 ;
|
||
|
|
ROM256X1A mem_2_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
|
||
|
|
.AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
|
||
|
|
.AD0(Address[0]), .DO0(mdL0_7_2));
|
||
|
|
|
||
|
|
MUX41 mux_7 (.D0(mdL0_0_0), .D1(mdL0_0_1), .D2(mdL0_0_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout7_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_6 (.D0(mdL0_1_0), .D1(mdL0_1_1), .D2(mdL0_1_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout6_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_5 (.D0(mdL0_2_0), .D1(mdL0_2_1), .D2(mdL0_2_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout5_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_4 (.D0(mdL0_3_0), .D1(mdL0_3_1), .D2(mdL0_3_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout4_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_3 (.D0(mdL0_4_0), .D1(mdL0_4_1), .D2(mdL0_4_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout3_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_2 (.D0(mdL0_5_0), .D1(mdL0_5_1), .D2(mdL0_5_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout2_ffin));
|
||
|
|
|
||
|
|
MUX41 mux_1 (.D0(mdL0_6_0), .D1(mdL0_6_1), .D2(mdL0_6_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout1_ffin));
|
||
|
|
|
||
|
|
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||
|
|
|
||
|
|
MUX41 mux_0 (.D0(mdL0_7_0), .D1(mdL0_7_1), .D2(mdL0_7_2), .D3(scuba_vlo),
|
||
|
|
.SD1(Address[8]), .SD2(Address[9]), .Z(qdataout0_ffin));
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
// exemplar begin
|
||
|
|
// exemplar attribute FF_7 GSR ENABLED
|
||
|
|
// exemplar attribute FF_6 GSR ENABLED
|
||
|
|
// exemplar attribute FF_5 GSR ENABLED
|
||
|
|
// exemplar attribute FF_4 GSR ENABLED
|
||
|
|
// exemplar attribute FF_3 GSR ENABLED
|
||
|
|
// exemplar attribute FF_2 GSR ENABLED
|
||
|
|
// exemplar attribute FF_1 GSR ENABLED
|
||
|
|
// exemplar attribute FF_0 GSR ENABLED
|
||
|
|
// exemplar end
|
||
|
|
|
||
|
|
endmodule
|