54 lines
2.3 KiB
Plaintext
54 lines
2.3 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="mipi_dsi_bridge" device="LCMXO3LF-6900C-5BG256C" default_implementation="mipi_dsi_bridge">
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<Options/>
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<Implementation title="mipi_dsi_bridge" dir="mipi_dsi_bridge" description="mipi_dsi_bridge" synthesis="lse" default_strategy="Strategy1">
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<Options def_top="mipi_dsi_bridge" top="mipi_dsi_bridge"/>
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<Source name="PLL.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="DDR_MIPI.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="FIFo.ipx" type="IPX_Module" type_short="IPX" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="FIFo.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="PLL.ipx" type="IPX_Module" type_short="IPX" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="DDR_MIPI.ipx" type="IPX_Module" type_short="IPX" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="ROM.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="ROM.ipx" type="IPX_Module" type_short="IPX" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="send_mipi_frame.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="spi_slave.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="tb_send_frame.v" type="Verilog" type_short="Verilog" excluded="TRUE">
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<Options/>
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</Source>
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<Source name="tb_spi_bridge.v" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
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<Options/>
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</Source>
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<Source name="mipi_dsi_bridge.v" type="Verilog" type_short="Verilog">
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<Options top_module="mipi_dsi_bridge"/>
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</Source>
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<Source name="mipi_dsi_bridge.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="mipi_dsi_bridge/mipi_dsi_bridge.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="mipi_dsi_bridge1.sty"/>
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</BaliProject>
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