From 01bd21fd8730eb5e0283209f8778cdf767dbf373 Mon Sep 17 00:00:00 2001 From: Gaurav Singh Date: Sun, 19 Jan 2020 15:29:01 +0100 Subject: [PATCH] Update tb_spi_bridge.v --- FPGA/Test_bench/tb_spi_bridge.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA/Test_bench/tb_spi_bridge.v b/FPGA/Test_bench/tb_spi_bridge.v index 011d459..16724bf 100644 --- a/FPGA/Test_bench/tb_spi_bridge.v +++ b/FPGA/Test_bench/tb_spi_bridge.v @@ -47,7 +47,7 @@ wire reset_g; GSR GSR_INST (.GSR (reset_g)); PUR PUR_INST (.PUR (reset_g)); -counter counter_ins(nsys_reset, clock, hs_clock_o, hs_data_o , buf_clkout_lp_n_o, buf_clkout_lp_p_o, buf_dout_lp_n_o, +mipi_dsi_bridge mipi_dsi_bridge_ins(nsys_reset, clock, hs_clock_o, hs_data_o , buf_clkout_lp_n_o, buf_clkout_lp_p_o, buf_dout_lp_n_o, buf_dout_lp_p_o, byte_clock_o, tx_ready_o, write_to_fifo,read_from_fifo_w, reg_1v8_en, reg_3v0_en, lcd_rst, bl_en, spi_miso_o, spi_data, spi_cs, spi_clock, 1'b1); @@ -144,4 +144,4 @@ begin $finish; end -endmodule \ No newline at end of file +endmodule