diff --git a/FPGA/Soruce/DDR.lpc b/FPGA/Soruce/DDR.lpc
new file mode 100644
index 0000000..edf9b44
--- /dev/null
+++ b/FPGA/Soruce/DDR.lpc
@@ -0,0 +1,56 @@
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=DDR
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=09/08/2019
+Time=10:33:27
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=
+trioddr=0
+highspeed=0
+io_type=
+num_int=
+width=
+freq_in=
+bandwidth=
+aligned=
+pre-configuration=DISABLED
+mode2=Transmit
+trioddr2=0
+highspeed2=0
+io_type2=LVDS25
+freq_in2=96
+gear=4x
+aligned2=Edge-to-Edge
+num_int2=2
+width2=1
+Interface=GDDRX4_TX.ECLK.Aligned
+Delay=Bypass
+DelVal=
+UsePll=
+GenPll=0
+
+[Command]
+cmd_line= -w -n DDR -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -type iol -mode out -io_type LVDS25 -width 1 -freq_in 96 -gear 4 -clk eclk -aligned -del -1
diff --git a/FPGA/Soruce/DDR_MIPI.ipx b/FPGA/Soruce/DDR_MIPI.ipx
new file mode 100644
index 0000000..1e14b4c
--- /dev/null
+++ b/FPGA/Soruce/DDR_MIPI.ipx
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
diff --git a/FPGA/Soruce/DDR_MIPI.lpc b/FPGA/Soruce/DDR_MIPI.lpc
new file mode 100644
index 0000000..f8b5d66
--- /dev/null
+++ b/FPGA/Soruce/DDR_MIPI.lpc
@@ -0,0 +1,56 @@
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=DDR_MIPI
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=09/13/2019
+Time=22:33:27
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=
+trioddr=0
+highspeed=0
+io_type=
+num_int=
+width=
+freq_in=
+bandwidth=
+aligned=
+pre-configuration=DISABLED
+mode2=Transmit_MIPI
+trioddr2=0
+highspeed2=0
+io_type2=LVCMOS25
+freq_in2=200
+gear=4x
+aligned2=Centered
+num_int2=1
+width2=1
+Interface=GDDRX4_TX.ECLK.Centered
+Delay=Bypass
+DelVal=
+UsePll=
+GenPll=0
+
+[Command]
+cmd_line= -w -n DDR_MIPI -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -type iol -mode out -io_type MIPI_LP -width 1 -freq_in 200 -gear 4 -clk eclk -del -1
diff --git a/FPGA/Soruce/DDR_MIPI.v b/FPGA/Soruce/DDR_MIPI.v
new file mode 100644
index 0000000..0f8d5ed
--- /dev/null
+++ b/FPGA/Soruce/DDR_MIPI.v
@@ -0,0 +1,168 @@
+/*
+ * File: tb_spi_bridge.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+`timescale 1 ns / 1 ps
+module DDR_MIPI (clkout_lp0_i, buf_clkout_lp0_o,
+ clkout_lp1_i, buf_clkout_lp1_o,
+ clock_slow_i, clockp_fast_data_i,
+ clocks_fast_clk_i, mipi_clock_o,
+ lock_chk_i, reset_i, byte_clock_o,
+ tristate_data_i,tristate_clk_i, tx_ready_o,
+ buf_dout_lp0_o, dout_lp0_i,
+ buf_dout_lp1_o, dout_lp1_i,
+ data_i, mipi_data_o)
+ /* synthesis NGD_DRC_MASK=1 */;
+
+ input wire clkout_lp0_i; //lp link for mipi clkp
+ input wire clkout_lp1_i; //lp line for mipi clkn
+ input wire clock_slow_i; // slow clock for sync
+ input wire clockp_fast_data_i; //fast clokc input for mipi data
+ input wire clocks_fast_clk_i; //fast clock input for mipi clok
+ input wire lock_chk_i; //clock check
+ input wire reset_i; //reset active high
+ input wire tristate_data_i; //controls HS pin tristate active high
+ input wire tristate_clk_i; //controls HS pin tristate active high
+ input wire dout_lp0_i; //lp line mipi datap
+
+
+ input wire dout_lp1_i; //lp line mipi datan
+ input wire [7:0] data_i; //mipi data input
+ output wire buf_clkout_lp0_o; //mipi clock lp0 out
+ output wire buf_clkout_lp1_o; //mipi clock lp1 out
+ output wire mipi_clock_o; //mipi clock out
+ output wire byte_clock_o; //ddr byte clock output
+ output wire tx_ready_o; //After reset, Indicate completion of reset synchronization
+ output wire [0:0] buf_dout_lp0_o; //data lp0 out
+ output wire [0:0] buf_dout_lp1_o; //data lp1 out
+ output wire [0:0] mipi_data_o; //mipi data out
+
+
+ wire opensync_0;
+ wire opensync_1;
+ wire opensync_cken;
+ wire opensync_2;
+ wire buf_clkout;
+ wire scuba_vhi;
+ wire d70;
+ wire d60;
+ wire d50;
+ wire d40;
+ wire d30;
+ wire d20;
+ wire d10;
+ wire d00;
+ wire eclkc;
+ wire sclk_t;
+ wire cdiv1;
+ wire scuba_vlo;
+ wire eclkd;
+ wire xstop;
+ wire xstart;
+ wire opensync_3;
+ wire tristate_data_o;
+ wire tristate_clk_o;
+ wire buf_douto0;
+
+ defparam LUT4_1.initval = 16'h0a78 ;
+ ROM16X1A LUT4_1 (.AD3(opensync_0), .AD2(opensync_3), .AD1(lock_chk_i),
+ .AD0(scuba_vhi), .DO0(opensync_cken));
+
+ defparam LUT4_0.initval = 16'hfffe ;
+ ROM16X1A LUT4_0 (.AD3(opensync_0), .AD2(opensync_1), .AD1(scuba_vlo),
+ .AD0(scuba_vlo), .DO0(xstop));
+
+ FD1P3BX FF_3 (.D(opensync_3), .SP(opensync_cken), .CK(clock_slow_i), .PD(reset_i),
+ .Q(opensync_0))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_2 (.D(opensync_0), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
+ .Q(opensync_1))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_1 (.D(opensync_1), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
+ .Q(opensync_2))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_0 (.D(opensync_2), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
+ .Q(opensync_3))
+ /* synthesis GSR="ENABLED" */;
+
+ OB Inst1_OB (.I(clkout_lp1_i), .O(buf_clkout_lp1_o));
+ OB Inst2_OB (.I(clkout_lp0_i), .O(buf_clkout_lp0_o));
+ OB Inst3_OB (.I(dout_lp1_i), .O(buf_dout_lp1_o));
+ OB Inst4_OB (.I(dout_lp0_i), .O(buf_dout_lp0_o));
+
+ OFS1P3DX Inst8_OFS1P3DX (.D(tristate_clk_i), .SP(scuba_vhi), .SCLK(sclk_t),
+ .CD(reset_i), .Q(tristate_clock_o));
+
+ OFS1P3DX Inst9_OFS1P3DX (.D(tristate_data_i), .SP(scuba_vhi), .SCLK(sclk_t),
+ .CD(reset_i), .Q(tristate_data_o));
+
+ OBZ Inst7_OBZ (.I(buf_clkout), .T(tristate_clock_o), .O(mipi_clock_o))
+ /* synthesis IO_TYPE="MIPI" */;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ ODDRX4B Inst6_ODDRX4B (.D0(scuba_vhi), .D1(scuba_vlo), .D2(scuba_vhi),
+ .D3(scuba_vlo), .D4(scuba_vhi), .D5(scuba_vlo), .D6(scuba_vhi),
+ .D7(scuba_vlo), .ECLK(eclkc), .SCLK(sclk_t), .RST(reset_i), .Q(buf_clkout));
+
+ ODDRX4B Inst5_ODDRX4B0 (.D0(d00), .D1(d10), .D2(d20), .D3(d30), .D4(d40),
+ .D5(d50), .D6(d60), .D7(d70), .ECLK(eclkd), .SCLK(sclk_t), .RST(reset_i),
+ .Q(buf_douto0));
+
+ ECLKSYNCA Inst4_ECLKSYNCA (.ECLKI(clocks_fast_clk_i), .STOP(xstop), .ECLKO(eclkc));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam Inst3_CLKDIVC.DIV = "4.0" ;
+ CLKDIVC Inst3_CLKDIVC (.RST(reset_i), .CLKI(eclkd), .ALIGNWD(scuba_vlo),
+ .CDIV1(cdiv1), .CDIVX(sclk_t));
+
+ ECLKSYNCA Inst2_ECLKSYNCA (.ECLKI(clockp_fast_data_i), .STOP(xstop), .ECLKO(eclkd));
+
+ OBZ Inst1_OBZ0 (.I(buf_douto0), .T(tristate_data_o), .O(mipi_data_o[0]))
+ /* synthesis IO_TYPE="MIPI" */;
+
+ assign byte_clock_o = sclk_t;
+ assign d70 = data_i[7];
+ assign d60 = data_i[6];
+ assign d50 = data_i[5];
+ assign d40 = data_i[4];
+ assign d30 = data_i[3];
+ assign d20 = data_i[2];
+ assign d10 = data_i[1];
+ assign d00 = data_i[0];
+ assign tx_ready_o = xstart;
+ assign xstart = opensync_3;
+
+
+ // exemplar begin
+ // exemplar attribute FF_3 GSR ENABLED
+ // exemplar attribute FF_2 GSR ENABLED
+ // exemplar attribute FF_1 GSR ENABLED
+ // exemplar attribute FF_0 GSR ENABLED
+ // exemplar attribute Inst12_BB IO_TYPE MIPI_LP
+ // exemplar attribute Inst11_BB IO_TYPE MIPI_LP
+ // exemplar attribute Inst10_BB0 IO_TYPE MIPI_LP
+ // exemplar attribute Inst9_BB0 IO_TYPE MIPI_LP
+ // exemplar attribute Inst7_OBZ IO_TYPE MIPI
+ // exemplar attribute Inst1_OBZ0 IO_TYPE MIPI
+ // exemplar end
+
+endmodule
diff --git a/FPGA/Soruce/FIFo.ipx b/FPGA/Soruce/FIFo.ipx
new file mode 100644
index 0000000..22cb427
--- /dev/null
+++ b/FPGA/Soruce/FIFo.ipx
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/FPGA/Soruce/FIFo.lpc b/FPGA/Soruce/FIFo.lpc
new file mode 100644
index 0000000..35f62dd
--- /dev/null
+++ b/FPGA/Soruce/FIFo.lpc
@@ -0,0 +1,53 @@
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=FIFo
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=01/16/2020
+Time=00:09:17
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=1024
+RWidth=8
+WDepth=1024
+WWidth=8
+regout=0
+CtrlByRdEn=0
+ClockEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=1000
+PfDeassert=506
+Reset=Async
+Reset1=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n FIFo -lang verilog -synth lse -bb -arch xo3c00f -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 10 -pf 1000
diff --git a/FPGA/Soruce/FIFo.v b/FPGA/Soruce/FIFo.v
new file mode 100644
index 0000000..1ceced5
--- /dev/null
+++ b/FPGA/Soruce/FIFo.v
@@ -0,0 +1,65 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
+/* Module Version: 5.8 */
+/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n FIFo -lang verilog -synth lse -bb -arch xo3c00f -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 10 -pf 1000 */
+/* Thu Jan 16 00:09:17 2020 */
+
+
+`timescale 1 ns / 1 ps
+module FIFo (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q,
+ Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
+ input wire [7:0] Data;
+ input wire WrClock;
+ input wire RdClock;
+ input wire WrEn;
+ input wire RdEn;
+ input wire Reset;
+ input wire RPReset;
+ output wire [7:0] Q;
+ output wire Empty;
+ output wire Full;
+ output wire AlmostEmpty;
+ output wire AlmostFull;
+
+ wire scuba_vhi;
+ wire Empty_int;
+ wire Full_int;
+ wire scuba_vlo;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam FIFo_0_0.FULLPOINTER1 = "0b01111111111000" ;
+ defparam FIFo_0_0.FULLPOINTER = "0b10000000000000" ;
+ defparam FIFo_0_0.AFPOINTER1 = "0b01111100111000" ;
+ defparam FIFo_0_0.AFPOINTER = "0b01111101000000" ;
+ defparam FIFo_0_0.AEPOINTER1 = "0b00000001011000" ;
+ defparam FIFo_0_0.AEPOINTER = "0b00000001010000" ;
+ defparam FIFo_0_0.ASYNC_RESET_RELEASE = "SYNC" ;
+ defparam FIFo_0_0.GSR = "DISABLED" ;
+ defparam FIFo_0_0.RESETMODE = "ASYNC" ;
+ defparam FIFo_0_0.REGMODE = "NOREG" ;
+ defparam FIFo_0_0.CSDECODE_R = "0b11" ;
+ defparam FIFo_0_0.CSDECODE_W = "0b11" ;
+ defparam FIFo_0_0.DATA_WIDTH_R = 9 ;
+ defparam FIFo_0_0.DATA_WIDTH_W = 9 ;
+ FIFO8KB FIFo_0_0 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), .DI3(Data[3]),
+ .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), .DI7(Data[7]), .DI8(scuba_vlo),
+ .DI9(scuba_vlo), .DI10(scuba_vlo), .DI11(scuba_vlo), .DI12(scuba_vlo),
+ .DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), .DI16(scuba_vlo),
+ .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), .CSR0(scuba_vhi),
+ .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), .WE(WrEn),
+ .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), .RST(Reset),
+ .RPRST(RPReset), .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]),
+ .DO4(Q[4]), .DO5(Q[5]), .DO6(Q[6]), .DO7(Q[7]), .DO8(), .DO9(),
+ .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), .DO17(),
+ .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));
+
+ assign Empty = Empty_int;
+ assign Full = Full_int;
+
+
+ // exemplar begin
+ // exemplar end
+
+endmodule
diff --git a/FPGA/Soruce/PLL.ipx b/FPGA/Soruce/PLL.ipx
new file mode 100644
index 0000000..3064aad
--- /dev/null
+++ b/FPGA/Soruce/PLL.ipx
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
diff --git a/FPGA/Soruce/PLL.lpc b/FPGA/Soruce/PLL.lpc
new file mode 100644
index 0000000..9afd0d6
--- /dev/null
+++ b/FPGA/Soruce/PLL.lpc
@@ -0,0 +1,87 @@
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=PLL
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=01/14/2020
+Time=21:29:07
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+mode=Frequency
+CLKI=12
+CLKI_DIV=1
+BW=1.146
+VCO=480.000
+fb_mode=CLKOP
+CLKFB_DIV=8
+FRACN_ENABLE=0
+FRACN_DIV=0
+DynamicPhase=STATIC
+ClkEnable=0
+Standby=0
+Enable_sel=0
+PLLRst=0
+PLLMRst=0
+ClkOS2Rst=0
+ClkOS3Rst=0
+LockSig=0
+LockStk=0
+WBProt=0
+OPBypass=0
+OPUseDiv=0
+CLKOP_DIV=5
+FREQ_PIN_CLKOP=96
+OP_Tol=0.0
+CLKOP_AFREQ=96.000000
+CLKOP_PHASEADJ=0
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+EnCLKOS=1
+OSBypass=0
+OSUseDiv=0
+CLKOS_DIV=5
+FREQ_PIN_CLKOS=96
+OS_Tol=0.0
+CLKOS_AFREQ=96.000000
+CLKOS_PHASEADJ=90
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+EnCLKOS2=1
+OS2Bypass=0
+OS2UseDiv=0
+CLKOS2_DIV=10
+FREQ_PIN_CLKOS2=48
+OS2_Tol=0.0
+CLKOS2_AFREQ=48.000000
+CLKOS2_PHASEADJ=0
+EnCLKOS3=0
+OS3Bypass=0
+OS3UseDiv=0
+CLKOS3_DIV=1
+FREQ_PIN_CLKOS3=48
+OS3_Tol=0.0
+CLKOS3_AFREQ=48.000000
+CLKOS3_PHASEADJ=0
+
+[Command]
+cmd_line= -w -n PLL -lang verilog -synth lse -arch xo3c00f -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -fclkos 96 -fclkos_tol 0.0 -fclkos2 48 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 1
diff --git a/FPGA/Soruce/PLL.v b/FPGA/Soruce/PLL.v
new file mode 100644
index 0000000..43acd64
--- /dev/null
+++ b/FPGA/Soruce/PLL.v
@@ -0,0 +1,103 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
+/* Module Version: 5.7 */
+/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n PLL -lang verilog -synth lse -arch xo3c00f -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -fclkos 96 -fclkos_tol 0.0 -fclkos2 48 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 1 */
+/* Tue Jan 14 21:29:07 2020 */
+
+
+`timescale 1 ns / 1 ps
+module PLL (CLKI, CLKOP, CLKOS, CLKOS2)/* synthesis NGD_DRC_MASK=1 */;
+ input wire CLKI;
+ output wire CLKOP;
+ output wire CLKOS;
+ output wire CLKOS2;
+
+ wire LOCK;
+ wire CLKOS2_t;
+ wire CLKOS_t;
+ wire CLKOP_t;
+ wire scuba_vlo;
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.MRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
+ defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+ defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+ defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
+ defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+ defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOS2_CPHASE = 9 ;
+ defparam PLLInst_0.CLKOS_FPHASE = 2 ;
+ defparam PLLInst_0.CLKOS_CPHASE = 5 ;
+ defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+ defparam PLLInst_0.CLKOP_CPHASE = 4 ;
+ defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+ defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+ defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
+ defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+ defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
+ defparam PLLInst_0.FRACN_DIV = 0 ;
+ defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
+ defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
+ defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
+ defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+ defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
+ defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
+ defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
+ defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+ defparam PLLInst_0.CLKOS3_DIV = 1 ;
+ defparam PLLInst_0.CLKOS2_DIV = 10 ;
+ defparam PLLInst_0.CLKOS_DIV = 5 ;
+ defparam PLLInst_0.CLKOP_DIV = 5 ;
+ defparam PLLInst_0.CLKFB_DIV = 8 ;
+ defparam PLLInst_0.CLKI_DIV = 1 ;
+ defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
+ EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
+ .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
+ .LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
+ .RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
+ .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
+ .ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
+ .PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
+ .PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
+ .PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
+ .PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
+ .PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t),
+ .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
+ .PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
+ .PLLDATO2(), .PLLDATO1(), .PLLDATO0())
+ /* synthesis FREQUENCY_PIN_CLKOS2="48.000000" */
+ /* synthesis FREQUENCY_PIN_CLKOS="96.000000" */
+ /* synthesis FREQUENCY_PIN_CLKOP="96.000000" */
+ /* synthesis FREQUENCY_PIN_CLKI="12.000000" */
+ /* synthesis ICP_CURRENT="7" */
+ /* synthesis LPF_RESISTOR="8" */;
+
+ assign CLKOS2 = CLKOS2_t;
+ assign CLKOS = CLKOS_t;
+ assign CLKOP = CLKOP_t;
+
+
+ // exemplar begin
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 48.000000
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 96.000000
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 96.000000
+ // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 12.000000
+ // exemplar attribute PLLInst_0 ICP_CURRENT 7
+ // exemplar attribute PLLInst_0 LPF_RESISTOR 8
+ // exemplar end
+
+endmodule
diff --git a/FPGA/Soruce/ROM.ipx b/FPGA/Soruce/ROM.ipx
new file mode 100644
index 0000000..174c035
--- /dev/null
+++ b/FPGA/Soruce/ROM.ipx
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FPGA/Soruce/ROM.lpc b/FPGA/Soruce/ROM.lpc
new file mode 100644
index 0000000..bba826d
--- /dev/null
+++ b/FPGA/Soruce/ROM.lpc
@@ -0,0 +1,40 @@
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=Distributed_ROM
+CoreRevision=2.8
+ModuleName=ROM
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=01/14/2020
+Time=20:17:42
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Addresses=768
+Data=8
+LUT=1
+MemFile=c:/users/gaurav/documents/fpga/lattice/counter/rom.mem
+MemFormat=orca
+
+[FilesGenerated]
+c:/users/gaurav/documents/fpga/lattice/counter/rom.mem=mem
+
+[Command]
+cmd_line= -w -n ROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -dram -type romblk -addr_width 10 -num_words 768 -data_width 8 -outdata REGISTERED -memfile c:/users/gaurav/documents/fpga/lattice/counter/rom.mem -memformat orca
diff --git a/FPGA/Soruce/ROM.v b/FPGA/Soruce/ROM.v
new file mode 100644
index 0000000..77d89e4
--- /dev/null
+++ b/FPGA/Soruce/ROM.v
@@ -0,0 +1,240 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.0.396.4 */
+/* Module Version: 2.8 */
+/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n ROM -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -type rom -addr_width 10 -num_rows 768 -data_width 8 -outdata REGISTERED -memfile c:/users/gaurav/documents/fpga/lattice/counter/rom.mem -memformat orca */
+/* Tue Jan 14 20:17:42 2020 */
+
+
+`timescale 1 ns / 1 ps
+module ROM (Address, OutClock, OutClockEn, Reset, Q)/* synthesis NGD_DRC_MASK=1 */;
+ input wire [9:0] Address;
+ input wire OutClock;
+ input wire OutClockEn;
+ input wire Reset;
+ output wire [7:0] Q;
+
+ wire qdataout7_ffin;
+ wire mdL0_0_2;
+ wire mdL0_0_1;
+ wire mdL0_0_0;
+ wire qdataout6_ffin;
+ wire mdL0_1_2;
+ wire mdL0_1_1;
+ wire mdL0_1_0;
+ wire qdataout5_ffin;
+ wire mdL0_2_2;
+ wire mdL0_2_1;
+ wire mdL0_2_0;
+ wire qdataout4_ffin;
+ wire mdL0_3_2;
+ wire mdL0_3_1;
+ wire mdL0_3_0;
+ wire qdataout3_ffin;
+ wire mdL0_4_2;
+ wire mdL0_4_1;
+ wire mdL0_4_0;
+ wire qdataout2_ffin;
+ wire mdL0_5_2;
+ wire mdL0_5_1;
+ wire mdL0_5_0;
+ wire qdataout1_ffin;
+ wire mdL0_6_2;
+ wire mdL0_6_1;
+ wire mdL0_6_0;
+ wire qdataout0_ffin;
+ wire scuba_vlo;
+ wire mdL0_7_2;
+ wire mdL0_7_1;
+ wire mdL0_7_0;
+
+ FD1P3DX FF_7 (.D(qdataout7_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[7]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_6 (.D(qdataout6_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[6]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_5 (.D(qdataout5_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[5]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_4 (.D(qdataout4_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[4]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_3 (.D(qdataout3_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[3]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_2 (.D(qdataout2_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[2]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_1 (.D(qdataout1_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[1]))
+ /* synthesis GSR="ENABLED" */;
+
+ FD1P3DX FF_0 (.D(qdataout0_ffin), .SP(OutClockEn), .CK(OutClock), .CD(Reset),
+ .Q(Q[0]))
+ /* synthesis GSR="ENABLED" */;
+
+ defparam mem_0_7.initval = 256'hFFFFFFF8A228E28E28840000000020080A82A0828000002A2402090080402000 ;
+ ROM256X1A mem_0_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_0_0));
+
+ defparam mem_0_6.initval = 256'hFFFFFFF88220E20E208000011000000008822080800000220010000400000000 ;
+ ROM256X1A mem_0_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_1_0));
+
+ defparam mem_0_5.initval = 256'hFFFFFFFCE338F38F38D400008AA0A0A84613A46A0000013A541A050281422000 ;
+ ROM256X1A mem_0_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_2_0));
+
+ defparam mem_0_4.initval = 256'hFFFFFFFC6018718618040001DCCC62084E9180C2800000181C3E170780C0E000 ;
+ ROM256X1A mem_0_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_3_0));
+
+ defparam mem_0_3.initval = 256'hFFFFFFFE61987987981400008A02A0284619844A20000198642A010285402000 ;
+ ROM256X1A mem_0_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_4_0));
+
+ defparam mem_0_2.initval = 256'hFFFFFFFC0300F00F00D8400154E642B0E0300E2C00000100987426150C864201 ;
+ ROM256X1A mem_0_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_5_0));
+
+ defparam mem_0_1.initval = 256'hFFFFFFFA0280E80E80800002A8820000B1280B0120000080D038140A04000000 ;
+ ROM256X1A mem_0_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_6_0));
+
+ defparam mem_0_0.initval = 256'hFFFFFFFBC4F16F16F1484001566EC2902C0F42E4000000F4087422150D86C201 ;
+ ROM256X1A mem_0_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_7_0));
+
+ defparam mem_1_7.initval = 256'hAAAB55555555555555555555552AAAAAAAAAAAAAAD5555555FFFFFFFFFFFFFFF ;
+ ROM256X1A mem_1_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_0_1));
+
+ defparam mem_1_6.initval = 256'hFFFF55555555555555555555552AAAAAABFFFFFFF8000000000000007FFFFFFF ;
+ ROM256X1A mem_1_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_1_1));
+
+ defparam mem_1_5.initval = 256'hFFFF55555557FFFFFFF55555552AAAAAAAAAAAAAA8000000155555552AAAAAAB ;
+ ROM256X1A mem_1_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_2_1));
+
+ defparam mem_1_4.initval = 256'h000155555555555555555555555555555555555552AAAAAABFFFFFFFFFFFFFFF ;
+ ROM256X1A mem_1_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_3_1));
+
+ defparam mem_1_3.initval = 256'h0001FFFFFFFD5555555555555555555555FFFFFFF8000000000000007FFFFFFF ;
+ ROM256X1A mem_1_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_4_1));
+
+ defparam mem_1_2.initval = 256'hFFFEAAAAAAA80000000000000000000000000000055555555FFFFFFFD5555555 ;
+ ROM256X1A mem_1_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_5_1));
+
+ defparam mem_1_1.initval = 256'hFFFE00000005555555400000002AAAAAABFFFFFFF80000000AAAAAAAFFFFFFFF ;
+ ROM256X1A mem_1_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_6_1));
+
+ defparam mem_1_0.initval = 256'h555400000005555555400000002AAAAAAAAAAAAAA8000000155555552AAAAAAB ;
+ ROM256X1A mem_1_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_7_1));
+
+ defparam mem_2_7.initval = 256'h0000000000000005555555400000000000000000000002AAAAAABFFFFFFFAAAA ;
+ ROM256X1A mem_2_7 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_0_2));
+
+ defparam mem_2_6.initval = 256'h0000000000000002AAAAAAA00000005555555400000007FFFFFFEAAAAAAAFFFF ;
+ ROM256X1A mem_2_6 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_1_2));
+
+ defparam mem_2_5.initval = 256'h00000000000000055555554AAAAAAAD555555400000007FFFFFFEAAAAAAAFFFF ;
+ ROM256X1A mem_2_5 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_2_2));
+
+ defparam mem_2_4.initval = 256'h0000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAA8000000155555550000 ;
+ ROM256X1A mem_2_4 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_3_2));
+
+ defparam mem_2_3.initval = 256'h00000000000000000000000AAAAAAAAAAAAAAAAAAAAAA8000000155555550000 ;
+ ROM256X1A mem_2_3 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_4_2));
+
+ defparam mem_2_2.initval = 256'h0000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAFFFFFFFFFFFFFFFFFFF ;
+ ROM256X1A mem_2_2 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_5_2));
+
+ defparam mem_2_1.initval = 256'h00000000000000055555555FFFFFFFAAAAAAAAAAAAAAAFFFFFFFFFFFFFFFFFFF ;
+ ROM256X1A mem_2_1 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_6_2));
+
+ defparam mem_2_0.initval = 256'h00000000000000000000001FFFFFFFAAAAAAAAAAAAAAAD555555555555555555 ;
+ ROM256X1A mem_2_0 (.AD7(Address[7]), .AD6(Address[6]), .AD5(Address[5]),
+ .AD4(Address[4]), .AD3(Address[3]), .AD2(Address[2]), .AD1(Address[1]),
+ .AD0(Address[0]), .DO0(mdL0_7_2));
+
+ MUX41 mux_7 (.D0(mdL0_0_0), .D1(mdL0_0_1), .D2(mdL0_0_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout7_ffin));
+
+ MUX41 mux_6 (.D0(mdL0_1_0), .D1(mdL0_1_1), .D2(mdL0_1_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout6_ffin));
+
+ MUX41 mux_5 (.D0(mdL0_2_0), .D1(mdL0_2_1), .D2(mdL0_2_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout5_ffin));
+
+ MUX41 mux_4 (.D0(mdL0_3_0), .D1(mdL0_3_1), .D2(mdL0_3_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout4_ffin));
+
+ MUX41 mux_3 (.D0(mdL0_4_0), .D1(mdL0_4_1), .D2(mdL0_4_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout3_ffin));
+
+ MUX41 mux_2 (.D0(mdL0_5_0), .D1(mdL0_5_1), .D2(mdL0_5_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout2_ffin));
+
+ MUX41 mux_1 (.D0(mdL0_6_0), .D1(mdL0_6_1), .D2(mdL0_6_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout1_ffin));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ MUX41 mux_0 (.D0(mdL0_7_0), .D1(mdL0_7_1), .D2(mdL0_7_2), .D3(scuba_vlo),
+ .SD1(Address[8]), .SD2(Address[9]), .Z(qdataout0_ffin));
+
+
+
+ // exemplar begin
+ // exemplar attribute FF_7 GSR ENABLED
+ // exemplar attribute FF_6 GSR ENABLED
+ // exemplar attribute FF_5 GSR ENABLED
+ // exemplar attribute FF_4 GSR ENABLED
+ // exemplar attribute FF_3 GSR ENABLED
+ // exemplar attribute FF_2 GSR ENABLED
+ // exemplar attribute FF_1 GSR ENABLED
+ // exemplar attribute FF_0 GSR ENABLED
+ // exemplar end
+
+endmodule
diff --git a/FPGA/Soruce/Read_me.txt b/FPGA/Soruce/Read_me.txt
new file mode 100644
index 0000000..1d1449a
--- /dev/null
+++ b/FPGA/Soruce/Read_me.txt
@@ -0,0 +1 @@
+The directory contains lattice dimond proejct files and also IPexress files.
\ No newline at end of file
diff --git a/FPGA/Soruce/mipi_dsi_bridge.ldf b/FPGA/Soruce/mipi_dsi_bridge.ldf
new file mode 100644
index 0000000..f152861
--- /dev/null
+++ b/FPGA/Soruce/mipi_dsi_bridge.ldf
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FPGA/Soruce/mipi_dsi_bridge.lpf b/FPGA/Soruce/mipi_dsi_bridge.lpf
new file mode 100644
index 0000000..d77405f
--- /dev/null
+++ b/FPGA/Soruce/mipi_dsi_bridge.lpf
@@ -0,0 +1,33 @@
+RVL_ALIAS "pll_clk_p" "pll_clk_p";
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "clk" IO_TYPE=LVCMOS25 OPENDRAIN=OFF HYSTERESIS=SMALL ;
+LOCATE COMP "clk" SITE "C8" ;
+BLOCK JTAGPATHS ;
+LOCATE COMP "hs_clock_o" SITE "B9" ;
+IOBUF PORT "hs_clock_o" IO_TYPE=LVDS25E SLEWRATE=SLOW PULLMODE=NONE DRIVE=8 CLAMP=OFF OPENDRAIN=OFF ;
+LOCATE COMP "hs_data_o" SITE "D8" ;
+IOBUF PORT "hs_data_o" IO_TYPE=LVDS25E SLEWRATE=FAST PULLMODE=NONE DRIVE=8 ;
+IOBUF PORT "buf_clkout_lp_n_o" DRIVE=6 IO_TYPE=LVCMOS12 CLAMP=ON OPENDRAIN=OFF PULLMODE=DOWN ;
+IOBUF PORT "buf_clkout_lp_p_o" DRIVE=6 IO_TYPE=LVCMOS12 CLAMP=ON OPENDRAIN=OFF PULLMODE=DOWN ;
+IOBUF PORT "buf_dout_lp_n_o" DRIVE=6 IO_TYPE=LVCMOS12 CLAMP=ON OPENDRAIN=OFF PULLMODE=DOWN ;
+IOBUF PORT "buf_dout_lp_p_o" DRIVE=6 IO_TYPE=LVCMOS12 CLAMP=ON OPENDRAIN=OFF PULLMODE=DOWN ;
+LOCATE COMP "buf_clkout_lp_n_o" SITE "H16" ;
+LOCATE COMP "buf_clkout_lp_p_o" SITE "F16" ;
+LOCATE COMP "buf_dout_lp_p_o" SITE "H14" ;
+OUTPUT PORT "buf_clkout_lp_n_o" LOAD 100.000000 pF ;
+OUTPUT PORT "buf_clkout_lp_p_o" LOAD 100.000000 pF ;
+OUTPUT PORT "buf_dout_lp_n_o" LOAD 100.000000 pF ;
+OUTPUT PORT "buf_dout_lp_p_o" LOAD 100.000000 pF ;
+LOCATE COMP "nsys_reset" SITE "B3" ;
+LOCATE COMP "lcd_rst" SITE "D10" ;
+LOCATE COMP "reg_1v8_en" SITE "F8" ;
+LOCATE COMP "reg_3v0_en" SITE "B12" ;
+LOCATE COMP "bl_en" SITE "E11" ;
+IOBUF PORT "lcd_rst" OPENDRAIN=ON IO_TYPE=LVCMOS25 DRIVE=8 ;
+LOCATE COMP "spi_mosi_i" SITE "R8" ;
+LOCATE COMP "spi_miso_o" SITE "C1" ;
+LOCATE COMP "spi_clk_i" SITE "M6" ;
+LOCATE COMP "spi_csn_i" SITE "T7" ;
+LOCATE COMP "lcd_test_i" SITE "N2" ;
+LOCATE COMP "buf_dout_lp_n_o" SITE "K15" ;
diff --git a/FPGA/Soruce/mipi_dsi_bridge.v b/FPGA/Soruce/mipi_dsi_bridge.v
new file mode 100644
index 0000000..0ae9a38
--- /dev/null
+++ b/FPGA/Soruce/mipi_dsi_bridge.v
@@ -0,0 +1,376 @@
+/*
+ * File: MIPI_DSI_BRIDGE.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+module mipi_dsi_bridge(nsys_reset, clk,
+ hs_clock_o,
+ hs_data_o ,
+ buf_clkout_lp_n_o,
+ buf_clkout_lp_p_o,
+ buf_dout_lp_n_o,
+ buf_dout_lp_p_o,
+ reg_1v8_en,
+ reg_3v0_en,
+ lcd_rst,
+ bl_en,
+ spi_miso_o,
+ spi_mosi_i,
+ spi_csn_i,
+ spi_clk_i,
+ lcd_test_i);
+
+output reg reg_1v8_en;
+output reg reg_3v0_en;
+output reg lcd_rst;
+output reg bl_en;
+output spi_miso_o;
+output hs_clock_o;
+output hs_data_o;
+output wire buf_clkout_lp_n_o ;
+output wire buf_clkout_lp_p_o ;
+output wire buf_dout_lp_n_o ;
+output wire buf_dout_lp_p_o ;
+
+input wire nsys_reset;
+input clk; //clock input
+input spi_mosi_i;
+input spi_csn_i;
+input spi_clk_i;
+input lcd_test_i;
+
+
+
+
+reg spi_csn_reg1;
+reg spi_csn_reg2;
+reg spi_csn_reg3;
+reg write_cmd;
+reg fifo_reset;
+reg [7:0]command_r;
+reg [2:0] controller_state;
+reg [3:0] reset_state;
+reg [7:0] spi_cmd;
+reg [7:0] line_counter;
+reg [32:0] delay_counter;
+
+wire [7:0]fifo_out;
+wire pll_clk_spi;
+wire reset_i;
+wire pll_clk_p;
+wire pll_clk_s;
+wire pll_clk_s2;
+wire ready;
+wire sclk;
+wire lock;
+wire fifo_full;
+wire fifo_empty_w;
+wire fifo_almost_full;
+wire almost_empty;
+wire fifo_read_en_w;
+wire spi_byte_clock;
+wire fifo_write_en_r;
+wire [7:0]spi_rxdata;
+wire tx_finish_w;
+
+
+assign reset_i = !nsys_reset;
+
+assign pll_clk_spi = pll_clk_s2;
+
+PLL pll_i1 (.CLKI(clk ), .CLKOP(pll_clk_p), .CLKOS(pll_clk_s), .CLKOS2(pll_clk_s2));
+
+FIFo fifo_module( .Reset(fifo_reset),
+ .RPReset(1'b0),
+ .Data(spi_rxdata),
+ .Q(fifo_out),
+ .WrEn(fifo_write_en_r),
+ .RdEn(fifo_read_en_w),
+ .WrClock(spi_byte_clock),
+ .RdClock(byte_clock_o),
+ .Full(fifo_full),
+ .AlmostFull(fifo_almost_full),
+ .AlmostEmpty(almost_empty),
+ .Empty(fifo_empty_w)
+ );
+
+DPHY_TX_FRAME dphy_tx_frame(
+ .reset_i(reset_i), //reset active high
+ .command_i(command_r),
+ .write_cmd_i(write_cmd),
+ .clockp_fast_data_i(pll_clk_p), //fast clokc input for mipi data
+ .clocks_fast_clk_i(pll_clk_s), //fast clock input for mipi clok
+ .clock_slow_sync_i(pll_clk_s2), //slow clock for sync
+ .lock_chk_i(1'b1), //pll lock check
+ .fifo_almost_empty(almost_empty),
+ .fifo_empty(fifo_empty_w),
+ .data_i(fifo_out), //mipi data input from FIFO
+
+ .finish_o(tx_finish_w),
+ .fifo_read_en(fifo_read_en_w),
+ .buf_clkout_lp_p_o(buf_clkout_lp_p_o), //mipi clock lp0 out
+ .buf_clkout_lp_n_o(buf_clkout_lp_n_o), //mipi clock lp1 out
+ .buf_dout_lp_p_o(buf_dout_lp_p_o), //data lp0 out
+ .buf_dout_lp_n_o(buf_dout_lp_n_o), //data lp1 out
+ .byte_clock_o(byte_clock_o), //byte clock out
+ .hs_data_o(hs_data_o), //mipi data out
+ .hs_clock_o(hs_clock_o)); //mipi clock out
+
+
+
+SPI_SLAVE spi_slave_inst1 ( .clk_i(pll_clk_spi),
+ .rst_i(reset_i),
+ .rx_data_o(spi_rxdata),
+ .byte_clock_o(spi_byte_clock),
+ .spi_clk_i(spi_clk_i),
+ .spi_mosi_i(spi_mosi_i),
+ .spi_csn_i(spi_csn_i)
+ );
+
+
+
+parameter controller_state_reset_lcd = 3'h0;
+parameter controller_state_idle = 3'h1;
+parameter controller_state_cmd_received = 3'h2;
+parameter controller_state_cmd_busy = 3'h3;
+parameter controller_state_wait_cs = 3'h4;
+
+
+parameter state_lcd_activate_vee = 4'h0;
+parameter state_lcd_reset_active = 4'h1;
+parameter state_lcd_reset_wait = 4'h2;
+parameter state_lcd_reset_wait_for_vdd = 4'h3;
+parameter state_lcd_reset_send_cmd_init = 4'h4;
+parameter state_lcd_reset_wait_cmd = 4'h5;
+parameter state_lcd_reset_wait_init = 4'h6;
+parameter state_lcd_reset_tp_write = 4'h7;
+parameter state_lcd_reset_tp_wait = 4'h8;
+
+
+//reset sequence delay timing as per mipi specs
+parameter delay_reset_deactivated = 32'h1071B00; //250ms @ 46Mhz
+parameter delay_reset_ativated = 32'h6A980; //5ms @ 12Mhz
+parameter delay_reset_wait_vdd = 32'h10B80; //1ms
+parameter delay_wait_for_vdd = 32'h6A980; //5ms
+parameter delay_wait_init = 32'h6A980; //5ms
+
+
+parameter CMD_LCD_INIT = 8'h89; //from ROM 13th line
+parameter CMD_LCD_TP_FIRST = 8'hCF; //line 17
+parameter CMD_LCD_TP_NEXT = 8'hD9; //line 18
+parameter DISPLAY_LINE_MAX = 8'd240;
+
+always @(posedge reset_i or posedge byte_clock_o) //must be slower than ddr_byte_clock
+begin
+
+if (reset_i)
+ begin
+ controller_state <= controller_state_reset_lcd;
+ reset_state <= state_lcd_activate_vee;
+ lcd_rst <= 1'h0; //reset active
+ reg_1v8_en <= 1'h0; //reg inactive
+ reg_3v0_en <= 1'h0; //reg inactive
+ line_counter <= 8'h0;
+ end
+ else
+ begin
+
+ case (controller_state)
+ controller_state_reset_lcd: begin
+ if (delay_counter)
+ begin
+ delay_counter <= delay_counter - 1'b1;
+ end
+ else
+ begin
+ case (reset_state)
+ state_lcd_activate_vee:begin
+ reg_1v8_en <= 1'h1; //activate 1v8
+ lcd_rst <= 1'h1; //reset inactive
+ bl_en <= 1'h1; //enable BL
+ fifo_reset <= 1;
+ write_cmd <= 1'b0;
+
+ delay_counter <= delay_reset_deactivated;
+ reset_state <= state_lcd_reset_active;
+ end
+
+ state_lcd_reset_active:begin
+ fifo_reset <= 1'b0;
+ lcd_rst <= 1'h0; //reset active
+ delay_counter <= delay_reset_ativated;
+ reset_state <= state_lcd_reset_wait;
+ end
+
+ state_lcd_reset_wait:begin
+ fifo_reset <= 1'b1;
+ lcd_rst <= 1'h1; //reset inactive
+ delay_counter <= delay_reset_wait_vdd;
+ reset_state <= state_lcd_reset_wait_for_vdd;
+ end
+
+ state_lcd_reset_wait_for_vdd:begin
+ fifo_reset <= 1'b0;
+ reg_3v0_en <= 1'h1; //reg acitve
+ delay_counter <= delay_wait_for_vdd;
+ reset_state <= state_lcd_reset_send_cmd_init;
+ end
+
+ state_lcd_reset_send_cmd_init:begin
+ write_cmd <= 1'b1;
+ command_r <= CMD_LCD_INIT;
+ delay_counter <= 0;
+ reset_state <= state_lcd_reset_wait_cmd;
+ end
+
+ state_lcd_reset_wait_cmd:begin //lcd take quite some time to process some commands
+ if(tx_finish_w)
+ begin
+ delay_counter <= delay_wait_init;
+ reset_state <= state_lcd_reset_wait_init;
+ end
+ else
+ begin
+ write_cmd <= 1'b0;
+ end
+ end
+
+ state_lcd_reset_wait_init:begin
+ reset_state <= state_lcd_activate_vee; //reset, reset state machine
+
+ if (lcd_test_i)
+ begin
+ reset_state <= state_lcd_reset_tp_write;
+ line_counter <= 8'h0;
+ end
+ else
+ begin
+ controller_state <= controller_state_idle;
+ end
+ end
+
+ state_lcd_reset_tp_write:begin
+ write_cmd <= 1'b1;
+ line_counter <= line_counter + 1'b1;
+ if (line_counter == 8'h0)
+ begin
+ command_r <= CMD_LCD_TP_FIRST;
+ end
+ else
+ begin
+ command_r <= CMD_LCD_TP_NEXT;
+ end
+
+ delay_counter <= 0;
+ reset_state <= state_lcd_reset_tp_wait;
+ end
+
+ state_lcd_reset_tp_wait:begin
+ if (tx_finish_w)
+ begin
+ if (line_counter < DISPLAY_LINE_MAX)
+ begin
+ reset_state <= state_lcd_reset_tp_write;
+ end
+ else
+ begin
+ reset_state <= state_lcd_activate_vee; //reset reset_state
+ controller_state <= controller_state_wait_cs;
+ end
+ end
+ else
+ begin
+ write_cmd <= 1'b0;
+ end
+
+ end
+
+ default:begin
+ reset_state <= state_lcd_activate_vee;
+ end
+ endcase
+
+ end
+ end
+ controller_state_idle: begin
+ spi_csn_reg1 <= spi_csn_i;
+ spi_csn_reg2 <= spi_csn_reg1;
+ spi_csn_reg3 <= spi_csn_reg2;
+ if (!spi_csn_reg3 & spi_csn_reg2)
+ begin
+ write_cmd <= spi_csn_i;
+ command_r <= spi_cmd;
+ controller_state <= controller_state_cmd_received;
+ end
+ end
+ controller_state_cmd_received: begin
+ controller_state <= controller_state_cmd_busy;
+ end
+ controller_state_cmd_busy: begin
+ if(tx_finish_w)
+ begin
+ controller_state <= controller_state_wait_cs;
+ end
+ else
+ begin
+ write_cmd <= 1'b0;
+ end
+ end
+ controller_state_wait_cs: begin
+ if (!spi_csn_i) //wait till spi_csn_i goes idle
+ begin
+ controller_state <= controller_state_idle;
+ end
+ end
+ default: begin
+ controller_state <= controller_state_idle;
+ end
+ endcase
+ end
+
+end
+
+reg first_byte;
+
+assign fifo_write_en_r = !spi_csn_i;
+always @(posedge reset_i or posedge spi_byte_clock or posedge spi_csn_i)
+begin
+
+ if (reset_i)
+ begin
+ first_byte <= 1'b0;
+ spi_cmd <= 8'b0;
+ end
+ else
+ begin
+ if (spi_csn_i)
+ begin
+ first_byte <= 1'b0;
+ end
+ else
+ begin
+
+ if (first_byte == 1'b0)
+ begin
+ first_byte <= 1'b1;
+ spi_cmd <= spi_rxdata;
+ end
+ end
+ end
+end
+
+
+endmodule
diff --git a/FPGA/Soruce/rom.mem b/FPGA/Soruce/rom.mem
new file mode 100644
index 0000000..8dd0a89
--- /dev/null
+++ b/FPGA/Soruce/rom.mem
@@ -0,0 +1,20 @@
+000: 05 00 00 00 00 00 00 00 00
+009: 05 00 00 00 B8 15 11 00 25
+012: 05 00 00 00 B8 15 29 00 0F
+01B: 05 00 00 00 B8 15 3A 55 02
+024: 05 00 00 00 B8 15 36 80 12
+02D: 05 00 00 00 B8 15 3A 77 1F
+036: 05 00 00 00 B8 15 36 88 2A
+03F: 06 00 E0 01 B8 39 E1 01 0B 2C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+05D: 0A 00 D0 02 B8 05 2C 00 25 39 D1 02 07 2C
+06B: 06 00 E0 01 B8 39 E1 01 0B 3C
+075: 06 00 D0 02 B8 39 D1 02 07 3C
+07F: 06 00 00 00 B8 05 2C 00 25 00
+089: 15 00 00 00 B8 15 29 00 0F 15 11 00 25 15 36 00 29 15 3A 55 02 15 3A 55 02
+0AE: 05 00 00 00 B8 05 2C 00 25
+0B7: E6 01 00 00 B8 39 E1 01 0B 2C FF FF
+0C3: E6 01 00 00 B8 39 E1 01 0B 3C FF FF
+0CF: E6 01 00 00 B8 39 E1 01 0B 2C
+0D9: E6 01 00 00 B8 39 E1 01 0B 3C
+0E3: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE FB DE 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 96 B5 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 10 84 EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A EB 5A E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 E3 18 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 00 F8 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB 20 FB
+1D3: 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 0C F8 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 9F E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 E6 67 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 00 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 1F 60 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 3F 03 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2 54 A2
\ No newline at end of file
diff --git a/FPGA/Soruce/send_mipi_frame.v b/FPGA/Soruce/send_mipi_frame.v
new file mode 100644
index 0000000..f3bd824
--- /dev/null
+++ b/FPGA/Soruce/send_mipi_frame.v
@@ -0,0 +1,326 @@
+/*
+ * File: MIPI_DSI_BRIDGE.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+module DPHY_TX_FRAME(
+ reset_i, //reset active high
+ command_i,
+ write_cmd_i,
+ clockp_fast_data_i, //fast clokc input for mipi data
+ clocks_fast_clk_i, //fast clock input for mipi clok
+ clock_slow_sync_i, //slow clock for sync
+ lock_chk_i, //pll lock check
+ fifo_almost_empty,
+ fifo_empty,
+ data_i, //mipi data input Through FIFO
+ fifo_read_en,
+ buf_clkout_lp_p_o, //mipi clock lp0 out
+ buf_clkout_lp_n_o, //mipi clock lp1 out
+ buf_dout_lp_p_o, //data lp0 out
+ buf_dout_lp_n_o, //data lp1 out
+ byte_clock_o, //byte clock out
+ hs_data_o, //mipi data out
+ hs_clock_o, //mipi clock out
+ finish_o // state machine finished transmitting
+ );
+
+input wire write_cmd_i;
+input wire [7:0]command_i;
+input wire reset_i; //reset active high
+input wire clockp_fast_data_i; //fast clokc input for mipi data
+input wire clocks_fast_clk_i; //fast clock input for mipi clok
+input wire clock_slow_sync_i; //slow clock for sync
+input wire fifo_empty;
+input wire fifo_almost_empty;
+input wire lock_chk_i; //pll lock check
+input wire [7:0]data_i; //mipi data input
+output reg fifo_read_en;
+output wire buf_clkout_lp_p_o; //mipi clock lp_p out
+output wire buf_clkout_lp_n_o; //mipi clock lp_n out
+output wire buf_dout_lp_p_o; //data lp_p out
+output wire buf_dout_lp_n_o; //data lp_n out
+output wire byte_clock_o; //byte clock out
+output wire hs_data_o; //mipi data out
+output wire hs_clock_o; //mipi clock out
+output reg finish_o;
+
+wire ddr_ready_w;
+reg [7:0]command_r;
+reg [9:0]rom_addr_r;
+wire [7:0]rom_out;
+reg rom_read_en;
+
+reg [8:0]rom_tp_addr;
+reg rom_tb_read_en;
+ROM rom_inst1 (.Address(rom_addr_r), .OutClock(byte_clock_o), .OutClockEn(rom_read_en), .Reset(reset_i), .Q(rom_out));
+
+reg data_from_rom_nfifo;
+reg data_zero;
+reg hs_clock_tristate_r;
+reg hs_data_tristate_r;
+
+wire write_to_fifo_w;
+
+
+wire [7:0]mipi_data;
+reg [7:0]mipi_data_temp;
+
+reg clkout_lp_p_w;
+reg clkout_lp_n_w;
+reg dout_lp_p_w;
+reg dout_lp_n_w;
+
+DDR_MIPI ddr_mipi_inst1 ( .reset_i(reset_i),
+ .clkout_lp0_i(clkout_lp_p_w),
+ .clkout_lp1_i(clkout_lp_n_w),
+ .dout_lp0_i(dout_lp_p_w),
+ .dout_lp1_i(dout_lp_n_w),
+ .clock_slow_i(clock_slow_sync_i),
+ .data_i(mipi_data),
+ .clockp_fast_data_i(clockp_fast_data_i),
+ .clocks_fast_clk_i(clocks_fast_clk_i),
+ .lock_chk_i(lock_chk_i),
+ .tristate_data_i(hs_data_tristate_r),
+ .tristate_clk_i(hs_clock_tristate_r),
+
+ .byte_clock_o(byte_clock_o),
+ .tx_ready_o(ddr_ready_w),
+ .buf_clkout_lp0_o(buf_clkout_lp_p_o),
+ .buf_clkout_lp1_o(buf_clkout_lp_n_o),
+ .buf_dout_lp0_o(buf_dout_lp_p_o),
+ .buf_dout_lp1_o(buf_dout_lp_n_o),
+ .mipi_data_o(hs_data_o),
+ .mipi_clock_o(hs_clock_o));
+
+
+
+parameter send_frame_state_idle = 4'h0;
+parameter send_frame_state_enter_hs_clk1 = 4'h1;
+parameter send_frame_state_enter_hs_clk1_wait = 4'h2;
+parameter send_frame_state_enter_hs1 = 4'h3;
+parameter send_frame_state_enter_hs1_wait = 4'h4;
+parameter send_frame_state_enter_hs2 = 4'h5;
+parameter send_frame_state_lp_wait1 = 4'h6;
+parameter send_frame_state_lp_wait2 = 4'h7;
+parameter send_frame_state_enable_hs = 4'h8;
+parameter send_frame_state_send_preamble = 4'h9;
+parameter send_frame_state_send_rom = 4'hA;
+parameter send_frame_state_send_fifo = 4'hB;
+parameter send_frame_state_send_crc = 4'hC;
+parameter send_frame_state_finish = 4'hD;
+
+reg [4:0]frame_state;
+reg [9:0]rom_count;
+reg [8:0]zeros_count;
+reg [8:0]fifo_count;
+reg fifo_empty_reg;
+reg data_zero_reg;
+reg data_from_rom_nfifo_reg;
+
+
+always @(posedge reset_i or posedge byte_clock_o) //ddr module samples on falling edge of byte clock , so to align data_zero with posedge
+begin
+ if (reset_i)
+ begin
+ data_from_rom_nfifo_reg <= 1'h0;
+ data_zero_reg <= 1'h0;
+ end
+ else
+ begin
+
+ data_zero_reg <= data_zero;
+ data_from_rom_nfifo_reg <= data_from_rom_nfifo;
+ end
+end
+
+assign mipi_data = data_zero_reg? 8'h0:(data_from_rom_nfifo_reg ? rom_out:data_i); //switch between rom or data in or zero
+
+
+always @(posedge reset_i or negedge byte_clock_o)
+begin
+ if (reset_i)
+ begin
+ frame_state <= send_frame_state_idle;
+ clkout_lp_p_w <= 1'b1;
+ clkout_lp_n_w <= 1'b1;
+ dout_lp_p_w <= 1'b1;
+ dout_lp_n_w <= 1'b1;
+ data_zero <= 1'b1;
+ hs_data_tristate_r <= 1'b1; //tristate hs data
+ hs_clock_tristate_r <= 1'b1; //tristate hs clock
+ fifo_count <= 9'h0;
+ fifo_read_en <= 1'b0;
+ finish_o <= 1'b0;
+ data_from_rom_nfifo <= 1'b0;
+ end
+ else
+ begin
+ case (frame_state)
+ send_frame_state_idle: begin //set dp low , disable clock tri state to un acitve
+ clkout_lp_p_w <= 1'b1;
+ clkout_lp_n_w <= 1'b1;
+ dout_lp_p_w <= 1'b1;
+ dout_lp_n_w <= 1'b1;
+
+ hs_data_tristate_r <= 1'b1; //tristate hs data
+ hs_clock_tristate_r <= 1'b1; //tristate hs clock
+ rom_read_en <= 1'b0;
+
+ if (write_cmd_i)
+ begin
+ finish_o <= 1'b0;
+ data_from_rom_nfifo <= 1'b1; //read from rom
+ data_zero <= 1'b1;
+ rom_addr_r <= command_i; //First address of rom
+ frame_state <= send_frame_state_enter_hs_clk1;
+ end
+ else
+ begin
+ finish_o <= 1'b1;
+ end
+ end
+ send_frame_state_enter_hs_clk1:begin //genrate enter hs on clk // first falling edege of byte_clk
+ rom_read_en <= 1'b1;
+ clkout_lp_p_w <= 1'b0; //pull clock_lp low
+ clkout_lp_n_w <= 1'b1;
+ frame_state <= send_frame_state_enter_hs_clk1_wait;
+ end
+ send_frame_state_enter_hs_clk1_wait:begin //to achive 50ns minimum delay between lp and ln
+ rom_count[7:0] <= rom_out[7:0];
+ rom_addr_r <= rom_addr_r + 1'b1; //increse rom address for HSByte of rom count
+
+ frame_state <= send_frame_state_enter_hs1;
+ end
+ send_frame_state_enter_hs1: begin //Third falling edege of byte_clk
+ rom_count[9:8] <= rom_out[1:0]; //fetch MSB rom count
+ rom_addr_r <= rom_addr_r + 1'b1; //increse rom address
+
+ dout_lp_p_w <= 1'b0;
+ dout_lp_n_w <= 1'b1;
+
+
+ clkout_lp_p_w <= 1'b0; //pull both clock_lp low
+ clkout_lp_n_w <= 1'b0;
+
+ hs_clock_tristate_r <= 1'b0; //tristate disabled hs clock
+
+ frame_state <= send_frame_state_enter_hs1_wait;
+ end
+ send_frame_state_enter_hs1_wait: begin //Fourth Falling edge of byte_clk
+ fifo_count[7:0] <= rom_out[7:0]; //fetch expected LSB fifo length
+ rom_addr_r <= rom_addr_r + 1'b1; //increse rom address
+
+ frame_state <= send_frame_state_enter_hs2;
+ end
+ send_frame_state_enter_hs2: begin //Fifth falling edege of byte_clk
+ fifo_count[8] <= rom_out[0]; //fetch expected MSB fifo length
+ dout_lp_p_w <= 1'b0;
+ dout_lp_n_w <= 1'b0;
+
+ frame_state <= send_frame_state_lp_wait1;
+ end
+
+ send_frame_state_lp_wait1: begin //6th falling edege of byte_clk, now enable data input mux tristate to be zero start send few null 4 byte
+ frame_state <= send_frame_state_lp_wait2;
+ end
+
+ send_frame_state_lp_wait2: begin //7th falling edege of byte_clk, now enable data input mux tristate to be zero start send few null 4 byte
+ frame_state <= send_frame_state_enable_hs;
+ end
+ send_frame_state_enable_hs: begin //8th- 12th falling edge
+ hs_data_tristate_r <= 1'b0; //tristate hs data
+ hs_clock_tristate_r <= 1'b0; //tristate hs clock
+ frame_state <= send_frame_state_send_preamble;
+ zeros_count <= 8'h4;
+ end
+ send_frame_state_send_preamble:begin //send zeros
+ zeros_count <= zeros_count - 1'h1;
+ if (!zeros_count)
+ begin
+ frame_state <= send_frame_state_send_rom;
+ data_zero <= 1'b0; //ROM samples addr on rising edge , by the time we get to next state correct data will be avilable
+ rom_addr_r <= rom_addr_r + 1'b1; //increse rom address
+ rom_count <= rom_count - 1'b1;
+ end
+ end
+ send_frame_state_send_rom: begin
+ rom_count <= rom_count - 1'b1;
+ rom_addr_r <= rom_addr_r + 1'b1; //increse rom address
+ if (!rom_count)
+ begin
+ if (fifo_count )
+ begin
+ data_from_rom_nfifo <= 1'b0;
+ fifo_count <= fifo_count - 1'h1;
+ //fifo_read_en <= !fifo_empty; //enable fifo right now sothat data becomes available by next falling edge of byte clock , if fifo some how empty , keep it disable
+ frame_state <= send_frame_state_send_fifo;
+ end
+ else
+ begin
+ data_zero <= 1'b1;
+ zeros_count <= 8'h5; //2 byte of crc (1byte transmits on state transition ) + 4 byte 0
+ frame_state <= send_frame_state_send_crc;
+ end
+ end
+ else
+ begin
+ if (rom_count == 9'h1 && fifo_count) // because need to get rid of first command byte off fifo
+ begin
+ fifo_read_en <= !fifo_empty; //enable fifo right now sothat data becomes available by next falling edge of byte clock , if fifo some how empty , keep it disable
+ end
+ end
+ end
+
+ send_frame_state_send_fifo: begin //wait till trans finish start sending fifo if not empty or skip this state on cmmand
+
+ fifo_count <= fifo_count - 1'h1;
+
+ //fifo_empty_reg <= fifo_empty; //to get last byte out of fifo
+
+ if (!fifo_count || fifo_empty)
+ begin
+
+ fifo_read_en <= 1'b0;
+ data_zero <= 1'b1;
+ zeros_count <= 4'h4 + fifo_count; //if any fifo_count is pending but fifo gone empty , pad it with zeros 2 byte of crc (1byte transmits on state transition ) + 4 byte 0
+ frame_state <= send_frame_state_send_crc;
+ end
+ end
+
+ send_frame_state_send_crc: begin //if 00 00 ff nesessry then use rom
+ zeros_count <= zeros_count - 1'h1;
+ if (!zeros_count)
+ begin
+ frame_state <= send_frame_state_finish;
+ end
+ end
+ send_frame_state_finish: begin
+ if (!write_cmd_i)
+ begin
+ frame_state <= send_frame_state_idle;
+ end
+ end
+ default: begin
+ frame_state <= send_frame_state_idle;
+ end
+
+ endcase
+
+ end
+end
+
+endmodule
\ No newline at end of file
diff --git a/FPGA/Soruce/spi_slave.v b/FPGA/Soruce/spi_slave.v
new file mode 100644
index 0000000..57ff70e
--- /dev/null
+++ b/FPGA/Soruce/spi_slave.v
@@ -0,0 +1,116 @@
+/*
+ * File: spi_slave.v
+ * Author: Gaurav
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+//Data change on falling edge sample on rising edge , Spi clk default low
+
+module SPI_SLAVE (clk_i, rst_i, rx_data_o, byte_clock_o, spi_clk_i, spi_mosi_i, spi_csn_i);
+
+input clk_i; //system clock
+input rst_i; //reset input
+output reg [7:0]rx_data_o; //received over MOSI
+output reg byte_clock_o; //byte clock goes high when new data on rx_data_o
+
+input spi_clk_i; //spi clock
+input spi_mosi_i; //spi mosi (rx)
+input spi_csn_i; //spi cs, active low
+
+reg [7:0]rx_data;
+reg spi_byte_clk_r;
+
+reg [7:0] rx_reg_r; //rx shift reg
+reg [2:0] rx_bit_count_r; //count rx
+
+reg spi_miso_r;
+reg spi_byte_clock_r1;
+reg spi_byte_clock_r2;
+reg spi_byte_clock_r3;
+reg spi_byte_clock_r4;
+
+wire spi_clk_w;
+
+assign spi_clk_w = spi_csn_i? 1'b0: spi_clk_i;
+
+always @(posedge rst_i or posedge clk_i) //cross over to FPGA clock domain
+begin
+ if (rst_i)
+ begin
+ byte_clock_o <= 1'b0;
+ spi_byte_clock_r1 <= 1'b0;
+ spi_byte_clock_r2 <= 1'b0;
+ spi_byte_clock_r3 <= 1'b0;
+ spi_byte_clock_r4 <= 1'b0;
+
+ end
+ else
+ begin
+
+ spi_byte_clock_r1 <= spi_byte_clk_r;
+ spi_byte_clock_r2 <= spi_byte_clock_r1;
+ spi_byte_clock_r3 <= spi_byte_clock_r2;
+ spi_byte_clock_r4 <= spi_byte_clock_r3;
+
+ if ( !spi_byte_clock_r4 && spi_byte_clock_r3)
+ begin
+ byte_clock_o <= 1'b0;
+ rx_data_o <= rx_data;
+ end
+ else
+ begin
+ byte_clock_o <= 1'b1;
+ end
+ end
+end
+
+
+always @(posedge rst_i or posedge spi_clk_w or posedge spi_csn_i)
+begin
+
+ if (rst_i)
+ begin
+ spi_byte_clk_r <= 1'b0;
+ rx_bit_count_r <= 3'b0;
+ rx_data <= 0;
+ end
+ else
+ begin
+
+ if (spi_csn_i)
+ begin
+ rx_bit_count_r <= 3'b0;
+ //spi_byte_clk_r <= 1'b0;
+ end
+ else
+ begin
+ rx_bit_count_r <= rx_bit_count_r + 1'b1;
+ rx_reg_r <= {rx_reg_r[6:0], spi_mosi_i};
+
+ if (rx_bit_count_r == 3'h7)
+ begin
+ rx_data <= {rx_reg_r[6:0], spi_mosi_i};
+ spi_byte_clk_r <= 1'b1;
+ end
+ else if (rx_bit_count_r == 3'h3)
+ begin
+ spi_byte_clk_r <= 1'b0;
+ end
+ end
+ end
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA/Soruce/tb_send_frame.v b/FPGA/Soruce/tb_send_frame.v
new file mode 100644
index 0000000..8dba67d
--- /dev/null
+++ b/FPGA/Soruce/tb_send_frame.v
@@ -0,0 +1,148 @@
+/*
+ * File: tb_spi_bridge.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+`timescale 1 ns / 1 ns
+
+module testbenc;
+
+parameter CLK_PERIOD = 1000;
+
+ wire reset_g;
+ reg reset_i;
+ reg [7:0] command_r;
+ reg write_cmd;
+ reg pll_clk_p;
+ reg pll_clk_s;
+ reg pll_clk_s2;
+ reg almost_empty;
+ reg fifo_empty_w;
+ reg [7:0]fifo_out;
+
+ wire tx_finish_w;
+ wire fifo_read_en_w;
+ wire buf_clkout_lp_p_o;
+ wire buf_clkout_lp_n_o;
+ wire buf_dout_lp_p_o;
+ wire buf_dout_lp_n_o;
+ wire byte_clock_o;
+ wire hs_data_o;
+ wire hs_clock_o;
+ wire [7:0]debug1;
+ wire [7:0]debug2;
+
+parameter CMD_LCD_INIT = 8'h89; //from ROM 13th line
+parameter CMD_LCD_TP_FIRST = 8'hCF; //line 17
+parameter CMD_LCD_WRITE_LINE_FIRST = 8'h3F; //line
+parameter CMD_LCD_WRITE_LINE_NEXT = 8'h6B;
+parameter CMD_LCD_TP_NEXT = 8'hD9; //line 18
+parameter DISPLAY_LINE_MAX = 8'd240;
+
+GSR GSR_INST (.GSR (reset_g));
+PUR PUR_INST (.PUR (reset_g));
+
+DPHY_TX_BYTE dphy_tx_byte(
+ .reset_i(reset_i), //reset active high
+ .command_i(command_r),
+ .write_cmd_i(write_cmd),
+ .clockp_fast_data_i(pll_clk_p), //fast clokc input for mipi data
+ .clocks_fast_clk_i(pll_clk_s), //fast clock input for mipi clok
+ .clock_slow_sync_i(pll_clk_s2), //slow clock for sync
+ .lock_chk_i(1'b1), //pll lock check
+ .fifo_almost_empty(almost_empty),
+ .fifo_empty(fifo_empty_w),
+ .data_i(fifo_out), //mipi data input from FIFO
+
+ .finish_o(tx_finish_w),
+ .fifo_read_en(fifo_read_en_w),
+ .buf_clkout_lp_p_o(buf_clkout_lp_p_o), //mipi clock lp0 out
+ .buf_clkout_lp_n_o(buf_clkout_lp_n_o), //mipi clock lp1 out
+ .buf_dout_lp_p_o(buf_dout_lp_p_o), //data lp0 out
+ .buf_dout_lp_n_o(buf_dout_lp_n_o), //data lp1 out
+ .byte_clock_o(byte_clock_o), //byte clock out
+ .hs_data_o(hs_data_o), //mipi data out
+ .hs_clock_o(hs_clock_o), //mipi clock out
+ .debug_out(debug1),//debug_out),
+ .debug_adr(debug2));//debug_adr));
+
+
+
+initial begin //genrate 90 phase clock and slow sync clock
+ pll_clk_p = 1'b0;
+ pll_clk_s = 1'b0;
+ pll_clk_s2 = 1'b0;
+end
+always begin
+ #(CLK_PERIOD/2.0) pll_clk_p = ~pll_clk_p;
+
+end
+always begin
+ #(CLK_PERIOD/4.0)
+ forever #(CLK_PERIOD/2.0) pll_clk_s = ~pll_clk_s;
+end
+always begin
+ #(CLK_PERIOD*4.0) pll_clk_s2 = ~pll_clk_s2;
+end
+
+reg [7:0]line_counter;
+initial begin
+ reset_i = 1'b0;
+ write_cmd = 1'b0;
+ almost_empty = 1'b0;
+ fifo_empty_w = 1'b0;
+ fifo_out = 8'h8C;
+ line_counter = DISPLAY_LINE_MAX;
+ command_r = CMD_LCD_INIT;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #500000
+ while (tx_finish_w == 1'b0)
+ begin
+ end
+
+ command_r = CMD_LCD_WRITE_LINE_FIRST;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #5000000
+ while (tx_finish_w == 1'b0)
+ begin
+ end
+
+ while (line_counter)
+ begin
+ command_r = CMD_LCD_WRITE_LINE_NEXT;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #5000000
+ while (tx_finish_w == 1'b0)
+ begin
+
+ end
+ line_counter = line_counter - 1'b1;
+ end
+
+ $finish;
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA/Soruce/tb_spi_bridge.v b/FPGA/Soruce/tb_spi_bridge.v
new file mode 100644
index 0000000..2a475a3
--- /dev/null
+++ b/FPGA/Soruce/tb_spi_bridge.v
@@ -0,0 +1,146 @@
+/*
+ * File: tb_spi_bridge.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+`timescale 1ns / 1ns
+
+module test_bench_spi;
+
+parameter CLK_PERIOD = 2;
+parameter SPI_CLK_PERIOD = 2;
+ reg clock;
+ reg spi_clock;
+ reg spi_data;
+ reg spi_cs;
+reg nsys_reset;
+wire hs_clock_o;
+wire hs_data_o;
+wire buf_clkout_lp_n_o;
+wire buf_clkout_lp_p_o;
+wire buf_dout_lp_n_o;
+wire buf_dout_lp_p_o;
+wire byte_clock_o;
+wire tx_ready_o;
+wire write_to_fifo;
+wire read_from_fifo_w;
+wire reg_1v8_en;
+wire reg_3v0_en;
+wire lcd_rst;
+wire bl_en;
+wire spi_miso_o;
+
+wire reset_g;
+GSR GSR_INST (.GSR (reset_g));
+PUR PUR_INST (.PUR (reset_g));
+
+counter counter_ins(nsys_reset, clock, hs_clock_o, hs_data_o , buf_clkout_lp_n_o, buf_clkout_lp_p_o, buf_dout_lp_n_o,
+ buf_dout_lp_p_o, byte_clock_o, tx_ready_o, write_to_fifo,read_from_fifo_w,
+ reg_1v8_en, reg_3v0_en, lcd_rst, bl_en, spi_miso_o, spi_data, spi_cs, spi_clock, 1'b1);
+
+initial begin
+ clock = 1'b0;
+ spi_clock = 1'b0;
+ spi_data = 1'b0;
+ spi_cs = 1'b1;
+end
+
+
+always begin
+ #(CLK_PERIOD/2) clock = ~clock;
+end
+
+task send_byte;
+ input [7:0] data;
+ reg [4:0] i = 4'b0;
+ begin
+
+ for(i = 4'b0; i< 4'h8; i = i+1) begin
+ spi_data = data[(8'h7-i)];
+ #(SPI_CLK_PERIOD/2.0)
+ spi_clock = 1'b1;
+ #(SPI_CLK_PERIOD/2.0)
+ spi_clock = 1'b0;
+ end
+ end
+endtask
+
+task send_line;
+ input [7:0]command;
+ input data_in;
+ reg [7:0]data;
+ reg [8:0]i;
+ begin
+ spi_cs = 1'b0;
+ #100
+ data = data_in;
+ send_byte(command);
+ for(i= 9'b0; i < 480; i = i + 1'b1) begin
+ #2
+ send_byte(data);
+ data=data+1'b1;
+ end
+ #100
+ spi_cs = 1'b1;
+ end
+endtask
+
+task send_line_short; //Error Condition
+ input [7:0]command;
+ input [7:0]data_in;
+ reg [7:0]data;
+ reg [8:0]i;
+ begin
+ spi_cs = 1'b0;
+ data = data_in;
+ send_byte(command);
+ for(i= 9'b0; i < 30; i = i + 1'b1) begin
+ #2
+ send_byte(data);
+ data=data+1'b1;
+ end
+ #100
+ spi_cs = 1'b1;
+ end
+endtask
+
+
+task send_frame;
+ input [7:0]dummy;
+ reg [8:0]i;
+ begin
+ send_line(8'h3F, dummy);
+ for ( i= 9'h0; i<239; i = i + 1'h1)begin
+ #1000
+ send_line_short(8'h6B, dummy);
+ end
+
+
+
+ end
+endtask
+
+initial
+begin
+ nsys_reset = 1'b0;
+ #20
+ nsys_reset = 1'b1;
+ #125000
+ send_frame(8'h00);
+ #5000
+
+ $finish;
+end
+endmodule
\ No newline at end of file
diff --git a/FPGA/Test_bench/tb_send_frame.v b/FPGA/Test_bench/tb_send_frame.v
new file mode 100644
index 0000000..8dba67d
--- /dev/null
+++ b/FPGA/Test_bench/tb_send_frame.v
@@ -0,0 +1,148 @@
+/*
+ * File: tb_spi_bridge.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+`timescale 1 ns / 1 ns
+
+module testbenc;
+
+parameter CLK_PERIOD = 1000;
+
+ wire reset_g;
+ reg reset_i;
+ reg [7:0] command_r;
+ reg write_cmd;
+ reg pll_clk_p;
+ reg pll_clk_s;
+ reg pll_clk_s2;
+ reg almost_empty;
+ reg fifo_empty_w;
+ reg [7:0]fifo_out;
+
+ wire tx_finish_w;
+ wire fifo_read_en_w;
+ wire buf_clkout_lp_p_o;
+ wire buf_clkout_lp_n_o;
+ wire buf_dout_lp_p_o;
+ wire buf_dout_lp_n_o;
+ wire byte_clock_o;
+ wire hs_data_o;
+ wire hs_clock_o;
+ wire [7:0]debug1;
+ wire [7:0]debug2;
+
+parameter CMD_LCD_INIT = 8'h89; //from ROM 13th line
+parameter CMD_LCD_TP_FIRST = 8'hCF; //line 17
+parameter CMD_LCD_WRITE_LINE_FIRST = 8'h3F; //line
+parameter CMD_LCD_WRITE_LINE_NEXT = 8'h6B;
+parameter CMD_LCD_TP_NEXT = 8'hD9; //line 18
+parameter DISPLAY_LINE_MAX = 8'd240;
+
+GSR GSR_INST (.GSR (reset_g));
+PUR PUR_INST (.PUR (reset_g));
+
+DPHY_TX_BYTE dphy_tx_byte(
+ .reset_i(reset_i), //reset active high
+ .command_i(command_r),
+ .write_cmd_i(write_cmd),
+ .clockp_fast_data_i(pll_clk_p), //fast clokc input for mipi data
+ .clocks_fast_clk_i(pll_clk_s), //fast clock input for mipi clok
+ .clock_slow_sync_i(pll_clk_s2), //slow clock for sync
+ .lock_chk_i(1'b1), //pll lock check
+ .fifo_almost_empty(almost_empty),
+ .fifo_empty(fifo_empty_w),
+ .data_i(fifo_out), //mipi data input from FIFO
+
+ .finish_o(tx_finish_w),
+ .fifo_read_en(fifo_read_en_w),
+ .buf_clkout_lp_p_o(buf_clkout_lp_p_o), //mipi clock lp0 out
+ .buf_clkout_lp_n_o(buf_clkout_lp_n_o), //mipi clock lp1 out
+ .buf_dout_lp_p_o(buf_dout_lp_p_o), //data lp0 out
+ .buf_dout_lp_n_o(buf_dout_lp_n_o), //data lp1 out
+ .byte_clock_o(byte_clock_o), //byte clock out
+ .hs_data_o(hs_data_o), //mipi data out
+ .hs_clock_o(hs_clock_o), //mipi clock out
+ .debug_out(debug1),//debug_out),
+ .debug_adr(debug2));//debug_adr));
+
+
+
+initial begin //genrate 90 phase clock and slow sync clock
+ pll_clk_p = 1'b0;
+ pll_clk_s = 1'b0;
+ pll_clk_s2 = 1'b0;
+end
+always begin
+ #(CLK_PERIOD/2.0) pll_clk_p = ~pll_clk_p;
+
+end
+always begin
+ #(CLK_PERIOD/4.0)
+ forever #(CLK_PERIOD/2.0) pll_clk_s = ~pll_clk_s;
+end
+always begin
+ #(CLK_PERIOD*4.0) pll_clk_s2 = ~pll_clk_s2;
+end
+
+reg [7:0]line_counter;
+initial begin
+ reset_i = 1'b0;
+ write_cmd = 1'b0;
+ almost_empty = 1'b0;
+ fifo_empty_w = 1'b0;
+ fifo_out = 8'h8C;
+ line_counter = DISPLAY_LINE_MAX;
+ command_r = CMD_LCD_INIT;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #500000
+ while (tx_finish_w == 1'b0)
+ begin
+ end
+
+ command_r = CMD_LCD_WRITE_LINE_FIRST;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #5000000
+ while (tx_finish_w == 1'b0)
+ begin
+ end
+
+ while (line_counter)
+ begin
+ command_r = CMD_LCD_WRITE_LINE_NEXT;
+ #50000
+ write_cmd = 1'b1;
+ #5000
+ write_cmd = 1'b0;
+ #5000000
+ while (tx_finish_w == 1'b0)
+ begin
+
+ end
+ line_counter = line_counter - 1'b1;
+ end
+
+ $finish;
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA/Test_bench/tb_spi_bridge.v b/FPGA/Test_bench/tb_spi_bridge.v
new file mode 100644
index 0000000..011d459
--- /dev/null
+++ b/FPGA/Test_bench/tb_spi_bridge.v
@@ -0,0 +1,147 @@
+/*
+ * File: tb_spi_bridge.v
+ * Copyright: Gaurav Singh
+ * website: www.circuitvalley.com
+ * Created on Jan 19, 2020, 1:33 AM
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ * Email: gauravsingh@circuitvalley.com
+************************************************************************/
+
+`timescale 1ns / 1ns
+
+module test_bench_spi;
+
+parameter CLK_PERIOD = 2;
+parameter SPI_CLK_PERIOD = 2;
+ reg clock;
+ reg spi_clock;
+ reg spi_data;
+ reg spi_cs;
+reg nsys_reset;
+wire hs_clock_o;
+wire hs_data_o;
+wire buf_clkout_lp_n_o;
+wire buf_clkout_lp_p_o;
+wire buf_dout_lp_n_o;
+wire buf_dout_lp_p_o;
+wire byte_clock_o;
+wire tx_ready_o;
+wire write_to_fifo;
+wire read_from_fifo_w;
+wire reg_1v8_en;
+wire reg_3v0_en;
+wire lcd_rst;
+wire bl_en;
+wire spi_miso_o;
+
+wire reset_g;
+GSR GSR_INST (.GSR (reset_g));
+PUR PUR_INST (.PUR (reset_g));
+
+counter counter_ins(nsys_reset, clock, hs_clock_o, hs_data_o , buf_clkout_lp_n_o, buf_clkout_lp_p_o, buf_dout_lp_n_o,
+ buf_dout_lp_p_o, byte_clock_o, tx_ready_o, write_to_fifo,read_from_fifo_w,
+ reg_1v8_en, reg_3v0_en, lcd_rst, bl_en, spi_miso_o, spi_data, spi_cs, spi_clock, 1'b1);
+
+initial begin
+ clock = 1'b0;
+ spi_clock = 1'b0;
+ spi_data = 1'b0;
+ spi_cs = 1'b1;
+end
+
+
+always begin
+ #(CLK_PERIOD/2) clock = ~clock;
+end
+
+task send_byte;
+ input [7:0] data;
+ reg [4:0] i = 4'b0;
+ begin
+
+ for(i = 4'b0; i< 4'h8; i = i+1) begin
+ spi_data = data[(8'h7-i)];
+ #(SPI_CLK_PERIOD/2.0)
+ spi_clock = 1'b1;
+ #(SPI_CLK_PERIOD/2.0)
+ spi_clock = 1'b0;
+ end
+ end
+endtask
+
+task send_line;
+ input [7:0]command;
+ input data_in;
+ reg [7:0]data;
+ reg [8:0]i;
+ begin
+ spi_cs = 1'b0;
+ #100
+ data = data_in;
+ send_byte(command);
+ for(i= 9'b0; i < 480; i = i + 1'b1) begin
+ #2
+ send_byte(data);
+ data=data+1'b1;
+ end
+ #100
+ spi_cs = 1'b1;
+ end
+endtask
+
+task send_line_short; //Error Condition
+ input [7:0]command;
+ input [7:0]data_in;
+ reg [7:0]data;
+ reg [8:0]i;
+ begin
+ spi_cs = 1'b0;
+ data = data_in;
+ send_byte(command);
+ for(i= 9'b0; i < 30; i = i + 1'b1) begin
+ #2
+ send_byte(data);
+ data=data+1'b1;
+ end
+ #100
+ spi_cs = 1'b1;
+ end
+endtask
+
+
+task send_frame;
+ input [7:0]dummy;
+ reg [8:0]i;
+ begin
+ send_line(8'h3F, dummy);
+ for ( i= 9'h0; i<239; i = i + 1'h1)begin
+ #1000
+ send_line_short(8'h6B, dummy);
+ end
+
+
+
+ end
+endtask
+
+initial
+begin
+ nsys_reset = 1'b0;
+ #20
+ nsys_reset = 1'b1;
+ #125000
+ send_frame(8'h00);
+ #5000
+
+ $finish;
+end
+endmodule
\ No newline at end of file