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mipi_dsi_bridge_fpga
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Update mipi_dsi_bridge.v

master
Gaurav Singh 2020-01-19 15:38:00 +01:00 committed by GitHub
parent 3fa450f6b1
commit a8d74f5e3a
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1 changed files with 0 additions and 2 deletions
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FPGA/Soruce/mipi_dsi_bridge.v
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@ -27,7 +27,6 @@ module mipi_dsi_bridge(nsys_reset, clk,
reg_3v0_en, reg_3v0_en,
lcd_rst, lcd_rst,
bl_en, bl_en,
spi_miso_o,
spi_mosi_i, spi_mosi_i,
spi_csn_i, spi_csn_i,
spi_clk_i, spi_clk_i,
@ -37,7 +36,6 @@ output reg reg_1v8_en;
output reg reg_3v0_en; output reg reg_3v0_en;
output reg lcd_rst; output reg lcd_rst;
output reg bl_en; output reg bl_en;
output spi_miso_o;
output hs_clock_o; output hs_clock_o;
output hs_data_o; output hs_data_o;
output wire buf_clkout_lp_n_o ; output wire buf_clkout_lp_n_o ;