mipi_dsi_bridge_fpga/FPGA/Source/PLL.lpc

88 lines
1.4 KiB
Plaintext

[Device]
Family=machxo3lf
PartType=LCMXO3LF-6900C
PartName=LCMXO3LF-6900C-5BG256C
SpeedGrade=5
Package=CABGA256
OperatingCondition=COM
Status=S
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
ModuleName=PLL
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=01/14/2020
Time=21:29:07
[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
mode=Frequency
CLKI=12
CLKI_DIV=1
BW=1.146
VCO=480.000
fb_mode=CLKOP
CLKFB_DIV=8
FRACN_ENABLE=0
FRACN_DIV=0
DynamicPhase=STATIC
ClkEnable=0
Standby=0
Enable_sel=0
PLLRst=0
PLLMRst=0
ClkOS2Rst=0
ClkOS3Rst=0
LockSig=0
LockStk=0
WBProt=0
OPBypass=0
OPUseDiv=0
CLKOP_DIV=5
FREQ_PIN_CLKOP=96
OP_Tol=0.0
CLKOP_AFREQ=96.000000
CLKOP_PHASEADJ=0
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=1
OSBypass=0
OSUseDiv=0
CLKOS_DIV=5
FREQ_PIN_CLKOS=96
OS_Tol=0.0
CLKOS_AFREQ=96.000000
CLKOS_PHASEADJ=90
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=1
OS2Bypass=0
OS2UseDiv=0
CLKOS2_DIV=10
FREQ_PIN_CLKOS2=48
OS2_Tol=0.0
CLKOS2_AFREQ=48.000000
CLKOS2_PHASEADJ=0
EnCLKOS3=0
OS3Bypass=0
OS3UseDiv=0
CLKOS3_DIV=1
FREQ_PIN_CLKOS3=48
OS3_Tol=0.0
CLKOS3_AFREQ=48.000000
CLKOS3_PHASEADJ=0
[Command]
cmd_line= -w -n PLL -lang verilog -synth lse -arch xo3c00f -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -fclkos 96 -fclkos_tol 0.0 -fclkos2 48 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 1