116 lines
2.8 KiB
Verilog
116 lines
2.8 KiB
Verilog
/*
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* File: spi_slave.v
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* Author: Gaurav
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* website: www.circuitvalley.com
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* Created on Jan 19, 2020, 1:33 AM
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* Email: gauravsingh@circuitvalley.com
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************************************************************************/
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//Data change on falling edge sample on rising edge , Spi clk default low
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module SPI_SLAVE (clk_i, rst_i, rx_data_o, byte_clock_o, spi_clk_i, spi_mosi_i, spi_csn_i);
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input clk_i; //system clock
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input rst_i; //reset input
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output reg [7:0]rx_data_o; //received over MOSI
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output reg byte_clock_o; //byte clock goes high when new data on rx_data_o
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input spi_clk_i; //spi clock
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input spi_mosi_i; //spi mosi (rx)
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input spi_csn_i; //spi cs, active low
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reg [7:0]rx_data;
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reg spi_byte_clk_r;
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reg [7:0] rx_reg_r; //rx shift reg
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reg [2:0] rx_bit_count_r; //count rx
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reg spi_miso_r;
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reg spi_byte_clock_r1;
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reg spi_byte_clock_r2;
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reg spi_byte_clock_r3;
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reg spi_byte_clock_r4;
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wire spi_clk_w;
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assign spi_clk_w = spi_csn_i? 1'b0: spi_clk_i;
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always @(posedge rst_i or posedge clk_i) //cross over to FPGA clock domain
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begin
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if (rst_i)
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begin
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byte_clock_o <= 1'b0;
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spi_byte_clock_r1 <= 1'b0;
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spi_byte_clock_r2 <= 1'b0;
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spi_byte_clock_r3 <= 1'b0;
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spi_byte_clock_r4 <= 1'b0;
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end
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else
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begin
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spi_byte_clock_r1 <= spi_byte_clk_r;
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spi_byte_clock_r2 <= spi_byte_clock_r1;
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spi_byte_clock_r3 <= spi_byte_clock_r2;
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spi_byte_clock_r4 <= spi_byte_clock_r3;
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if ( !spi_byte_clock_r4 && spi_byte_clock_r3)
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begin
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byte_clock_o <= 1'b0;
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rx_data_o <= rx_data;
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end
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else
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begin
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byte_clock_o <= 1'b1;
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end
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end
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end
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always @(posedge rst_i or posedge spi_clk_w or posedge spi_csn_i)
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begin
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if (rst_i)
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begin
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spi_byte_clk_r <= 1'b0;
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rx_bit_count_r <= 3'b0;
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rx_data <= 0;
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end
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else
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begin
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if (spi_csn_i)
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begin
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rx_bit_count_r <= 3'b0;
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//spi_byte_clk_r <= 1'b0;
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end
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else
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begin
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rx_bit_count_r <= rx_bit_count_r + 1'b1;
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rx_reg_r <= {rx_reg_r[6:0], spi_mosi_i};
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if (rx_bit_count_r == 3'h7)
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begin
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rx_data <= {rx_reg_r[6:0], spi_mosi_i};
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spi_byte_clk_r <= 1'b1;
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end
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else if (rx_bit_count_r == 3'h3)
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begin
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spi_byte_clk_r <= 1'b0;
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end
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end
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end
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end
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endmodule |