148 lines
3.8 KiB
Verilog
148 lines
3.8 KiB
Verilog
/*
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* File: tb_spi_bridge.v
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* Copyright: Gaurav Singh
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* website: www.circuitvalley.com
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* Created on Jan 19, 2020, 1:33 AM
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* Email: gauravsingh@circuitvalley.com
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************************************************************************/
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`timescale 1 ns / 1 ns
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module testbenc;
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parameter CLK_PERIOD = 1000;
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wire reset_g;
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reg reset_i;
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reg [7:0] command_r;
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reg write_cmd;
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reg pll_clk_p;
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reg pll_clk_s;
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reg pll_clk_s2;
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reg almost_empty;
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reg fifo_empty_w;
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reg [7:0]fifo_out;
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wire tx_finish_w;
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wire fifo_read_en_w;
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wire buf_clkout_lp_p_o;
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wire buf_clkout_lp_n_o;
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wire buf_dout_lp_p_o;
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wire buf_dout_lp_n_o;
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wire byte_clock_o;
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wire hs_data_o;
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wire hs_clock_o;
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wire [7:0]debug1;
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wire [7:0]debug2;
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parameter CMD_LCD_INIT = 8'h89; //from ROM 13th line
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parameter CMD_LCD_TP_FIRST = 8'hCF; //line 17
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parameter CMD_LCD_WRITE_LINE_FIRST = 8'h3F; //line
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parameter CMD_LCD_WRITE_LINE_NEXT = 8'h6B;
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parameter CMD_LCD_TP_NEXT = 8'hD9; //line 18
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parameter DISPLAY_LINE_MAX = 8'd240;
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GSR GSR_INST (.GSR (reset_g));
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PUR PUR_INST (.PUR (reset_g));
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DPHY_TX_BYTE dphy_tx_byte(
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.reset_i(reset_i), //reset active high
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.command_i(command_r),
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.write_cmd_i(write_cmd),
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.clockp_fast_data_i(pll_clk_p), //fast clokc input for mipi data
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.clocks_fast_clk_i(pll_clk_s), //fast clock input for mipi clok
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.clock_slow_sync_i(pll_clk_s2), //slow clock for sync
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.lock_chk_i(1'b1), //pll lock check
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.fifo_almost_empty(almost_empty),
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.fifo_empty(fifo_empty_w),
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.data_i(fifo_out), //mipi data input from FIFO
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.finish_o(tx_finish_w),
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.fifo_read_en(fifo_read_en_w),
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.buf_clkout_lp_p_o(buf_clkout_lp_p_o), //mipi clock lp0 out
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.buf_clkout_lp_n_o(buf_clkout_lp_n_o), //mipi clock lp1 out
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.buf_dout_lp_p_o(buf_dout_lp_p_o), //data lp0 out
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.buf_dout_lp_n_o(buf_dout_lp_n_o), //data lp1 out
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.byte_clock_o(byte_clock_o), //byte clock out
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.hs_data_o(hs_data_o), //mipi data out
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.hs_clock_o(hs_clock_o), //mipi clock out
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.debug_out(debug1),//debug_out),
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.debug_adr(debug2));//debug_adr));
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initial begin //genrate 90 phase clock and slow sync clock
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pll_clk_p = 1'b0;
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pll_clk_s = 1'b0;
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pll_clk_s2 = 1'b0;
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end
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always begin
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#(CLK_PERIOD/2.0) pll_clk_p = ~pll_clk_p;
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end
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always begin
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#(CLK_PERIOD/4.0)
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forever #(CLK_PERIOD/2.0) pll_clk_s = ~pll_clk_s;
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end
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always begin
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#(CLK_PERIOD*4.0) pll_clk_s2 = ~pll_clk_s2;
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end
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reg [7:0]line_counter;
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initial begin
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reset_i = 1'b0;
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write_cmd = 1'b0;
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almost_empty = 1'b0;
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fifo_empty_w = 1'b0;
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fifo_out = 8'h8C;
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line_counter = DISPLAY_LINE_MAX;
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command_r = CMD_LCD_INIT;
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#50000
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write_cmd = 1'b1;
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#5000
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write_cmd = 1'b0;
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#500000
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while (tx_finish_w == 1'b0)
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begin
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end
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command_r = CMD_LCD_WRITE_LINE_FIRST;
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#50000
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write_cmd = 1'b1;
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#5000
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write_cmd = 1'b0;
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#5000000
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while (tx_finish_w == 1'b0)
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begin
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end
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while (line_counter)
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begin
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command_r = CMD_LCD_WRITE_LINE_NEXT;
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#50000
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write_cmd = 1'b1;
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#5000
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write_cmd = 1'b0;
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#5000000
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while (tx_finish_w == 1'b0)
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begin
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end
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line_counter = line_counter - 1'b1;
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end
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$finish;
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end
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endmodule |