Gaurav Singh 58c89ef5d4 Update tb_spi_bridge.v		2020-01-19 16:05:52 +01:00
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DDR.lpc	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
DDR_MIPI.ipx	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
DDR_MIPI.lpc	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
DDR_MIPI.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
FIFo.ipx	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
FIFo.lpc	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
FIFo.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
PLL.ipx	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
PLL.lpc	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
PLL.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
ROM.ipx	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
ROM.lpc	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
ROM.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
Read_me.txt	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
mipi_dsi_bridge.ldf	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
mipi_dsi_bridge.lpf	Update mipi_dsi_bridge.lpf	2020-01-19 15:42:09 +01:00
mipi_dsi_bridge.v	Update mipi_dsi_bridge.v	2020-01-19 15:38:00 +01:00
rom.mem	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
send_mipi_frame.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
spi_slave.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
tb_send_frame.v	Added FPGA Verilog source and Test bench	2020-01-19 04:42:52 +01:00
tb_spi_bridge.v	Update tb_spi_bridge.v	2020-01-19 16:05:52 +01:00