57 lines
948 B
Plaintext
57 lines
948 B
Plaintext
[Device]
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Family=machxo3lf
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PartType=LCMXO3LF-6900C
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PartName=LCMXO3LF-6900C-5BG256C
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SpeedGrade=5
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Package=CABGA256
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OperatingCondition=COM
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=DDR_GENERIC
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CoreRevision=6.0
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ModuleName=DDR
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SourceFormat=Verilog HDL
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ParameterFileVersion=1.0
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Date=09/08/2019
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Time=10:33:27
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[Parameters]
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Verilog=1
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VHDL=0
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EDIF=1
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Destination=Synplicity
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Expression=BusA(0 to 7)
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Order=Big Endian [MSB:LSB]
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IO=0
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mode=
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trioddr=0
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highspeed=0
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io_type=
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num_int=
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width=
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freq_in=
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bandwidth=
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aligned=
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pre-configuration=DISABLED
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mode2=Transmit
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trioddr2=0
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highspeed2=0
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io_type2=LVDS25
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freq_in2=96
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gear=4x
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aligned2=Edge-to-Edge
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num_int2=2
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width2=1
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Interface=GDDRX4_TX.ECLK.Aligned
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Delay=Bypass
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DelVal=
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UsePll=
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GenPll=0
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[Command]
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cmd_line= -w -n DDR -lang verilog -synth lse -bus_exp 7 -bb -arch xo3c00f -type iol -mode out -io_type LVDS25 -width 1 -freq_in 96 -gear 4 -clk eclk -aligned -del -1
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