169 lines
6.1 KiB
Verilog
169 lines
6.1 KiB
Verilog
/*
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* File: tb_spi_bridge.v
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* Copyright: Gaurav Singh
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* website: www.circuitvalley.com
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* Created on Jan 19, 2020, 1:33 AM
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* Email: gauravsingh@circuitvalley.com
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************************************************************************/
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`timescale 1 ns / 1 ps
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module DDR_MIPI (clkout_lp0_i, buf_clkout_lp0_o,
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clkout_lp1_i, buf_clkout_lp1_o,
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clock_slow_i, clockp_fast_data_i,
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clocks_fast_clk_i, mipi_clock_o,
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lock_chk_i, reset_i, byte_clock_o,
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tristate_data_i,tristate_clk_i, tx_ready_o,
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buf_dout_lp0_o, dout_lp0_i,
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buf_dout_lp1_o, dout_lp1_i,
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data_i, mipi_data_o)
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/* synthesis NGD_DRC_MASK=1 */;
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input wire clkout_lp0_i; //lp link for mipi clkp
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input wire clkout_lp1_i; //lp line for mipi clkn
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input wire clock_slow_i; // slow clock for sync
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input wire clockp_fast_data_i; //fast clokc input for mipi data
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input wire clocks_fast_clk_i; //fast clock input for mipi clok
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input wire lock_chk_i; //clock check
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input wire reset_i; //reset active high
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input wire tristate_data_i; //controls HS pin tristate active high
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input wire tristate_clk_i; //controls HS pin tristate active high
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input wire dout_lp0_i; //lp line mipi datap
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input wire dout_lp1_i; //lp line mipi datan
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input wire [7:0] data_i; //mipi data input
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output wire buf_clkout_lp0_o; //mipi clock lp0 out
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output wire buf_clkout_lp1_o; //mipi clock lp1 out
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output wire mipi_clock_o; //mipi clock out
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output wire byte_clock_o; //ddr byte clock output
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output wire tx_ready_o; //After reset, Indicate completion of reset synchronization
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output wire [0:0] buf_dout_lp0_o; //data lp0 out
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output wire [0:0] buf_dout_lp1_o; //data lp1 out
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output wire [0:0] mipi_data_o; //mipi data out
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wire opensync_0;
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wire opensync_1;
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wire opensync_cken;
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wire opensync_2;
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wire buf_clkout;
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wire scuba_vhi;
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wire d70;
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wire d60;
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wire d50;
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wire d40;
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wire d30;
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wire d20;
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wire d10;
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wire d00;
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wire eclkc;
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wire sclk_t;
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wire cdiv1;
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wire scuba_vlo;
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wire eclkd;
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wire xstop;
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wire xstart;
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wire opensync_3;
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wire tristate_data_o;
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wire tristate_clk_o;
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wire buf_douto0;
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defparam LUT4_1.initval = 16'h0a78 ;
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ROM16X1A LUT4_1 (.AD3(opensync_0), .AD2(opensync_3), .AD1(lock_chk_i),
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.AD0(scuba_vhi), .DO0(opensync_cken));
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defparam LUT4_0.initval = 16'hfffe ;
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ROM16X1A LUT4_0 (.AD3(opensync_0), .AD2(opensync_1), .AD1(scuba_vlo),
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.AD0(scuba_vlo), .DO0(xstop));
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FD1P3BX FF_3 (.D(opensync_3), .SP(opensync_cken), .CK(clock_slow_i), .PD(reset_i),
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.Q(opensync_0))
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/* synthesis GSR="ENABLED" */;
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FD1P3DX FF_2 (.D(opensync_0), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
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.Q(opensync_1))
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/* synthesis GSR="ENABLED" */;
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FD1P3DX FF_1 (.D(opensync_1), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
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.Q(opensync_2))
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/* synthesis GSR="ENABLED" */;
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FD1P3DX FF_0 (.D(opensync_2), .SP(opensync_cken), .CK(clock_slow_i), .CD(reset_i),
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.Q(opensync_3))
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/* synthesis GSR="ENABLED" */;
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OB Inst1_OB (.I(clkout_lp1_i), .O(buf_clkout_lp1_o));
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OB Inst2_OB (.I(clkout_lp0_i), .O(buf_clkout_lp0_o));
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OB Inst3_OB (.I(dout_lp1_i), .O(buf_dout_lp1_o));
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OB Inst4_OB (.I(dout_lp0_i), .O(buf_dout_lp0_o));
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OFS1P3DX Inst8_OFS1P3DX (.D(tristate_clk_i), .SP(scuba_vhi), .SCLK(sclk_t),
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.CD(reset_i), .Q(tristate_clock_o));
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OFS1P3DX Inst9_OFS1P3DX (.D(tristate_data_i), .SP(scuba_vhi), .SCLK(sclk_t),
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.CD(reset_i), .Q(tristate_data_o));
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OBZ Inst7_OBZ (.I(buf_clkout), .T(tristate_clock_o), .O(mipi_clock_o))
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/* synthesis IO_TYPE="MIPI" */;
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VHI scuba_vhi_inst (.Z(scuba_vhi));
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ODDRX4B Inst6_ODDRX4B (.D0(scuba_vhi), .D1(scuba_vlo), .D2(scuba_vhi),
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.D3(scuba_vlo), .D4(scuba_vhi), .D5(scuba_vlo), .D6(scuba_vhi),
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.D7(scuba_vlo), .ECLK(eclkc), .SCLK(sclk_t), .RST(reset_i), .Q(buf_clkout));
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ODDRX4B Inst5_ODDRX4B0 (.D0(d00), .D1(d10), .D2(d20), .D3(d30), .D4(d40),
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.D5(d50), .D6(d60), .D7(d70), .ECLK(eclkd), .SCLK(sclk_t), .RST(reset_i),
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.Q(buf_douto0));
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ECLKSYNCA Inst4_ECLKSYNCA (.ECLKI(clocks_fast_clk_i), .STOP(xstop), .ECLKO(eclkc));
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam Inst3_CLKDIVC.DIV = "4.0" ;
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CLKDIVC Inst3_CLKDIVC (.RST(reset_i), .CLKI(eclkd), .ALIGNWD(scuba_vlo),
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.CDIV1(cdiv1), .CDIVX(sclk_t));
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ECLKSYNCA Inst2_ECLKSYNCA (.ECLKI(clockp_fast_data_i), .STOP(xstop), .ECLKO(eclkd));
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OBZ Inst1_OBZ0 (.I(buf_douto0), .T(tristate_data_o), .O(mipi_data_o[0]))
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/* synthesis IO_TYPE="MIPI" */;
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assign byte_clock_o = sclk_t;
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assign d70 = data_i[7];
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assign d60 = data_i[6];
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assign d50 = data_i[5];
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assign d40 = data_i[4];
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assign d30 = data_i[3];
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assign d20 = data_i[2];
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assign d10 = data_i[1];
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assign d00 = data_i[0];
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assign tx_ready_o = xstart;
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assign xstart = opensync_3;
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// exemplar begin
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// exemplar attribute FF_3 GSR ENABLED
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// exemplar attribute FF_2 GSR ENABLED
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// exemplar attribute FF_1 GSR ENABLED
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// exemplar attribute FF_0 GSR ENABLED
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// exemplar attribute Inst12_BB IO_TYPE MIPI_LP
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// exemplar attribute Inst11_BB IO_TYPE MIPI_LP
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// exemplar attribute Inst10_BB0 IO_TYPE MIPI_LP
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// exemplar attribute Inst9_BB0 IO_TYPE MIPI_LP
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// exemplar attribute Inst7_OBZ IO_TYPE MIPI
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// exemplar attribute Inst1_OBZ0 IO_TYPE MIPI
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// exemplar end
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endmodule
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